DSP Processors

Dr.N.Herald Anantha Rufus

Asso. Professor/ ECE
Vel Tech Rangarajan Dr. Sagunthala R & D
Institute of Science and Technology
 Introduction
• DSP processors are microprocessors designed for
efficient mathematical manipulation of digital signals.
• DSPs tend to run one program, not many programs.
– Hence OSes are much simpler, there is no virtual memory
• DSPs usually run applications with hard real-time
constraints:
– You must account for anything that could happen in a time
slot
• DSPs usually process infinite continuous data streams.
Computer Architectures for signal processing

• A Typical DSP System

 Computer Architectures for signal processing

Need for DSP Architecture

•Harvard Architecture
• Filtering, correlation, •Pipelining
FFT •Fast dedicated
Parallelism
• Heavy data flow hardware MAC
through CPU •Special Instruction
• Real time operations •On-chip memory and
cache
•Extended Parallelism-
SIMD, VLIW, Superscalar
 Desirable Features of DSP Processors
• DSP processors should have multiple registers so that data (i.e. arrays) exchange
from register to register is fast.
• DSP operations require multiple operands simultaneously. Hence DSP processor
should have multiple operand fetch capacity.
• DSP processors should have circular buffers to support circular shift operations.
• The DSP processor should be able to perform multiply and accumulate
operations very fast.
• DSP processors should have multiple pointers to support multiple operands,
jumps and shifts.
• Since DSP processors can be used with general processors, they should have
multi processing ability.
• To support DSP operations fast, the DSP processors should have on chip
memory.
• For real time applications interrupts and timers are required. Hence DSP
processors should have powerful interrupt structure and timers

The architectures of DSP processors are designed to have these features. The DSP
processors from Analog Devices, Texas Instruments, Motorola etc. are commonly used.
 Computer Architectures for Signal
Processing
• Although signal processing operations can be performed
on all the types of processors, they are not
computationally efficient.
• The specific operations in DSP, such as
multiply/accumulate, shifting, bit reversing, convolution
needs special provisions in architectures for efficient
computation.
• Different types of architectures are as follows :
1. Von-Neumann architecture.
2. Harvard architecture.
3. Modified Hardvard architecture
 Von-Neumann Architecture
• All the general purpose processors normally
have this type of architecture.
 Von-Neumann Architecture
• The architecture shares same memory for program and
data.
• The processors perform instruction fetch, decode and
execute operations sequentially. In such architecture, the
speed can be increased by pipelining.
• This type of architecture contains common internal
address and data bus, ALU, accumulator, I/O devices and
common memory for program and data.
• This type of architecture is not suitable for DSP processors.
 Harvard Architecture
• The Harvard architecture has separate
memories for program and data. There are
also separate, address and data buses for
program and data. Because of these separate
on chip memories and internal buses, the
speed of execution in Harvard
architecture is high
Harvard Architecture
 Harvard Architecture
• In this block diagram, separate Program Memory Address (PMA) bus and
Program Memory Data (PMD) bus for program memory.
• Similarly there is separate Data Memory Data (DMD) bus and Data Memory
Address (DMA) bus for data memory.
• This is all on chip.
• The digital signal processor includes various registers, address generators, ALUs
etc.
• The PMD bus is used to get instructions from the program memory and DMD
bus is used to exchange operands and results from data memory.
• The instruction code from program memory and operands from data memory
can be fetched simultaneously. This parallel operation increases the speed.
• It is possible to fetch next instruction when current instruction is executed.
That is, the fetch, decode and execute operations are done parallely.
Modified Harvard Architecture
 Modified Harvard Architecture
• Fig. shows the block diagram for modified Harvard
architecture.
• One set of bus is used to access program as well as data
memories.
• The DMD bus can be used to transfer the data from
program memory to data memory and vice-versa.
• Normally the program memory and data memory
addresses are generated by separate address generators.
• This modified Harvard architecture is used in several P-
DSPs such as DSP processors from Texas Instruments and
Analog Devices.
Hardware Multiplier-Accumulator (MAC) Unit
 Hardware Multiplier-Accumulator (MAC) Unit
• Most of the operations in DSP involve array multiplication. The
operations such as convolution, correlation require multiply and
accumulate operations.
• In real time applications, the array multiplication and accumulation
must be completed before next sample of input comes. This
requires very fast implementation of multiplication and
accumulation.
• The dedicated hardware unit called multiplier-accumulator (MAC).is
used. It is one of the computational unit in processor.
• The complete MAC operation is executed in one clock cycle.
In Texas Instruments DSP processor 320C5X, the output of
multiplier is stored into the product register. This product register
contents are added to accumulator register ACC in central ALU.
 Hardware Multiplier-Accumulator (MAC) Unit
• The MAC accepts two 16-bit 2's compliment fractional
numbers and computes 32-bit product in a single cycle only.
• The X-register and Y-register holds the inputs to be
multiplied. The DSP processors have a special instruction
called MACD. This means multiply accumulate with data
shift.
• The MACD instruction performs multiply, accumulate with
accesses are required :
i) Fetch MACD instruction from program memory
ii) Fetch one of the operands from program memory
iii) Fetch second operand from data memory
iv) Data memory write
 Pipelining
• Any instruction cycle can be split in following micro
instructions :
i) Fetch : In this phase, an instruction is fetched from the
memory.
ii) Decode : In this phase, an instruction is decoded.
iii) Read : An operand required for the instruction is fetched
from the data memory.
iv) Execute : The operation is executed and results are
stored at appropriate place.
Each of the above operations can be separately executed in
different functional units.
Fig. 5.2.6 shows how the instruction is executed without
pipeline.
 Pipelining

• In the above figure, observe that when instruction I1 is

in fetch phase, other units such as decode, read and
execute are idle. Similarly when I1 is in decode phase,
other three units are idle. This means each functional
unit is busy only for 25% of the total time.
 Pipelining

Fig. shows the instruction execution with pipeline. Here observe that when I1
is in decode phase, next instruction I 2 is fetched.
Similarly when I 2 goes to decode phase, next instruction I 3 is fetched. Thus
observe that all the functional units are executing four successive
instructions at any time.
On comparing Fig. 5.2.6 and Fig. 5.2.7 we observe that five instructions are
executed in the same time if pipelining is used.
 General purpose DSP architecture

DSP Processors

Fixed point processors • Floating point processors

• Represent each number with a minimum of • Represent each number with a minimum of 32 bits
16 bits • 232 = 4,294,967,296 possible bit patterns can represent
• 216 = 65536 possible bit patterns can a number
represent a number • ANSI/IEEE Std. 754-1985-- the largest and smallest
• Unsigned integer : 0 to 65,535 numbers are ±3.4×1038 and ± 1.2x10-38, respectively
• Signed integer : -32,768 to 32,767
Fixed point digital signal processors
First Generation Second Generation Third Generation Fourth Generation
• TMS320C54xx,D
• TMS320C1X by TI • TMS320C5X from SP563X and • TMS320C62XX
in 1982 TI, DSP5600X DSP16000 (VLIW Very Long
• Dedicated AU with from Motorola, • Aimed for instruction word )
multiplier and ADSP21XX from Digital • Included extensive
accumulator Analog Devices, communication parallelism while
• Harvard DSP16XX from • Special maintaining the
architecture with Lucent instructions for features of earlier
separate program Technologies Adaptive versions
and data memory • Enhanced filtering which • Wider
• On-chip memory features than first included echo instructions, wider
and special generation cancellations data paths more
instructions for • Larger on-chip and adaptive registers, larger
execution of basic memory and equalization instruction cache
DSP algorithms more special and Viterbi and multiple AU
instructions to decoding
execute DSP • Low power and
algorithms had power
• MAC with Repeat management
facility
Floating point DSP processors

First Generation Second Generation Third Generation

• TMS320C3X TI • TMS320C4X, • TMS320C67xx,

• Larger memory ADSP-2106x ADSP-TS001
and many on-chip SHARCH • VLIW
peripheral • Emphasis on
facilities multiprocessing
• Program cache and
and on-chip dual multiprocessor
access memories support
• Graphics and
Image processing
• Supported three
floating point
formats
Selecting Digital Signal Processor
• System engineers must select the device that provides the
most effective solution to meet the requirements of their
DSP application.
• Compare the raw processing power i.e. performance, of the
two processors.
• The mapping of DSP algorithms to DSP devices. This may
be complex, and requires an understanding of:
– I/O data paths,
– Memory management,
– Inter processor communication capability,
– Synchronization mechanisms
 Special purpose DSP Hardware
There are two types of special-purpose hardware,
1. Hardware designed for efficient execution of specific DSP
algorithms such as digital filters, Fast Fourier Transform.
This type of special- purpose hardware is sometimes called
an algorithm-specific digital signal processor 
2. Hardware designed for specific applications: for example
telecommunications, digital audio, or control applications.
This type of hardware is sometimes called an application-
specific digital signal processor.