Processor: Datapath and Control

Computer Organization & Design, Hennesy & Patterson Chapter 5 (3rd) or 4 (4th)

Augusto Salazar
Departamento de Ingeniería de Sistemas
Universidad del Norte
[email protected]

Originalmente por Profesor Miguel Jimeno

1
 MIPS´s High Level View
Including multiplexers and control lines

This is known as a Datapath for Single-Cycle, in which there is a ling cycle

for each instruction
2
 Storage Element: Idealized Memory

Write Enable Address

Memory (idealized) Data In DataOut

– One input bus: Data In 32 32
– One output bus: Data Out Clk
Memory word is selected by:
– Address selects the word to put on Data Out
– Write Enable = 1: address selects the memory
word to be written via the Data In bus
Clock input (CLK)
– The CLK input is a factor ONLY during write operation
– During read operation, behaves as a combinational logic
block:
• Address valid => Data Out valid after “access time.”

3
 Building a Datapath - Load
R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
31 26 21 16 11 0
op rs rt immediate
6 bits 5 bits 5 bits rd 16 bits
Rd Rt
RegDst Mux
Rs
RegWr 5 ALUct
5 5
r
busA W_Src
Rw Ra Rb
busW 32
32 32-bit

ALU
32 Registers 32
Clk busB MemWr

x
Mu
32
Mux

WrEn Adr
Extender

Data In 32
imm16 32 Data
16 32
Clk Memory
ALUSrc
4
ExtOp
 Building a Datapath - Store
Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16

31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits

Rd Rt ALUctr MemWr W_Src

RegDst
Mux
Rs Rt
RegWr 5 5 5
busA
Rw Ra Rb
busW 32
32 32-bit

ALU
32 Registers 32
Clk busB

Mux
Mux

32
WrEn Adr
Extender

Data In 32 32
imm16 Data
32
16 Memory
Clk

5 ExtOp ALUSrc
 Putting it All Together: A Single Cycle
Datapath
We have everything except control signals (underline)

Branch Instruction<31:0>
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Jump Fetch Unit
Rd Rt
RegDst Clk
1 Mux 0
Rs Rt Rt Rs Rd Imm16
RegWr 5 5 5 ALUctr
busA Zero MemWr MemtoReg
Rw Ra Rb
busW 32
32 32-bit

ALU
32 0
Registers busB 0 32
Clk

Mux
32
Mux

32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc

6
ExtOp
 Logisim implementation

This week we will add the data memory to the

project.

With this we should support load and store

instructions.