Inverter Design

Compiled By: Prof.R.K.Lamba

 MOS voltage levels
Case 1: NMOS discharges capacitor
• Initially: Vout = Vcc (capacitor fully charged)
• VGS of NMOS = Vcc
• What is final Vout?
Vout Vcc
G D
Vcc Cload
S Vout

time
• NMOS remains on since VGS > VT
• Final output voltage Vout = 0V
 MOS voltage levels
Case 2: NMOS charges capacitor
• Initially: Vout = 0
• Initial VGS of NMOS = Vcc
• What is final Vout?
Vcc
Vcc
G D
Vcc
S Vout
Vout Vcc-VT
Cload

time
• NMOS remains on until VGS = VT
• Final output voltage Vout = Vcc - VT
 MOS voltage levels
Repeat for PMOS:
• Case 1: PMOS discharging capacitor

G S
Vout
Gnd Cload • PMOS on until VGS = VT
D
• Vout = |VT|

• Case 2: PMOS charging capacitor

Vcc
G S
Gnd • PMOS always on (VGS = -VCC)
D
Vout • Vout = VCC
Cload
 MOS voltage levels
• NMOS summary
– Transfers logic ‘0’ completely (good for discharging
a node)
– Does not transfer logic ‘1’ completely (bad for
charging a node)
• PMOS summary
– Transfers logic ‘1’ completely
– Does not transfer logic ‘0’ completely
• Result:
– NMOS used for pulldown, PMOS for pullup
 Inverter Operation
• Inverter is simplest digital logic gate
In Out
‘0’ ‘1’
0 1
‘1’ ‘0’
1 0
• Many different circuit styles possible
– Resistive-load
– Pseudo-NMOS
– CMOS
• Important characteristics
– Speed (delay through the gate)
– Power consumption
– Robustness (tolerance to noise)
– Area and process cost
 Inverter model: VTC
Voltage transfer curve (VTC): plot of output voltage Vout
vs. input voltage Vin

Vin Inverter Vout

Ideal digital inverter:

Vcc ideal – When Vin=0,
Vout=Vcc
Vout – When Vin=Vcc,
actual
Vout=0
– Sharp transition
Vcc region
Vin
 Actual inverter: VOH and VOL
• VOH and VOL represent
the “high” and “low”
output voltages of the
VOH
inverter
• VOH = output voltage
Vout when Vin = ‘0’
• VOL = output voltage
VOL
Vcc when Vin = ‘1’
Vin
• Ideally,
– VOH = Vcc
– VOL = 0
 VOL and VOH
• In transfer function
terms:
– VOL = f(VOH)
VOH
– VOH = f(VOL)
– f = inverter transfer
Vout function
• Difference (VOH-VOL) is
VOL
VOL VOH Vcc
the voltage swing of the
Vin gate
– Full-swing logic swings
from ground to Vcc
 Inverter threshold

Inverter switching threshold:

– Point where voltage
transfer curve intersects
VOH Vout=Vin line Vout=Vin
– Represents the point at
Vout VTH which the inverter switches
state
VOL – Normally, VTH  Vcc/2
Vcc
Vin
 Noise Margins
• VIL and VIH measure effect
of input voltage on
inverter output
VOH • VIL = largest input voltage
Slope = -1
recognized as logic ‘0’
Vout • VIH = smallest input
voltage recognized as
VOL
VIL VIH Vcc
logic ‘1’
Vin • Defined as point on VTC
where slope = -1
 Noise margin (cont)
• Noise margin is a measure of the
robustness of an inverter
interconnect
– NML = VIL - VOL
– NMH = VOH - VIH
“1” • Models a chain of inverters.
VOH
NMH Example:
VIH
– First inverter output is VOH
VIL – Second inverter recognizes input >
NML
VOL VIH as logic ‘1’
“0”
– Difference VOH-VIH is “safety
zone” for noise
Ideally, noise margin should be
as large as possible
 Noise margin (cont)
• Why are VIL, VIH defined as unity-gain point
on VTC curve?
– Assume there is noise on input voltage Vin
Vout  f Vin  Vnoise 
– First-order approximation:
dVout
Vout  f Vin   Vnoise
dVin
– If gain (dVout/dVin) > 1, noise will be amplified.
– If gain < 1, noise is filtered. Therefore VIL, VIH
ensure that gain < 1
 Inverter time response
Vcc

Vcc/2 Vin
Vss
Vcc

Vcc/2 Vout

Vss
t 0 t1 t2 t 3
• Progagation delay measured from 50% point of
Vin to 50% point of Vout
• tphl = t1 - t0, tplh = t3 - t2, tp = ½(tphl+tplh)
 Rise and fall time
tF tR

V90%

V10%

t0 t 1 t2 t3
• Fall time: measured from 90% point to 10% point
– tF = t1 - t0
• Rise time: measured from 10% point to 90% point
– tR = t3 - t2
• Alternately, can define 20%-80% rise/fall time
 Ring oscillator
• Ring oscillator circuit: standard method of
comparing delay from one process to another
• Odd-number n of inverters connected in chain:
oscillates with period T (usually n >> 5)
V1 V3 V2
VOH
V1 V2 V3
V50%
Cload Cload

tPHL2 tPLH3 tPHL1 tPLH2 tPHL3 tPLH1

T  t plh1  t phl1  t plh 2  t phl 2  t plh 3  t phl 3  
T
1 1 1
T  2nt p , f   , tp 
T 2nt p 2nf
 Resistive-load inverter
• Requires only NMOS transistor
and resistor Vcc

• When Vin = 0:
R
– NMOS is OFF (VGS = 0)
– No current through NMOS or D Vout
G
resistor Vin
S
– Vout  Vcc
• When Vin = Vcc:
– NMOS is ON (VGS = Vcc) Gnd

– NMOS on resistance << R Remember: if body terminal

not shown, it is connected to
– Vout  0
gnd for NMOS, vcc for
PMOS
 Resistive-load inverter: VOH

Vcc

• Vin = 0: NMOS transistor R

off, no current flows in Vout
circuit Vin=0
• No voltage drop across R
• VOH = Vcc
Gnd
 Resistive-load inverter: VOL
• Vin = Vcc: NMOS transistor
Vcc
on (linear mode)
ID  k ' W
L
(V
GS  VT )VDS  VDS
1
2
2
 R
Iload
VGS  VIN  VCC
Vout
VDS  VOL Vin=Vcc
ID
(VCC  VOL )
ID  (because ID = Iload)
R
(VCC  VOL ) 2 Gnd
 k ' WL [(VCC  VT )VOL  12 VOL ]
R
• Solve quadratic equation for VOL
 Resistive-load inverter: VOL cont

• Note that the value of VOL depends on the

size of the NMOS device and on R
– Increase W to reduce VOL
– Increase R to reduce VOL
• Logic with this property is called “ratioed
logic”
– Requires careful sizing for correct logic levels
• Ratioless logic: output levels do not depend
on transistor sizes
 Resistive-load inverter: VIL
• VIL = low unity gain point of VTC
– When Vin = VIL, NMOS in saturation:
VCC  Vout 1

 2 k n Vin  VT  2

R
Vout  VCC  12 Rk n Vin  VT 
2

– Take derivative of Vout with respect to Vin, set to -1

dVout
  Rk n Vin  VT   1
dVin
increase VIL (and
1
Vin  VIL   VT NML) by reducing kn
Rk n
 Resistive-load inverter: VIH
• VIH = high unity gain point of VTC
– When Vin = VIH, NMOS in linear region:
VCC  Vout
R

 k n Vin  VT Vout  12 Vout
2

VCC  Vout  k n RVin  VT Vout  12 k n RVout
2
(1)
– Take derivative of Vout with respect to Vin, set to -1
dVout dVout dVout
  k n RVin  VT   k n RVout  k n RVout
dVin dVin dVin
1  k n RVin  VT   k n RVout  k n RVout
– Solve this equation simultaneously with (1) to get:
8VCC 1
VIH  VT  
3k n R k n R
 Resistive-load inverter: VTH
• Threshold of resistive-load inverter: V TH:
– Point on VTC where Vin = Vout:
– NMOS in saturation (ignoring ):
I D  12 k ' WL Vin  VT 
2

Vin  Vout  VTH

(VCC  VTH ) 1 ' W
 2 k L VTH  VT 
2

R
– Solve this quadratic for VTH
 Resistive-load inverter: VTC
VCC Resistor load line Vin=4V
R (slope = 1/R)
Drain current IDS

Vin=3V VCC

Vout
Vin=2V

Vin=1V
VOL
Vout = VDS VCC 0 1 2 Vin 3 4
• Plot IDS of transistor and Iload of resistor vs. Vout
• Since currents must be equal, intersection points
define VTC
 Resistive-load inverter: VTC
VCC
small R Vin=4V
R R
Drain current IDS

Vin=3V VCC
small R
large
R

Vout
Vin=2V R

Vin=1V large
R

Vout = VDS VCC 0 1 2 Vin 3 4

• Changing value of R affects VTC curve

• larger R → reduces VOL and improves NML but degrades NMH
 Resistive-load inverter: power
• Static power consumption: depends on
input voltage Vin
– P0 = power when Vin = ‘0’
– P1 = power when Vin = ‘1’
• Average power depends on input
probability
–  = probability that Vin = ‘1’
– (1-) = probability that Vin = ‘0’
– Pavg = P1 + (1-)P0
 Resistive-load inverter: power
• Find P0 and P1:
– Vin = 0: NMOS transistor off. No current flows
from Vcc to Gnd (except leakage). P0 = 0
– Vin = Vcc: NMOS transistor on. Output voltage
Vout = VOL.
I 
 VCC  VOL 
, P  IV
load
R
V  VOL VCC
P1  CC
Static power consumed
R when Vin = VCC
V  VOL VCC
Pavg   CC
R
 Resistive-load inverter: delay
R IR R IR

Cload Cload
‘1’ ID ‘0’

Output falling (Vin = 1): Output rising (Vin = 0):

• Discharge Cload • Charge Cload through
through NMOS resistor
• Need large ID, small IR • Need large IR
 Resistive-load inverter: delay
• Delay computation: exact method
– Integrate capacitor charging current
dV C
I C (t )  C , dt  dV
dt I C (t )
td V1
C
0 dt  V I C (t ) dV
0

– Problem: charging current IC is a function of t

– Integral can be difficult to compute
 Resistive-load inverter: delay
• Delay calculation: approximate method
– Use an average value of capacitor current IC
– Find current at start of transition, and current at
end of transition, and use the average
dV C
I avg C , dt  dV
dt I avg
td V1
C
0 dt  V I avg dV For rise delay:
0 V0 = 0, V1 = Vcc/2
C
td  V1  V0  For fall delay:
I avg V0 = Vcc, V1 = Vcc/2
 Resistive-load inverter: delay
• Inverter rise delay tplh: Vin Vout

– Beginning of transition:
VCC  VOL
Vout  VOL , IC 
R
– End of transition:
VCC
Vout  2 VCC ,
1
IC 
2R
– Average current:
3VCC  2VOL
I avg 
4R
– Delay:
Cload 4 RCload
td  V1  V0  , t plh    12 VCC  VOL 
I avg 3VCC  2VOL
 Resistive-load inverter: delay
• Inverter fall delay tphl:
– Beginning of transition: Vout=VCC (NMOS in saturation)
I C 0  k n VCC  VT 
1 2
2

– End of transition: Vout=½VCC (NMOS in linear)

  
I C1  k n VCC  VT  12 Vcc  14 Vcc2  k n 14 Vcc2  12 VTVCC 
– Average current:
I avg  1
2
 I C 0  I C1 
– Delay:
Cload Cload
td  V1  V0  , t phl   12 VCC 
I avg I avg
 Resistive-load inverter: layout
• Resistors in CMOS process
– Need large resistance in small area
L L
R 
A tW
  = resistivity in Ohms/square
• How to make resistor in CMOS process?
– Diffusion resistor:  = 10 – 100 square
(Need very large lengths)
– Polysilicon resistor:  = ~10 square
(Again, need very large lengths)
– Undoped poly (if available):  = 100 Msquare
 Resistive-load inverter: problems
• Static power consumption
• Tradeoff between delay and power:
– For fast operation, need small resistor
– For low power, need large resistor
• VOL is larger than 0V
– Reduced noise margin
• Large area
– Hard to make large resistance values on chip
 Pseudo-NMOS inverter
• Replace resistor with “always-on”
PMOS transistor
Vcc VGS,P = -VCC
• Easier to implement in standard
S
process than large resistance G
value D
Vout
• PMOS load transistor:
Vin
– On when VGS < VT →
VGS = -VCC: transistor always on
– Linear when VDS > VGS-VT →
Vout-Vcc > -Vcc-VT → Vout > -VT Gnd

– Saturated when VDS < VGS-VT → Remember:

Vout-Vcc < -Vcc-VT → Vout < -VT VT(PMOS) < 0
 Pseudo-NMOS inverter: VOH

• VOH for pseudo-NMOS

Vcc
inverter:
– Vin = 0
– NMOS in cutoff: no drain Vout
current
• Result: VOH is VCC (as in
resistive-load inverter case)
Gnd
 Pseudo-NMOS inverter: VOL
• Find VOL of pseudo-NMOS inverter:
– Vin = Vcc: NMOS on in linear mode

I Dn  k n Vcc  VTn VOL  12 VOL2 
– PMOS on in saturation mode (assume)
I Dp  k p   VCC  VTp 
1 2
2 (neglecting )
– Setting Idn = Idp:
k V  k n VCC  VTn VOL  k p   VCC  VTp   0
1 2 1 2
2 n OL 2

• Key point: VOL is not zero

– Depends on thresholds, sizes of N and P
transistors
 Pseudo NMOS inverter: VTC
I/V curve for NMOS: I/V curve for PMOS:
Vin=4V

-Drain current -IDS

Drain current IDS

Vin=3V
VGS=-Vcc

Vin=2V

Vin=1V

VDS = Vout VCC -VDS = -(Vout - VCC)

• Plot of -IDS vs -VDS since
current is from source to drain
• Only one curve since VGS fixed
 Pseudo NMOS inverter: VTC
Vin=4V
Drain current IDS

Vin=3V VCC

Vout
Vin=2V

Vin=1V

Vout = VDS VCC 0 1 2 Vin 3 4

• Similar VTC to resistive-load inverter

• Sharper transition region, smaller area
 Depletion-load inverter
• Depletion-load inverter: uses
depletion NMOS transistor as Vcc VGS = 0
load D
G
– Depletion transistor has VT < 0
S
Vout
• Load is always on:
Vin
– VGS = 0 > VT
• Body effect of depletion
transistor is significant (when Gnd
Vout = VOH)
 Depletion-load inverter
• Static characteristics: VOH and VOL
– VOH: NMOS driver is off. As long as body
effect does not cause VT(load) > 0, VOH = Vcc

– VOL: driver in linear mode, depletion load in

saturation
1
2
2

k nl   VTl   k nd VCC  VTd VOL  12 VOL
2

Need to calculate using body-effect coefficient
(solve for VOL) → VOL is non-zero
 Summary - Definitions

• VOH is the output high level of an inverter

VOH = VTC(VOL)
• VOL is the output low level of an inverter
VOL = VTC(VOH)
• VTH is the switching threshold
VTH = VIN = VOUT
• VIH is the lowest input voltage for which the output will be
≥ the input (worst case ‘1’)
dVTC(VIH)/dVIH = -1
• VIL is the highest input voltage for which the output will be
≤ the input (worst case ‘0’)
dVTC(VIL)/dVIL = -1
 Summary – Definitions

• NML is the difference between the highest acceptable ‘0’ and

the lowest possible ‘0’
NML = VIL – VOL
• NMH is the difference between the lowest acceptable ‘1’ and
the highest possible ‘1’
NMH = VOH – VIH
• tPHL is the propagation delay from the 50% point of the input to
the output when the output goes from high to low
• tPLH is the propagation delay from the 50% point of the input to
the output when the output goes from low to high
• tP is the average propagation delay
• tR is the rise time (usually 10% to 90%)
• tF is the fall time (usually 90% to 10%)
 Summary – Resistive-load inverter
2
1  1  2VCC Vcc
VOL  VCC  VT 0   VCC  VT 0   
kn R  kn R  kn R
VOH  VCC Iload
R
Vout
Vin
1 ID
VIL  VT 0 
kn R
8 VCC 1
VIH  VT 0   Gnd
3 kn R kn R

1 1 4 RCload
VTH  VT 0   2VCC  2VT 0  t plh   12 VCC  VOL 
kn R kn R 3VCC  2VOL

VCC  VCC  VOL 

8 CloadVCC
PDC ,avg  t phl 
R
2
kn 7VCC  12VCCVT 0  4VT20  4VCC / kn R
 Summary – Depletion-load inverter
Vcc
kload
VOL  VOH  VT 0   VOH  VT 0   VT ,load  VOL 
2

k driver
VOH  VCC
Vout
Vin
VIL  VT 0 
kload
Vout  VCC  VT ,load Vout  
k driver
 kload  dVT ,load
VIH  VT 0  2Vout   
k   VT ,load  Vout   dV

Gnd
 driver  out

• Solve with KCL (VT,load varies with Vout)

VCC kload
PDC ,avg     VT ,load VOL  
2 2
 CMOS Inverter
• Complementary NMOS and
PMOS devices
Vcc
• In steady-state, only one device
is on (no static power
consumption) Vin Vout
• Vin=1: NMOS on, PMOS off
– Vout = VOL = 0
• Vin=0: PMOS on, NMOS off
– Vout = VOH = Vcc Gnd

• Ideal VOL and VOH!

• Ratioless logic
 CMOS Inverter: VTC
PMOS NMOS
Vin=4V
Drain current IDS

VCC
Vin=3V

Vout
Vin=2V

Vin=1V

Vout = VDS VCC 0 1 2 Vin 3 4

• Output goes completely to Vcc and Gnd

• Sharp transition region
 CMOS inverter operation
Vcc

• NMOS transistor:
– Cutoff if Vin < VTN Vin Vout
– Linear if Vout < Vin – VTN
– Saturated if Vout > Vin – VTN
• PMOS transistor
– Cutoff if (Vin-VCC) < VTP → Vin < Vcc+VTP
– Linear if (Vout-VCC)>Vin-Vcc-VTP → Vout>Vin - VTP
– Sat. if (Vout-VCC)<Vin-Vcc-VTP → Vout < Vin-VTP
CMOS inverter VTC
P linear
P cutoff
N cutoff
N linear

P linear
N sat P sat
N sat

P sat
N linear
 CMOS inverter VTC

• Increase W of PMOS
VCC kp=kn kp increases
VTC moves to right
• Increase W of NMOS
Vout kp=5kn
kn increases
kp=0.2kn VTC moves to left
• For VTH = Vcc/2
kn = kp
VCC Wn  2Wp
Vin
 Effects of Vth adjustment

• Result from changing kp/kn ratio:

– Inverter threshold VTH  Vcc/2
– Rise and fall delays unequal
– Noise margins not equal
• Reasons for changing inverter threshold
– Want a faster delay for one type of transition
(rise/fall)
– Remove noise from input signal: increase one
noise margin at expense of the other
 CMOS inverter: VIL

• KCL: kn
2
2 kp
2

VGS ,n  VT 0,n   2VGS , p  VT 0, p VDS , p  VDS , p 2 
kn
2
k

Vin  VT 0,n  2  p 2Vin  VCC  VT 0, p Vout  VCC    Vout  VCC  2
2

• Differentiate and set dVout/dVin to –1
 dV 
k n Vin  VT 0,n   k p Vin  VCC  VT 0, p  out   Vout  VCC    Vout  VCC  out 
dV
 dVin dVin 
k n VIL  VT 0,n   k p  2Vout  VIL  VT 0, p  VCC 

2Vout  VT 0, p  VCC  k RVT 0,n kn

VIL  kR 
1  kR kp
• Solve simultaneously with KCL to find VIL
 CMOS inverter: VIH

• KCL: kn
2
 2 kp
2

2VGS ,n  VT 0,n VDS ,n  VDS ,n  VGS , p  VT 0, p 
2

kn
2
 kp

2Vin  VT 0,n Vout  Vout  Vin  VCC  VT 0, p 
2

2
2

• Differentiate and set dVout/dVin to –1

 dV 
k n Vin  VT 0,n  out  Vout  Vout out   k p Vin  VCC  VT 0, p 
dV
 dVin dVin 
k n  2Vout  VIH  VT 0, p   k p VIH  VCC  VT 0, p 

VCC  VT 0, p  k R  2Vout  VT 0,n  kn

VIH  kR 
1  kR kp
• Solve simultaneously with KCL to find VIH
 CMOS inverter: VTH
kp
• KCL:
kn
VGS ,n  VT 0,n   VGS , p  VT 0, p  2
2

2 2

kn kp
Vin  VT 0,n   Vin  VCC  VT 0, p  2
2

2 2

• Solve for VTH = Vin = Vout

VT 0,n 
1
VCC  VT 0, p  kn
kR
VTH  kR 
1 kp
1
kR
 CMOS inverter: Ideal VTH
VT 0,n 
1
VCC  VT 0, p 
kR kn
VTH  kR 
1 kp
1
kR

2
 VCC 2  VT 0, p 
• Ideally, VTH = VCC/2 k R ,ideal   

 VCC 2  VT 0,n 

• Assuming VT0,n = VT0,p, k R ,ideal  1

W 
 
 L  p n
  2.5
 
W p
 
 L n
CMOS inverter: VIL and VIH for Ideal VTH

• Assuming VT0,n=-VT0,p, and kR = 1,

1
VIL   3VCC  2VT 0 
8
1
VIL   5VCC  2VT 0 
8
VIL  VIH  VCC

NM L  VIL  VOL  VIL

NM H  VOH  VIH  VCC  VIH  VIL
CMOS inverter capacitances
Vcc
Cgs,p Csb,p

Cgd,p Cdb,p
Vin
Cgd,n Cdb,n Cint Cg

Cgs,n Csb,n
Gnd
 CMOS inverter capacitances
Vcc
Cgs,p Csb,p

Cap on node f:

• Junction cap
Cdb,p and Cdb,n
Cgd,p Cdb,p • Gate capacitance
Vin f
Cgd,n Cdb,n
Cgd,p and Cgd,n
Cint Cg
• Interconnect cap
• Receiver gate cap

Cgs,n Csb,n
Gnd
 CMOS inverter capacitances
• Junction capacitances Cdb,p and Cdb,n:
– Equation for junction cap
m
AC j 0  q N a N d 1 
C j V   , C j0   
 2 N a  N d 0 
m
 V
 1  
 0 
– Non-linear, depends on voltage across junction
– Use Keq factor to get equivalent capacitance for
a voltage transition
Cdb  AK eq C j  PK eqswC jsw
 CMOS inverter capacitances
• Gate capacitances CGD,p and CGD,n:
– In steady state, what regions are transistors in?
– One is in cutoff: CGD = CGS = 0
– One is in saturation: CGD = 0
– Therefore, gate-to-drain capacitance is only due
to overlap capacitance:
C gd , p  C gd ,n  CoxWLD

However, also need to consider Miller effect ...

 CMOS inverter capacitances
Cgd1
Vout Vout

Vin Vin 2Cgd1

• When input rises by V, output falls by V

– Effective voltage change across Cgd1 is 2V
– Effective capacitance to ground is twice Cgd1
• Including Miller effect:
C gd , p  C gd ,n  2CoxWLD
 CMOS inverter capacitance
• Interconnect capacitance
– Due to capacitance of metal and poly lines used
to connect transistors
– Complex; includes parallel-plate and fringing-
field components
– For wide wires:
 ox
Cint  WL tox = thickness of field oxide
tox

Sample capacitances for 1m process:

poly: 0.058 fF/m2 M1: 0.031 fF/m2
M2: 0.015 fF/m2 M3: 0.010 fF/m2
 CMOS inverter capacitance

• Receiver gate capacitance

– Includes all capacitances of gate(s) connected
to output node
– Unknown region of operation for receiver
transistor: total gate cap varies from
(2/3)WLCox to WLCox
– Ignore Miller effect since operation unknown
– Assume worst-case value, include overlap
C g  WLeff Cox  2WLD Cox
 Inverter capacitances, cont.

• Simplify the circuit: combine all capacitances at

output into one lumped linear capacitance:

Cload = Cgd,n + Cgd,p + Cdb,n + Cdb,p + Cint + Cg

• Csb,n = Csb,p = 0

• Cgs,n and Cgs,p are not connected to the load. These are
part of the gate capacitance Cg
 First-order inverter delay

• Assume: Current charging or

discharging capacitance Cload is
nearly constant Iavg Vin Vout
Cload

• tPHL = Cload (Vcc - Vcc/2) / Iavg

• tPLH = Cload (Vcc/2 - Vss) / Iavg

 Inverter delay, falling

ID.n Cload
Vin

• Assume PMOS fully off (ID,p = 0)

dV
I C
dt
dVout
I D ,n  Cload Need to determine ID,n
dt
 Inverter delay, falling
NMOS in saturation
Vcc
Vcc - Vtn NMOS in linear region

Vcc/2

t0 t1 t2

• From t0 to t1: NMOS in saturation

• From t1 to t2: NMOS in linear region
• Find ID in each region
 Inverter delay, falling t1-t0
• Assumption: Input fast enough to go through transition
before output voltage changes
• Vout drops from VOH to VCC-VTN (NMOS saturated)

I DS  kn (Vin  VT 0,n ) 2 / 2  kn (VOH  VT 0,n ) 2 / 2

t1 VOH VT 0 , n
 2CL
t dt  kn (VOH  VT 0,n )2  dV
VOH
out
0

2CLVT 0,n
t1  t0 
kn (VOH  VT 0,n ) 2
 Inverter delay, falling t2-t1
• Vout drops from (VOH-VT0,n) to VCC/2
• NMOS in linear region


I DS  kn (VOH  VT 0,n )Vout  12 Vout2 
(VOH VOL ) / 2
dVout
t2  t1  CL 
VOH VT 0 , n

kn (VOH  VT 0,n )Vout  12 Vout2 
CL  2(VOH  VT 0,n )  (VOH  VOL ) / 2 
t2  t1  ln  
kn (VOH  VT 0,n )  (VOH  VOL ) / 2 
 Inverter delay, falling

• Total fall delay =

(t1-t0) + (t2-t1)
CL  2VT 0,n  4(VOH  VT 0,n ) 
t PHL    ln  1
k n (VOH  VT 0,n ) VOH  VT 0,n  VOH  VOL 
 Inverter delay, rising

• Similar calculation as for falling delay

• Separate into regions where PMOS is in
linear, saturation

CL  2 VT 0, p  4(VOH  VOL  VT 0, p ) 
t PLH    ln  1
k p (VOH  VOL  VT 0, p ) VOH  VOL  VT 0, p  VOH  VOL 
 
 CMOS inverter delay
• First approximate method
– Assume a constant average
current for the transition
I1
– Iavg = average of drain current at V1=Vcc
beginning and end of transition
V2=½Vcc I2

Cload
t PHL  VCC  12 VCC  t1 t2
I avg
Iavg = ½(I1+I2)
Cload
t PLH   12 VCC  VSS 
I avg
 CMOS inverter delay
• Another approximate method:
– Again assume constant Iavg
– Iavg = current I1 at start of I1
transition V1=Vcc
– Why is this a good
approximation (esp. for deep V2=½Vcc
submicron)?

CloadVCC
t PHL  t1 t2
k n VCC  VTn 
2

Iavg = I1
CloadVCC
t PLH 
k p VCC  VTP  2
 Inverter rise, fall time
• Exact method: separate into regions
– t1
• Vout drops from 0.9VCC to VCC-VT (NMOS in saturation)
• Vout rises from 0.1VCC to VT (PMOS in saturation)
– t2
• Vout drops from VCC-VT to 0.1VCC (NMOS in linear region)
• Vout rises from VT to 0.9 VCC (PMOS in linear region)
– tf,r = t1 + t2

• Average current method:

– Find current at start and end of transition
– Find average and use

CV
 fall ,rise 
I avg
 CMOS inverter delay
• What if input has finite rise/fall time?
– Both transistors are on for some amount of time
– Capacitor charge/discharge current is reduced

Empirical equations:
2
 tr 
tpHL(ns)

t phl (actual )  t phl ( step )   

2

2
2
tf 
t plh (actual )  t ( step )   
2
plh
2
trise(ns)
 How to improve delay?

• Minimize load capacitances

– Small interconnect capacitance
– Small Cg of next stage
• Raise supply voltage
• Increase transistor gain factor
– increase transistor drive current for
charging/discharging output capacitance
Inverter Sizing
 Inverter Chain

In Out

CL

If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?

May need some additional constraints.

 Inverter Delay

• Minimum length devices, L=0.25m

• Assume that for WP = 2WN =2W 2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays W
• Analyze as an RC network
1 1
 WP   WN 
RP  Runit    Runit    RN  RW
 Wunit   Wunit 

Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL

W
Load for the next stage: C gin 3 Cunit
Wunit
 Inverter with Load

Delay

RW

CL
RW Load (CL)
tp = k RWCL

k is a constant, equal to 0.69

Assumptions: no load -> zero delay
Wunit = 1
 Inverter with Load

CP = 2Cunit Delay

2W

W
Cint CL

Load
CN = Cunit

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)
 Delay Formula

Delay ~ RW  Cint  C L 

t p  kRW Cint 1  C L / Cint   t p 0 1  f /  

Cint = Cgin with   1

f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
 Apply to Inverter Chain

In Out

1 2 N CL

tp = tp1 + tp2 + …+ tpN

 C gin, j 1 
t pj ~ Runit Cunit 1  
 C 
 gin , j 
N N  C gin, j 1 
t p   t p , j  t p 0  1  , C gin, N 1  C L
 C
i 1 

j 1 gin , j 
 Optimal Tapering for Given N

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

C gin , j  C gin , j 1C gin , j 1

- each stage has the same effective fanout (Cout/Cin)

- each stage has the same delay
 Optimum Delay and Number of
Stages
When each stage is sized by f and has same eff. fanout f:
f N
 F  C L / C gin,1

Effective fanout of each stage:

f NF
Minimum path delay


t p  Nt p 0 1  N F /  
 Example

In Out

1 f f2 CL= 8 C1
C1

CL/C1 has to be evenly distributed across N = 3 stages:

f 38 2
 Optimum Number of Stages

For a given load, CL and given input capacitance Cin

Find optimal sizing f
ln F
C L  F  Cin  f Cin with N 
N

ln f
t p 0 ln F  f  
 1/ N

t p  Nt p 0 F /   1   
  ln f ln f


t p t p 0 ln F ln f  1   f
  0
f  ln f 2

For  = 0, f = e, N = lnF f  exp1   f 

Optimum Effective Fanout f
Optimum f for given process defined by 
f  exp1   f 
fopt = 3.6
for =1
 Impact of Self-Loading on tp

No Self-Loading, =0 With Self-Loading =1

60.0

40.0
u/ln(u)

x=10,000

x=1000

20.0 x=100

x=10

0.0
1.0 3.0 5.0 7.0
u
Normalized delay function of F


t p  Nt p 0 1  N F /  
 Buffer Design

N f tp
1 64 1 64 65

1 8 64 2 8 18

1 4 16 64 3 4 15

1 64 4 2.8 15.3
2.8 8 22.6
 CMOS inverter power
• Power has three components
– Static power: when input isn’t switching
– Dynamic capacitive power: due to charging and
discharging of load capacitance
– Dynamic short-circuit power: direct current
from Vcc to Gnd when both transistors are on
 CMOS inverter static power
• Static power consumption:
– Static current: in CMOS there is no static current as
long as Vin < VTN or Vin > VCC+VTP
– Leakage current: determined by “off” transistor
– Influenced by transistor width, supply voltage,
transistor threshold voltages
Vcc Vcc

Ileak,p
Vss Vcc Vcc Vss
Ileak,n
Dynamic capacitive power

Evcc   ivcc (t )VCC dt
0

dVout
 VCC  C L dt
0
dt
VCC

 C LVCC  dV
0
out

Energy for one

Evcc  C V 2
L CC complete cycle
(charge and
Pdyn  C LVCC
2
f discharge)
 Dynamic capacitive power
• Formula for dynamic power:
Pdyn  C V 2
L CC f
• Observations
– Does not (directly) depend on device sizes
– Does not depend on switching delay
– Applies to general CMOS gate in which:
• Switched capacitances are lumped into CL
• Output swings from Gnd to Vcc
• Input signal approximated as step function
• Gate switches with frequency f
 Dynamic short-circuit power
• Short-circuit current flows from Vcc to Gnd when both transistors are on
• Plot on VTC curve:

VCC Imax: depends on

saturation current
Imax of devices
Vout ID

Vin VCC
 Dynamic short-circuit power

Imax

• Approximate short-circuit current as a

triangular wave
• Energy per cycle:
I max t r I max t f t r  t f
Esc  VCC  VCC  VCC I max
2 2 2
tr  t f
Psc  VCC I max f
2
 Inverter power consumption
• Total power consumption
Ptot  Pdyn  Psc  Pstat
 tr  t f 
Ptot  C V 2
L CC f  VCC I max   f  VCC I leak
 2 

• Energy-delay product:
– Multiply energy x delay: EDP = E*D
– Often the goal of a design is to minimize EDP
 Power reduction
• Reducing dynamic capacitive power:
– Lower the voltage!
• Quadratic effect on dynamic power
– Reduce capacitance
• Short interconnect lengths
• Drive small gate load (small gates, small fan-out)
– Reduce frequency
• Lower clock frequency -> use more parallelism
• Lower signal activity
 Power reduction
• Reducing short-circuit current:
– Fast rise/fall times on input signal
– Reduce input capacitance
– Insert small buffers to “clean up” slow input
signals before sending to large gate
• Reducing leakage current:
– Small transistors (leakage proportional to
width)
– Lower voltage
Power Dissipation
 Where Does Power Go in CMOS?

• Dynamic Power Consumption

Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors
Dynamic Power Dissipation
Vdd

Vin Vout

CL

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Not a function of transistor sizes!

Need to reduce CL, Vdd, and f to reduce power.
Modification for Circuits with Reduced Swing
Vdd
Vdd

Vdd -Vt

CL

E0 = CL  Vdd   V dd – Vt 
1

Can exploit reduced swing to lower power

(e.g., reduced bit-line swing in memory)
Adiabatic Charging

2 2
Adiabatic Charging
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles

E = C  V 2  n N 
N L dd
EN : the energy consumed for N clock cycles
n(N): the number of 0->1 transition in N clock cycles

EN 2
n N 
P avg = lim --------  fclk =  lim ------------  C  Vdd  f clk
N N N   N  L

n N 
0 = lim ------------
1 N N

P av g = 0 1  C  Vdd 2  f clk
 L
 Transistor Sizing for Minimum
In
Energy Out

Cext
Cg1 1 f

• Goal: Minimize Energy of whole circuit

– Design parameters: f and VDD
– tp  tpref of circuit with f=1 and VDD =Vref
 f  F 

t p  t p 0  1    1   
    f  
VDD
t p0 
VDD  VTE
 Transistor Sizing (2)

• Performance Constraint (=1)

 F  F
 2  f    2  f  
tp t p0  f  VDD Vref  VTE  f 
  1
t pref t p 0 ref 3  F  Vref VDD  VTE 3  F 
• Energy for single Transition

E  VDD
2
C g1  1   1  f   F 
2
E  VDD   2  2 f  F 
   
 
Eref  Vref   4  F 
 Transistor Sizing (3)

VDD=f(f) E/Eref=f(f)

4 1.5

3.5
F=1
3
2

normalized energy
1
2.5
vdd (V)

2 5
1.5
0.5

1 10

0.5 20

0 0
1 2 3 4 5 6 7 1 2 3 4 5 6 7
f f
Short Circuit Currents
Vdd

Vin Vout

CL

0.15

0.10
IVDD (mA)

0.05

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)
How to keep Short-Circuit Currents Low?

Short circuit current goes to zero if tfall >> trise,

but can’t do this for cascade logic, so ...
Minimizing Short-Circuit Power
8

Pnorm
5
Vdd =3.3

4
Vdd =2.5
3

1
Vdd =1.5
0
0 1 2 3 4 5
tsin/tsout
Leakage
Vdd

Vout

Drain Junction
Leakage

Sub-Threshold
Current

Sub-threshold current one of most compelling issues

Sub-Threshold Current Dominant Factor
in low-energy circuit design!
Reverse-Biased Diode Leakage
GATE

p+ p+
N

Reverse Leakage Current

+
V
- dd

IDL = JS  A

2
JS = JS
1-5pA/ mpA/m2
= 10-100 for a 1.2 m
at 25 degCMOS technology
C for 0.25m CMOS
JS doubles for every 9 deg C!
Js double with every 9oC increase in temperature
Subthreshold Leakage Component
Static Power Consumption
Vdd

Istat
Vout

CL
Vin = 5V

Pstat = P(In=1).Vdd . Istat

Wasted•energy … over dynamic consumption

Dominates
Should be avoided in almost all cases,
• Not a function of switching frequency
but could help reducing energy in others (e.g. sense amps)
 Principles for Power Reduction
• Prime choice: Reduce voltage!
– Recent years have seen an acceleration in supply
voltage reduction
– Design at very low voltages still open question (0.6 …
0.9 V by 2010!)
• Reduce switching activity
• Reduce physical capacitance
– Device Sizing: for F=20
• fopt(energy)=3.53, fopt(performance)=4.47