8086 and Memory Interfacing
Memory organization
In the design of all computers, semiconductor memories are used as
primary storage for data and code
Among the most widely used are RAM and ROM
The physical address space, or memory map, of a microprocessor
refers to the range of addresses of memory location that can
accessed by the microprocessor. The size of the address space
depends on the number of address lines of the microprocessor.
At least two memory devices are required in a microprocessor
system: one for the ROM and one for the RAM.
In an 8086 the high addresses in the memory map should always be
occupied by a ROM, while the low addresses in the memory map
should always be occupied by a RAM.
Memory organization
A memory device or memory chip must have three types of lines or
connections: Address, Data, Enable and Control.
Address Lines:
The input lines that select a memory location within the memory
device.
Decoders are used, inside the memory chip, to select a specific
location
The number of address pins on a memory chip specifies the
number of memory locations.
If ‘n’ specifies the number of address lines, then
Number of memory locations can be addressed = 2n
Memory organization
Data Lines:
The data pins are typically bi-directional in read-write
memories.
The number of data pins is related to the size of the
memory location .
For example, an 8-bit wide (byte-wide) memory device has 8
data pins
The number of data lines (m-bits) determines the size of each
location in the memory.
Memory Capacity
The number of bits/bytes that a semiconductor memory chip
can store is called its chip capacity
Memory Capacity = 2n x m
Memory organization
Memory organization
Chip select Read/Write Chip select Write Read
2n words 2n words
m-bits per word m-bits per word
m-data lines m-data lines
D0 – Dm-1 D0 – Dm-1
RAM Memory Chip RAM Memory Chip
Memory organization
Chip select Read
2n words
m-bits per word
m-data lines
D0 – Dm-1
ROM Memory Chip
Memory Interfacing
8086 Microprocessor
Memory organization in 8086
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8086 Microprocessor
Memory organization in 8086
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8086 Microprocessor
Memory organization in 8086
Available memory space = EPROM + RAM
Allot equal address space in odd and even bank for both
EPROM and RAM
Can be implemented in two IC’s (one for even and other for
odd) or in multiple IC’s
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8086 Microprocessor
Interfacing SRAM and EPROM
Memory interface Read from and write in to a set of
semiconductor memory IC chip
EPROM Read operations
RAM Read and Write
In order to perform read/ write operations,
Chip Select (CS) signal has to be generated
Control signals for read / write operations
Allot address for each memory location
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8086 Microprocessor
Interfacing SRAM and EPROM
Memory map of 8086
EPROM’s are mapped at FFFFFH
Facilitate automatic execution of monitor programs and creation of
interrupt vector table
RAM are mapped at the beginning; 00000H is allotted to RAM
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Memory Decoding
In general, all the memory locations are not implemented.
All the address are not used by the memory devices to select
particular memory locations.
The unused lines are used to generate chip select signals.
Basically, two techniques are used to decode the address
1. Absolute or Full decoding
2. Linear or Partial decoding
Full Decoding
– All of the higher address lines are decoded to select memory
chip, and the chip is selected only for the specified logic levels
on these high order address lines.
– Each memory location has unique address
– Disadvantages: it needs more hardware for decoding
Memory Decoding
Partial Decoding
All the address lines are not used to generate chip select,
basically used in small systems
Individual high order address lines are used to decode the chip
select for the memory chips using less hardware
Disadvantages: Each memory location has more than one
address called roll-over addresses (fold back or shading).
Decoding circuits
1.NAND gates
2.Decoders
3.Programmable Logic Devices(PLAs, PAL, GAL)
4.Comparators
Interface 8Kx8 EPROM chips to 8086. Select suitable address maps
1. The address of RAM may be selected anywhere in the 1MB
address space.
2. The address of EPROM/ROM may be selected such that the
address FFFF0H must lie in this space ( EPROM’s are mapped at
FFFFh since after reset ,the IP & CS are initialized to form
address FFFF0H)
To address 8K=23 x 210 = 213 , the processor needs 13 address lines
So address lines A0 – A12 used to address 8K locations
A13 – A19 are used to generate chip select signal
Address Map/ Address decoding Table
CHIPS A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH
EPROM
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 FE000H
To decoder To address lines of 4K Memory IC
Design an interface between 8086 CPU and Two chips of 16Kx8 EPROM and
two chips of 32Kx8 RAM. Select the starting address of EPROM suitably. The
RAM address must start at 00000h
CHIPS A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH
EPROM
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F8000H
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0FFFFH
RAM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000H
Decoders
Selected
A2 A1 A0
Output line
0 0 0 Y0
0 0 1 Y1
0 1 0 Y2
0 1 1 Y3
1 0 0 Y4
1 0 1 Y5
1 1 0 Y6
1 1 1 Y7
Decoders
Selected
B A
Output line
0 0 Y0
0 1 Y1
1 0 Y2
1 1 Y3
Interface two 4Kx8 EPROMs and two 4Kx8 RAM chips with 8086.
select suitable memory maps. Use decoder for generation of chip
select signals
CHIPS A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH
EPROM
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 FE000H
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 FDFFFH
RAM
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC000H
Design a memory system for 8086 microprocessor with 128Kb of
EPROM and 384Kb of RAM. Interface using 64Kb of memory chips
and use suitable address map
Address map table
CHIPS A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFFH
EPROM
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E0000H
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DFFFFH
RAM III
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0000H
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BFFFFH
RAM II
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0000H
1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9FFFFH
RAM I
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80000H
Chip Select signal generation
To Decoder input
Interface Diagram
Partial Decoding Technique
Design an 8086 based system with the following specifications:
64 KB EPROM
64 KB RAM
Use partial (linear) decoding scheme.
Draw the complete schematic of the design indicating address map.
Sol:
8086 is 16 bit μp so it is necessary to have odd and even memory banks.
Two 32 KB EPROMs and two 32 KB RAMs
For 64 KB RAM & EPROM need 16 address lines (A0-A15)
A0 & BHE are used to select even and odd banks
CHIPS A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS
X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EPROM
X X X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
X X X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RAM
X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chip select logic Interface Diagram
