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N-MOS Fabrication Guide

The document describes the process of fabricating an N-MOS transistor. 1. It starts with a p-type silicon substrate that has a thin layer of silicon dioxide grown on it. 2. Photolithography is used to pattern the silicon dioxide layer to form the source, drain, and gate areas. 3. A thin polysilicon layer is deposited and patterned to form the transistor gate. 4. N-type dopants are implanted to form the source and drain regions. 5. A thick silicon dioxide layer is deposited prior to adding metal contacts.

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119 views24 pages

N-MOS Fabrication Guide

The document describes the process of fabricating an N-MOS transistor. 1. It starts with a p-type silicon substrate that has a thin layer of silicon dioxide grown on it. 2. Photolithography is used to pattern the silicon dioxide layer to form the source, drain, and gate areas. 3. A thin polysilicon layer is deposited and patterned to form the transistor gate. 4. N-type dopants are implanted to form the source and drain regions. 5. A thick silicon dioxide layer is deposited prior to adding metal contacts.

Uploaded by

FARAZ UL ISLAM
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

N-MOS FABRICATION PROCESS

VLSI

EEE-466

Name: Faraz Al Islam


ID: 1610573 .
N-MOS
FABRICATION
PROCESS
Si-substrate

Fig. (1) Pure Si single crystal

------------------------
-------------------------
--------------------------
-------------------------

Fig. (2) P-type impurity is lightly


doped
N-MOS
FABRICATION Thick SiO2
(1 µm)
- - - PROCESS
---------------------
-------------------------
--------------------------
-------------------------

Fig. (3) SiO2 Deposited over si surface

Photoresist
Thick SiO2
(1 µm)

------------------------
-------------------------
--------------------------
-------------------------
Fig. (4) Photoresist is deposited
over SiO2 layer
UV Light

Mask-1

Photoresist
Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
Mask-1 is used to expose the SiO2
where S, D and G is to be formed.

Fig. (5) Photoresist layer is


exposed to UV Light through a
mask
N-MOS
FABRICATION
PROCESS

Polymerised
Photoresist

-------------------------------
----------------------------------
Thick SiO2
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (1 µm)
----------------------------------

Fig. (6) Developer removes unpolymerised photoresist. It


will cause no effect on Si surface
N-MOS
FABRICATION
PROCESS

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------

Fig. (7) Etching [HF acid is used] will remove SiO2


layer which is in direct contact with etching
solution
N-MOS
FABRICATION
PROCESS

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------

Fig. (7) unpolymerised photoresist is also etched


away [using H2SO4]
N-MOS
FABRICATION
PROCESS

Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------

Fig. (8) A thin layer of SiO2 grown over the entire chip surface
N-MOS
FABRICATION
PROCESS
Polysilicon layer
(1 – 2 µm)

-------------------------------
---------------------------------- Thin SiO2
Thick SiO2 (0.1 µm)
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(1 µm)
----------------------------------

Fig. (9) A thin layer of polysilicon is grown over the entire chip
surface to form GATE
N-MOS
FABRICATION
PROCESS Photoresist

Polysilicon
layer

------------------------------- Thin SiO2


---------------------------------- (0.1 µm)
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Thick SiO2
---------------------------------- (1 µm)

Fig. (10) A layer of photoresist is grown over polysilicon layer


UV Light

Mask-2

-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------
Mask-2 is used to deposit
Polysilicon to form gate.
Fig. (11) Photoresist is exposed to UV Light
Polysilicon
Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------

Fig. (12) Etching will remove that portion of Thin SiO2 which
is not exposed to UV light
Polysilicon used as GATE
(1 – 2 µm)

Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
-------------------------------
----------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
----------------------------------

Fig. (13) Polymerised photoresist is also stripped away


GAT
E
SOURCE DRAIN

Thin SiO2
(0.1 µm)

Thick SiO2
(1 µm)
- - - - - - - - - - - - -- -- --- - - -- -- - - - - - - - - - - -
--- -- -- - -
- - - - - - - - - - - - - - - - - - - n+ - - - - - - - - -
- - ---------
-- - - - - - - - - - - - n+ - -
- - - - - - - - - - - - --------- - - ----------- - - - - - - - -
-
-

Fig. (14) n+ Doping to form SOURCE and DRAIN


STEP - METALLIZATION

- - - - - - - - - - - - -- -- --- - - -- -- - - - - - - - - - - -
--- -- -- - -
- - - - - - - - - - - - - - - - - - - n+ - - - - - - - - - Thick SiO2
- - --------- Thick SiO2
-- - - - - - - - - - - - n+ - - (1 µm) (1 µm)
- - - - - - - - - - - - --------- - - ----------- - - - - - - - -
-
-

Fig. (15) A thick layer of SiO2 (1 µm) is again grown.


STEP - METALLIZATION

UV Light

Mask-3

Mask-3 is used to make contact cuts for S, D


and G.
Photoresist

- - - - - - - - - - - - -- -- --- - - -- -- - - - - - - - - - - -
--- -- -- - -
- - - - - - - - - - - - - - - - - - - n+ - - - - - - - - - Thick SiO2
- - --------- Thick SiO2
-- - - - - - - - - - - - n+ - - (1 µm) (1 µm)
- - - - - - - - - - - - --------- - - ----------- - - - - - - - -
-
-

Fig. (16) Photoresist is grown over thick SiO2. Selected areas of the poly GATE and SOURCE and
DRAIN are exposed where contact cuts are to be made
STEP - METALLIZATION

Mask-3

Photoresist

- - - - - - - - - - - - -- -- --- - - -- -- - - - - - - - - - - -
--- -- -- - -
- - - - - - - - - - - - - - - - - - - n+ - - - - - - - - - Thick SiO2
- - --------- Thick SiO2
-- - - - - - - - - - - - n+ - - (1 µm) (1 µm)
- - - - - - - - - - - - --------- - - ----------- - - - - - - - -
-
-

Fig. (17) The region of photoresist which is not exposed by UV light will become soft.
This unpolymerised photoresist and SiO2 below it are etched away.
STEP - METALLIZATION

Mask-3

Photoresist

- - - - - - - - - - - - -- -- --- - - -- -- - - - - - - - - - - -
--- -- -- - -
- - - - - - - - - - - - - - - - - - - n+ - - - - - - - - - Thick SiO2
- - --------- Thick SiO2
-- - - - - - - - - - - - n+ - - (1 µm) (1 µm)
- - - - - - - - - - - - --------- - - ----------- - - - - - - - -
-
-

Fig. (18) The contact cuts are formed for S, D and G (hardened photoresist is stripped
away).
STEP - METALLIZATION

Metal (1µm)

- - - - - - - - - - - - -- -- --- - - -- -- - - - - - - - - - - -
--- -- -- - -
- - - - - - - - - - - - - - - - - - - n+ - - - - - - - - - Thick SiO2
- - --------- Thick SiO2
-- - - - - - - - - - - - n+ - - (1 µm) (1 µm)
- - - - - - - - - - - - --------- - - ----------- - - - - - - - -
-
-

Fig. (19) Metal (aluminium) is deposited over the surface of whole chip (1 µm
thickness).
STEP - METALLIZATION

Photoresist

Metal (1µm)

--- ----
- - - - - - - - - - - - -- -- -- - - -- -- -- -- - - - - - - - - -
-- - - - -- - Thick SiO2 Thick SiO2
(1 µm) (1 µm)
- -
n+- - - -n+- - -
------------ -- ---------
- -
-- - - - - - - - - - - - --- ---------
- - - - - - - - Fig.
- - -(20)
- - -Photoresist
- - - - - - -is- deposited
- - - - - - -over
- - -the
- -metal.
STEP - METALLIZATION

UV Light

Mask-4

Photoresist
Metal (1µm)

--- ----
- - - - - - - - - - - - -- -- -- - - -- -- -- -- - - - - - - - - -
-- - - - -- - Thick SiO2 Thick SiO2
(1 µm) (1 µm)
- - - - - -n+
- - - - - - - - - - - - - -n+ --- ---------
- -
Mask-4 is used to deposit metal in contact cuts of S, D and
-- - - - - - - - - - - - -
G.
- - ---------
----------------------------------
Fig. (21) UV Light is passed through Mask-4 (with a aim of removing all metal other than metal
in contact-cuts).
STEP - METALLIZATION

Mask-4

Photoresist
Metal (1µm)

- - - - - - - - - - - - -- -- --- - - -- -- - - - - - - - - - - -
--- -- -- - -
- - - - - - - - - - - - - - - - - - - n+ - - - - - - - - - Thick SiO2
- - --------- Thick SiO2
-- - - - - - - - - - - - n+ - - (1 µm) (1 µm)
- - - - - - - - - - - - --------- - - ----------- - - - - - - - -
-
-

Fig. (22) Photoresist and metal which is not exposed to UV light are etched away.
STEP - METALLIZATION

SOURCE DRAIN
GAT
E

- - - - - - - - - - - - -- -- --- - - -- -- - - - - - - - - - - -
--- -- -- - -
- - - - - - - - - - - - - - - - - - - n+ - - - - - - - - -
- - ---------
-- - - - - - - - - - - - n+ - -
- - - - - - - - - - - - --------- - - ----------- - - - - - - - -
-
-

Fig. (23) Final n-MOS Transistor

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