module decoder_using_case (

input wire [3:0] binary_in , // 4 bit binary input

output reg [15:0] decoder_out , // 16-bit out
input wire enable // Enable for the decoder
);
always_comb
begin
decoder_out = 0;
if (enable) begin
case (binary_in)
4'h0 : decoder_out = 16'h0001;
4'h1 : decoder_out = 16'h0002;
4'h2 : decoder_out = 16'h0004;
4'h3 : decoder_out = 16'h0008;
4'h4 : decoder_out = 16'h0010;
4'h5 : decoder_out = 16'h0020;
4'h6 : decoder_out = 16'h0040;
4'h7 : decoder_out = 16'h0080;
4'h8 : decoder_out = 16'h0100;
4'h9 : decoder_out = 16'h0200;
4'hA : decoder_out = 16'h0400;
4'hB : decoder_out = 16'h0800;
4'hC : decoder_out = 16'h1000;
4'hD : decoder_out = 16'h2000;
4'hE : decoder_out = 16'h4000;
4'hF : decoder_out = 16'h8000;
end
end
// traditional testbench

module tb_decoder();
reg [3:0] binary_in;
reg enable;
wire [15:0] decoder_out;
decoder_using_case d1(.*);
initial begin
#10;
enable = 1'b0;
binary_in=4'b1001;
$display("enable = %d and decoder output = %h", enable, decoder_out);
#10;
enable = 1'b0;
binary_in=4'b1101;
$display("enable = %d and decoder output = %h", enable, decoder_out);
#10;
enable = 1'b1;
binary_in=4'b1001;
#5;
$display("enable = %d and decoder output = %h", enable, decoder_out);
#10;
enable = 1'b1;
binary_in=4'b1011;
#5;
$display("enable = %d and decoder output = %h", enable, decoder_out);
end
endmodule
// testbench using for loop

module tb_decoder();
reg [3:0] binary_in;
reg enable;
wire [15:0] decoder_out;
decoder_using_case d1(.*);
initial begin
#10;
enable = 1'b0;
binary_in=4'b1101;
$display("enable = %d and decoder output = %h", enable, decoder_out);
#10;
enable = 1'b0;
binary_in=4'b1001;
#5;
$display("enable = %d and decoder output = %h", enable, decoder_out);
#10;
enable = 1'b1;
for(int i=0;i<16;i++)
begin
binary_in++;
#10;
$display("enable = %d, decoder input = %h and output = %h", enable,binary_in,
decoder_out);
end
end
endmodule
//Randamization using $urandom_range function

module tb_decoder();
reg [3:0] binary_in;
reg enable;
wire [15:0] decoder_out;
decoder_using_case d1(.*);
initial begin

for(int i=0;i<16;i++)
begin
enable = $urandom_range(1);
binary_in = $urandom_range(15);
#10;
$display("enable = %d, decoder input = %h and output = %h", enable,binary_in, decoder_out);
end
end
endmodule
//Randamization with one input only (binary_in)

package ABC;
class decoder;
randc bit [3:0] binary_in;
constraint c1 {binary_in < 15;};
endclass
endpackage
module tb_decoder(); //Randamization with one input only (binary_in)
import ABC::decoder;
decoder d2=new(); package ABC;
reg enable;
class decoder;
reg [3:0] in;
wire [15:0] decoder_out; randc bit [3:0] binary_in;
decoder_using_case d1(in,decoder_out,enable); constraint c1 {binary_in < 15;};
initial begin endclass
repeat(4) begin endpackage
#10;
enable = 1'b0;
d2.randomize();
in = d2.binary_in;
#5;
$display("enable = %d and decoder input = %h and output = %h", enable,d2.binary_in, decoder_out);
end
enable = 1'b1;
for(int i=0;i<16;i++)
begin
d2.randomize();
in = d2.binary_in;
#10;
$display("enable = %d, decoder input = %h and output = %h", enable,d2.binary_in, decoder_out);
end
end
endmodule
//Randomization with both input variables (enable & binary_in)

package ABC;
class decoder;
randc bit [3:0] binary_in;
rand bit enable;
constraint c1 {binary_in < 15;};
endclass
endpackage
//Randomization with both input variables (enable & binary_in)

package ABC;
class decoder;
randc bit [3:0] binary_in;
rand bit enable;
constraint c1 {binary_in < 15;}; module tb_decoder();
endclass import ABC::decoder;
decoder d2=new();
endpackage
//reg enable;
reg [3:0] in,en;
wire [15:0] decoder_out;
decoder_using_case d1(in,decoder_out,en);
initial begin
for(int i=0;i<16;i++)
begin
d2.randomize();
in = d2.binary_in;
en = d2.enable;
#10;
$display("enable = %d, decoder input = %h and output = %h",
en,d2.binary_in, decoder_out);
end
end
endmodule