Computer Architecture
Lecture 1-1: Computer Abstraction and
Technology
Dr. Nguyen Minh Son
1
The Computer Revolution
Progress in computer technology
Underpinned by Moore’s Law
Makes novel applications feasible
Computers in automobiles
Cell phones
Human genome project
World Wide Web
Search Engines
Computers are pervasive
2
Classes of Computers
Desktop computers
General purpose, variety of software
Subject to cost/performance tradeoff
Server computers
Network based
High capacity, performance, reliability
Range from small servers to building sized
Embedded computers
Hidden as components of systems
Stringent power/performance/cost constraints
3
The Processor Market
Number of distinct processors sold between 1998 and
2002
4
Internet of Things
5
Internet of Things
6
What You Will Learn
How programs are translated into the machine
language
And how the hardware executes them
The hardware/software interface
What determines program performance
And how it can be improved
How hardware designers improve performance
What is parallel processing
7
Understanding Performance
Algorithm
Determines number of operations executed
Programming language, compiler, architecture
Determine number of machine instructions
executed per operation
Processor and memory system
Determine how fast instructions are executed
I/O system (including OS)
Determines how fast I/O operations are executed
8
Below Your Program
Application software
Written in high-level language
System software
Compiler: translates HLL code to
machine code
Operating System: service code
Handling input/output
Managing memory and storage
Scheduling tasks & sharing resources
Hardware
Processor, memory, I/O controllers
Levels of Program Code
High-level language
Level of abstraction closer
to problem domain
Provides for productivity
and portability
Assembly language
Textual representation of
instructions
Hardware representation
Binary digits (bits)
Encoded instructions and
data
10
Five classic components of a computer
Instruction decode
Control signals
Keyboard,
mouse, joystick
Monitor
ALU, Registers Primary memory
Cache
Secondary memory
11
Anatomy of a Computer
Output
device
Network
cable
Input Input
device device
13
Opening the Box
14
Inside the Processor (CPU)
Datapath: performs operations on data
Control: sequences datapath, memory, ...
Cache memory
Small fast SRAM memory for immediate access to data
15
Inside the Processor
AMD Barcelona: 4 processor cores
16
A Safe Place for Data
Volatile main memory
Loses instructions and data when power off
Non-volatile secondary memory
Magnetic disk
Flash memory
Optical disk (CDROM, DVD)
Networks
Communication and resource sharing
Local area network (LAN): Ethernet
Within a building
Wide area network (WAN): the Internet
Wireless network: WiFi, Bluetooth
18
Technology Trends
Electronics technology
continues to evolve
Increased capacity
and performance
Reduced cost
DRAM capacity
Year Technology Relative performance/cost
1951 Vacuum tube 1
1965 Transistor 35
1975 Integrated circuit (IC) 900
1995 Very large scale IC (VLSI) 2,400,000
2005 Ultra large scale IC 6,200,000,000
19
Defining Performance
Which airplane has the best performance?
Boeing 777 Boeing 777
Boeing 747 Boeing 747
BAC/Sud BAC/Sud
Concorde Concorde
Douglas Douglas DC-
DC-8-50 8-50
0 100 200 300 400 500 0 2000 4000 6000 8000 10000
Passenger Capacity Cruising Range (miles)
Boeing 777 Boeing 777
Boeing 747 Boeing 747
BAC/Sud BAC/Sud
Concorde Concorde
Douglas Douglas DC-
DC-8-50 8-50
0 500 1000 1500 0 100000 200000 300000 400000
Cruising Speed (mph) Passengers x mph
20
Response Time and Throughput
Response time
How long it takes to do a task
Throughput
Total work done per unit time
e.g., tasks/transactions/… per hour
How are response time and throughput
affected by
Replacing the processor with a faster version?
Adding more processors?
We’ll focus on response time for now…
21
Relative Performance
Define Performance = 1/Execution Time
“X is n time faster than Y”
Performanc e X Performanc e Y
Execution time Y Execution time X n
Example: time taken to run a program
10s on A, 15s on B
Execution TimeB / Execution TimeA
= 15s / 10s = 1.5
So A is 1.5 times faster than B
22
CPU Clocking
Operation of digital hardware governed by a
constant-rate clock
Clock period
Clock (cycles)
Data transfer
and computation
Update state
Clock period: duration of a clock cycle
e.g., 250ps = 0.25ns = 250×10–12s
Clock frequency (rate): cycles per second
e.g., 4.0GHz = 4000MHz = 4.0×109Hz
23
Power Trends
In CMOS IC technology
Power Capacitive load Voltage 2 Frequency
×30 5V → 1V ×1000
24
Reducing Power
Suppose a new CPU has
85% of capacitive load of old CPU
15% voltage and 15% frequency reduction
Pnew Cold 0.85 (Vold 0.85) 2 Fold 0.85
2
0.85 4
0.52
Pold Cold Vold Fold
The power wall
We can’t reduce voltage further
We can’t remove more heat
How else can we improve performance?
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Multiprocessors
Multicore microprocessors
More than one processor per chip
Requires explicitly parallel programming
Compare with instruction level parallelism
Hardware executes multiple instructions at once
Hidden from the programmer
Hard to do
Programming for performance
Load balancing
Optimizing communication and synchronization
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Manufacturing ICs
Yield: proportion of working dies per wafer
27
AMD Opteron X2 Wafer
X2: 300mm wafer, 117 chips, 90nm technology
X4: 45nm technology
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Integrated Circuit Cost
Cost per wafer
Cost per die
Dies per wafer Yield
Dies per wafer Wafer area Die area
1
Yield
(1 (Defects per area Die area/2)) 2
Nonlinear relation to area and defect rate
Wafer cost and area are fixed
Defect rate determined by manufacturing process
Die area determined by architecture and circuit
design
29
SPEC CPU Benchmark
Programs used to measure performance
Supposedly typical of actual workload
Standard Performance Evaluation Corp (SPEC)
Develops benchmarks for CPU, I/O, Web, …
SPEC CPU2006
Elapsed time to execute a selection of programs
Negligible I/O, so focuses on CPU performance
Normalize relative to reference machine
CINT2006 (integer) and CFP2006 (floating-point)
n
n
Execution time ratio
i1
i
30
Pitfall: MIPS as a Performance Metric
MIPS: Millions of Instructions Per Second
Doesn’t account for
Differences in ISAs between computers
Differences in complexity between instructions
Instruction count
MIPS
Execution time 10 6
Instruction count Clock rate
Instruction count CPI CPI 10 6
10 6
Clock rate
CPI varies between programs on a given CPU
31
Concluding Remarks
Cost/performance is improving
Due to underlying technology development
Hierarchical layers of abstraction
In both hardware and software
Instruction set architecture
The hardware/software interface
Execution time: the best performance measure
Power is a limiting factor
Use parallelism to improve performance
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