Computer Systems Architecture

AICT001-3-2

Registers
Diploma in Computing and IT: Level - 1

Prepared by: TPM First Prepared on: 03-06-08 Last Modified on: 20--06-08
Quality checked by: KNT
Copyright 2008 Asia Pacific Institute of Information Technology
 Topic & Structure of the lesson
Registers

• What is a Register?
• Types of Registers
• Operations of Registers
• Register Transfer Language

Computer Systems Architecture Slide 2 of 51

 Learning Outcomes
Registers

• At the end of the session you will be able to:-

– Explain what is a register.
– Apply the idea of Status Flags for dynamic
evaluation of the ALU status.
– Calculate the current value of the PSW Register.
– Apply Complements to effectively perform
subtraction, ‘the CPU’s way’.

Computer Systems Architecture Slide 3 of 51

 Key Terms you must be able to use
Registers

• If you have mastered this topic, you should be able to

use the following terms correctly in your assignments
and exams:-
– register
– Accumulator, Base register, Counter register, Data register
– Program counter
– Instruction register
– Memory address register
– Memory data register
– PSW
– flag registers
Computer Systems Architecture Slide 4 of 51
 Central Processing Unit (CPU)
Registers

• CPU has three important parts:-

– ALU (Arithmetic and Logic Unit)
– Control Unit
– Registers
ALU Control
Unit
CPU

High Speed Registers

Computer Systems Architecture Slide 5 of 51

 What is a Register?
Registers

• Small, permanent storage locations within the

CPU used for a particular purpose.
• Manipulated directly by the Control Unit.
• Wired for specific function.
• Size in bits or bytes (not MB like memory).
• Can hold data, an address or an instruction.

Computer Systems Architecture Slide 6 of 51

 Use of Registers
Registers

• CPU must have some working space (temporary

storage)
– Scratchpad for currently executing program.
– Holds data needed quickly or frequently.
• Stores information about status of CPU and currently
executing program.
– Hold data being processed.
– Hold an instruction to be executed.
– Hold a memory address.
– Hold status codes.
Computer Systems Architecture Slide 7 of 51
 Register Operations
Registers

• Registers are also used for:-

– Storing values from other locations (registers and
memory).
– Addition and subtraction.
– Shifting or rotating data.
– Testing contents for conditions such as zero or
positive.

Computer Systems Architecture Slide 8 of 51

 Internal Structure of the CPU
Registers

• A processor includes both.

• User Visible Registers (UVR)
or General Purpose
Registers (GPR) and User
Invisible Registers (UIR) or
Control/Status Registers.
– User Visible Registers
• may be general purpose or
have a special use.
– User Invisible Registers
• are used to control the
operation of the CPU.

Computer Systems Architecture Slide 9 of 51

 Register Organisation
Registers

• Registers may be visible to the programmer, or

used solely by the CPU (invisible) and special
OS functions.
• Depending on the CPU architecture, registers
may be general purpose, or some may have
single special purpose.
• General purpose: can be used for any
operation; hold address as well as data. Early
computers had only one, the accumulator.
Numbers limited by cost versus ability to make
use of greater numbers.
Computer Systems Architecture Slide 10 of 51
 User Visible Registers/General Purpose
Registers
Registers

• General Purpose Registers

– Hold intermediate results or data values, for
example, loop counters.
– Equivalent to LMC’s calculator (or the
accumulator).
– Typically several dozen in current CPUs.

Computer Systems Architecture Slide 11 of 51

 x86 General Purpose Registers
Registers

16bits
Accumulator ax
Base bx
Counter cx
Data dx
Base Pointer bp
Stack Pointer sp
Source Index si
Destination Index di
Computer Systems Architecture Slide 12 of 51
 User Visible Registers/General Purpose
Registers
Registers

• While General Purpose Registers can be used by most

instructions, they may be optimised for specific operations,
such as the accumulator.
• If registers are specialised then their use will be implicit and
need not be mentioned in the instruction. This means the
instruction will be shorter and less memory required.
• Example:-
– Data Registers : some instructions expect to use certain registers to
hold data such as; MUL CX whereas the other operand is assumed to be
in AX and result will be placed in AX.
– Address Registers : Stack Pointer, Segment Pointer, and Index
Pointer.

Computer Systems Architecture Slide 13 of 51

 User Invisible Registers (UIR)
Registers

• Every processor contains some special

purpose or control registers. These are
generally contained within the control unit.
Several important ones are:-
– Program Count Register (PC)
– Instruction Register (IR)
– Memory Address Register (MAR)
– Memory Data Register (MDR)
– Status/Flag Registers
Computer Systems Architecture Slide 14 of 51
 Program Counter (PC)
Registers

• Program Counter (PC)

– Also called instruction pointer (IP).
– Contains the address of the next instruction to be
fetched from memory; it is automatically updated
by the CPU during Fetch/Execute cycle.
– May be forced to change: for example a “jump”
instruction.
– Usually initialise to zero when machine starts, or is
reset.
Computer Systems Architecture Slide 15 of 51
 Instruction Register (IR)
Registers

• Instruction Register (IR)

– copy of the current instruction being executed.
– stores instruction fetched from memory.

Computer Systems Architecture Slide 16 of 51

 Instruction Register (IR)
Registers

A dedicated register in the CPU which contains the

actual current instruction.

Op Code + Address

What To Do Location of Data

Simple 16-bit example: 1101 101101100100

Computer Systems Architecture Slide 17 of 51

 MAR and MDR
Registers

• Memory Address Register (MAR)

– holds address of memory location and connected to address bus
– Contains Address in memory to find or place data.
• Memory Data Register (MDR)
– also referred to as the Memory Buffer Register (MBR).
– holds data being transferred to/from memory - connected to data bus
– Contains Actual Data to be placed in location given in MAR, or which has
been retrieved from location given in MAR.
• The MAR & MDR are used for data exchange between memory
and the CPU.

Computer Systems Architecture Slide 18 of 51

 Status/Flags Registers
Registers

• Status/Flags Registers
– sometimes called Program Status Word (PSW) Registers.
– contain individual bit fields indicating status information from
program execution, often error conditions.
– shows status of CPU and currently executing program.
– Flags (one bit Boolean variable) to track condition like
arithmetic carry and overflow, power failure, internal
computer error.

Computer Systems Architecture Slide 19 of 51

 Program Status Word (PSW)
Registers

• Types of Status Flags (1- bit Cells)

– Sign Flag (S)
• This Flag is set (assigned a value of 1) if the result of
the arithmetic operation is negative. Otherwise it is
reset (assigned a value of 0).
– Zero Flag (Z)
• This Flag is set (assigned a value of 1) if the result of
the arithmetic operation is zero. Otherwise it is reset
(assigned a value of 0).

Computer Systems Architecture Slide 20 of 51

 Program Status Word (PSW)
Registers

• Types of Status Flags (1- bit Cells)

– Half-Carry (HC) Flag
• This Flag is set (assigned a value of 1) if there is a
carry from the HSB (Half Significant Bit position).
Otherwise it is reset (assigned a value of 0).
– Carry (C) Flag
• This Flag is set (assigned a value of 1) if there is a
carry from the MSB (Most Significant Bit position).
Otherwise it is reset (assigned a value of 0).

Computer Systems Architecture Slide 21 of 51

 Program Status Word (PSW)
Registers

• Types of Status Flags (1- bit Cells)

– Overflow (V) Flag
• This Flag is set (assigned a value of 1) if there is a
carry from the MSB (Most Significant Bit position or the
MSB -1) Bit positions but not both. Otherwise it is reset
(assigned a value of 0).
– Parity (P) Flag
• For Even Parity, this Flag is set (assigned a value of 1)
if the number of 1s in the result inclusive of parity is
even. Otherwise it is reset (assigned a value of 0).
Computer Systems Architecture Slide 22 of 51
 Program Status Word (PSW)
Registers

• Example
– A 16bit PSW
– Each position is a binary value representing a
true/false condition.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S 0 0 P 0 1 Z HC 1 1 0 C 1 0 V 1
PSW

Computer Systems Architecture Slide 23 of 51

 Condition Codes Register
Registers

Example:
Given that the current ALU operation on two 8-bit operands,
12 and 16 is Addition, encode the value of the following 16-bit
Program Status Word (PSW), using hexadecimal notation.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
S 0 0 P 0 1 Z HC 1 1 0 C 1 0 V 1
Solution: PSW
a) Represent the operands using 8-bit signed 2’s complement
representation.
b) Perform the operation (Addition) and compute the result.
c) Find out the values of the binary Flags: S, Z, HC, C, P, V
d) Fill in the entries in the PSW Register.
e) Encode the Register contents using hexadecimal notation.
Computer Systems Architecture Slide 24 of 51
 Condition Codes Register
Registers

Decimal Binary Decimal 2s Complements

12 00001100 12 11110100
16 00010000 16 11110000

11110100 00011011
+ 11110000 + 1
111100100 00011100

Computer Systems Architecture Slide 25 of 51

 Register Design Issues
Registers

• Common flags in status register include: overflow,

underflow, attempt to divide by zero +ve, -ve, zero
result, interrupt enable/disable, supervisor/user mode
etc. These may be partially available to user
programs, but generally only read, not write.
• Number of registers vary between processors. More
registers do not always improve performance. The
more registers, the longer the instruction.
• For example; 8 registers mean that a register operand
needs to be 3 bits, whereas 32 registers require 5 bits
for the operand.
Computer Systems Architecture Slide 26 of 51
 How Registers Work : Fetch-Execute Cycle
Registers

• These 4 registers; PC, IR, MAR & MDR are

used for the movement of data between the
CPU and memory.
• The PC is updated by the CPU after each
instruction fetch.
• The fetched instruction is loaded into the IR.
• Data is exchanged using the MAR & MDR.
• User-visible registers exchange data with the
MDR.
Computer Systems Architecture Slide 27 of 51
 Fetch-Execute Example: Load Accumulator
Registers

Assume: Simple Eight bit system.

Thirty-two memory locations (0 to 31).
“Load” instruction is 010.
Value in location 15 is ten (ie: binary 00001010)
PC is at 5, about to increment.
The instruction, 01001111, is in location 6.

Then ...

Computer Systems Architecture Slide 28 of 51

 Register Transfer Language (RTL)
Registers

Location 31

PC: 00110

IR: (previous)

MAR: (previous) 15: 00001010

MDR: (previous)

A: (previous) 06: 01001111

Location 0

Computer Systems Architecture Slide 29 of 51

 MAR loaded with PC: PC -> MAR
Registers

Location 31

PC: 00110

IR: (previous)

MAR: 00110 15: 00001010

MDR: (previous)

A: (previous) 06: 01001111

Location 0

Computer Systems Architecture Slide 30 of 51

 Registers

Location 31

PC: 00110

IR: (previous)

MAR: 00110 15: 00001010

MDR: (previous)

A: (previous) 06: 01001111

Location 0

Computer Systems Architecture Slide 31 of 51

 Registers

Location 31

PC: 00110

IR: (previous)

MAR: 00110 15: 00001010

MDR: 01001111

A: (previous) 06: 01001111

Location 0

Computer Systems Architecture Slide 32 of 51

 MDR copied to IR: MDR -> IR
Registers

Location 31

PC: 00110

IR: 01001111

MAR: 00110 15: 00001010

MDR: 01001111

A: (previous) 06: 01001111

Location 0

Computer Systems Architecture Slide 33 of 51

 IR [ address part ] -> MAR
Registers

Location 31

PC: 00110

IR: 01001111

MAR: 01111 15: 00001010

MDR: 01001111

A: (previous) 06: 01001111

Location 0

Computer Systems Architecture Slide 34 of 51

 Location in MAR (01111) Accessed
Registers

Location 31

PC: 00110

IR: 01001111

MAR: 01111 15: 00001010

MDR: 01001111

A: (previous) 06: 01001111

Location 0

Computer Systems Architecture Slide 35 of 51

 Contents of 01111 loaded into MDR
Registers

Location 31

PC: 00110

IR: 01001111

MAR: 01111 15: 00001010

MDR: 00001010

A: (previous) 06: 01001111

Location 0

Computer Systems Architecture Slide 36 of 51

 IR [op code] executed: MDR -> A
Registers

Location 31

PC: 00110

IR: 01001111

MAR: 01111 15: 00001010

MDR: 00001010

A: 00001010 06: 01001111

Location 0

Computer Systems Architecture Slide 37 of 51

 Increment PC: PC = PC + 1
Registers

Location 31

PC: 00111

IR: 01001111

MAR: 01111 15: 00001010

MDR: 00001010

A: 00001010 06: 01001111

Location 0

Computer Systems Architecture Slide 38 of 51

 Finished
Registers

Location 31

PC: 00111

IR: 01001111

MAR: 01111 15: 00001010

MDR: 00001010

A: 00001010 06: 01001111

Location 0

Computer Systems Architecture Slide 39 of 51

 Register Transfer Language
Registers

• Format of RTL Statement:

Parallel Transfer
– Register source -------------> Register destination
• The connection between Registers:-
– Permanent linkage
– Switched linkage (triggered by control signal)
• Registers used can be GPR or UVR (such as AX,
BX..) as well as UIR (such as PC, IR,......)
• RTL is used to represent the FETCH Phase and
EXECUTE Phase in the Instruction Cycle.
Computer Systems Architecture Slide 40 of 51
 LMC vs. CPU
Registers

Fetch and
Execute
Cycle

Computer Systems Architecture Slide 41 of 51

 Fetch-Execute Cycle
Registers

• Two-cycle process because both instructions

and data are in memory.
• Fetch
– Decode or find instruction, load from memory into
register and signal ALU.
• Execute
– Performs operation that instruction requires.
– Move/transform data.
Computer Systems Architecture Slide 42 of 51
 Load Fetch/Execute Cycle
Registers

1. PC -> MAR Transfer the address from the PC to

the MAR

2. MDR -> IR Transfer the instruction to the IR

3. IR(address) -> MAR Address portion of the instruction

loaded in MAR
4. MDR -> A Actual data copied into the
accumulator
5. PC + 1 -> PC Program Counter incremented

Computer Systems Architecture Slide 43 of 51

 Store Fetch/Execute Cycle
Registers

1. PC -> MAR Transfer the address from the PC to

the MAR
2. MDR -> IR Transfer the instruction to the IR

3. IR(address) -> MAR Address portion of the instruction

loaded in MAR
4. A -> MDR* Accumulator copies data into MDR

5. PC + 1 -> PC Program Counter incremented

*Notice how Step #4 differs for LOAD and STORE

Computer Systems Architecture Slide 44 of 51

 The Store Instruction
Registers

PC  MAR
Fetch
MDR  IR
IR[address]  MAR time
Execute A  MDR
PC + 1  PC

Computer Systems Architecture Slide 45 of 51

 ADD Fetch/Execute Cycle
Registers

1. PC -> MAR Transfer the address from the PC to

the MAR

2. MDR -> IR Transfer the instruction to the IR

3. IR(address) -> MAR Address portion of the instruction

loaded in MAR
4. A + MDR -> A Contents of MDR added to contents
of accumulator
5. PC + 1 -> PC Program Counter incremented

Computer Systems Architecture Slide 46 of 51

 The Add Instruction
Registers

PC  MAR
Fetch
MDR  IR
IR[address]  MAR time
Execute A + MDR  A
PC + 1  PC

Computer Systems Architecture Slide 47 of 51

 Quick Review Questions
Registers

1. What is a register? Describe briefly the

operations of registers.
2. Why are there two different registers(MAR
and MDR) associated with memory?
3. Describe the LOAD and STORE instructions
of the Fetch/Execute cycle in terms of
Register Transfer Language (RTL).

Computer Systems Architecture Slide 48 of 51

 Summary of Main Teaching Points
Registers

• Registers
– Within the CPU, the most important components
are registers.
– Two types of registers are Visible and Invisible
registers.
• Register Transfer language
– To show the steps of the CPU fetch-execute cycle
for the instructions.

Computer Systems Architecture Slide 49 of 51

 Question and Answer Session
Registers

Q&A

Computer Systems Architecture Slide 50 of 51

 Next Session
Registers

• Tutorial
– Registers.

Computer Systems Architecture Slide 51 of 51