DC BIASING - BJT
[Link] Anantha Rufus
Assistant Professor / ECE
Vel Tech University
Introduction
• The analysis or design of a transistor amplifier requires
knowledge of both the dc and ac response of the system. In
fact, the amplifier increases the strength of a weak signal by
transferring the energy from the applied DC source to the
weak input ac signal The analysis or design of any electronic
amplifier therefore has two components:
• The dc portion and
• The ac portion
•During the design stage, the choice of parameters for the
required dc levels will affect the ac response.
• What is biasing circuit?
• Biasing: Application of dc voltages to establish a fixed
level of current and voltage.
Purpose of the DC biasing circuit
• To turn the device “ON”
• To place it in operation in the region of its characteristic where the device
• operates most linearly .
• Proper biasing circuit which it operate in linear region and circuit have
centeredQ-point or midpoint biased
• Improper biasing cause Improper biasing cause
• „Distortion in the output signal
• „Produce limited or clipped at output signal
Important Basic Relationships
I E IC I B
IC
IB
I E ( 1)I B I C
V CB V CE V BE
V CB V CE V BE
Operating Point
Limited to The device can
𝑉𝐶𝐸 = 0 and react to both
𝐼𝐶 = 0 positive and
negative input
signal
The device
operating near max
voltage and power
No bias
5
6
Operation Region
7
• BJT need to be operate in active region used
as amplifier.
• The cutoff and saturation region used as a
switches.
• For the BJTs to be biased in its linear or active
operating region the following must be true:
BE junction: forward biased
BC junction: reverse biased
Operation Region
Linear region:
• BE junction forward-bias (𝑉𝐵𝐸 = 0.7 𝑉)
• BC junction reverse-bias (𝑉𝐶𝐵 )
Cutoff region:
• BE junction reverse-bias (𝑉𝐵𝐸 )
• BC junction reverse-bias (𝑉𝐶𝐵 )
Saturation region:
• BE junction forward-bias (𝑉𝐵𝐸 = 0.7 𝑉)
• BE junction forward-bias (𝑉𝐶𝐵 )
9
DC Biasing Circuits
• Fixed-bias circuit
• Emitter-stabilized bias circuit
• Collector-emitter loop
• Voltage divider bias circuit
• DC bias with voltage feedback
Fixed Bias Configuration
• The configuration:
12
Fixed Bias Configuration
The network can be isolated from the
indicated ac levels by replacing the capacitors
with an open-circuitequivalent [ the reactance
of a capacitor for dc is ∞Ω]
13
Fixed Bias Configuration 2 loops
14
Fixed Bias Configuration
DC equivalent circuit:
1. BE loop
−𝑉𝐶𝐶 + 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 = 0
Write KVL equation 𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵
15
Fixed Bias Configuration
DC equivalent circuit: 𝐼𝐶 = 𝛽𝐼𝐵
2. CE loop
Write KVL equation
−𝑉𝐶𝐶 + 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸 = 0
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
16
Fixed Bias Configuration
DC equivalent circuit:
𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵
𝐼𝐶 = 𝛽𝐼𝐵
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸
Find 𝑉𝐵 , 𝑉𝐶 , and 𝑉𝐸
𝑉𝐵𝐸 = 𝑉𝐵 − 𝑉𝐸
17
Fixed Bias Configuration
18
Transistor Saturation
• “Saturation”: reached their maximum value.
• In transistor, saturation region is where the
current is in maximum value for the particular
design.
• Normally avoided:
– The BC junction is no longer reverse-biased
– As a result, the output amplified signal will be distorted.
[𝑉 , 𝑉 ]
𝐶𝐸 𝐶𝐵
19
Transistor Saturation
Actual Approximate
𝑉𝐶𝐸 = 0,
𝐼𝐶 = 𝐼𝐶𝑠𝑎𝑡
𝑉𝐶𝐸 = 0
Notice that in saturation region, 𝑉𝐶𝐸 = 0
20
Saturation Level
For the fixed-bias configuration, to determine the
saturation current, 𝐼𝐶 𝑠𝑎𝑡 , the equivalent circuit is:
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
𝑉𝐶𝐸 = 0 𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸
21
Transistor Saturation
• “Saturation”: reached their maximum value.
• In transistor, saturation region is where the
current is in maximum value for the particular
design.
• Normally avoided:
– The BC junction is no longer reverse-biased
– As a result, the output amplified signal will be distorted.
[𝑉 , 𝑉 ]
𝐶𝐸 𝐶𝐵
22
Transistor Saturation
Actual Approximate
𝑉𝐶𝐸 = 0,
𝐼𝐶 = 𝐼𝐶𝑠𝑎𝑡
𝑉𝐶𝐸 = 0
Notice that in saturation region, 𝑉𝐶𝐸 = 0
23
Load Line Analysis
• The dc operation of a transistor circuit can be described graphically using a dc load
line.
• This is a straight line draw on the characteristic curves form the saturation value to
the cutoff value.
25
Load Line Analysis
26
Load Line Analysis
How
Step 1:toFind
plot load
𝐼𝐶max line:
when 𝑉𝐶𝐸 = 0
From 𝑉𝐶𝐸 = 𝑉𝐶𝐶 – 𝐼𝐶 𝑅𝐶 ,
and 𝑉𝐶𝐸 = 0
𝑉𝐶𝐶
𝐼𝐶 =
𝑅𝐶
27
Load Line Analysis
How
Step 2:toFind
plot
𝑉𝐶𝐸load
max
line:𝐼𝐶
when = 0
From 𝑉𝐶𝐸 = 𝑉𝐶𝐶 – 𝐼𝐶 𝑅𝐶 ,
and 𝐼𝐶 = 0
𝑉𝐶𝐸 = 𝑉𝐶𝐶
28
Load Line Analysis
𝑉𝐶𝐶
How to plot load line: 𝐼𝐶 =
𝑅𝐶
Step 3: Draw straight line
𝑉𝐶𝐸 = 𝑉𝐶𝐶
29
Load Line Analysis
The characteristic becomes:
Q-point is establish from IB given
30
Load-Line Analysis
The characteristic becomes:
𝑰𝑩 𝑹𝐂 𝑽𝑪𝑪
Increase or decrease of
31
FIXED BIAS CIRCUIT
DISADVANTAGES
• Unstable – because it is too dependent on β
and produce width change of Q-point
• For improved bias stability , add emitter
resistor to dc bias.
