Asynchronous Sequential
Circuits
Asynch. Seq. Ckt.
Asynchronous circuits don’t use
clock pulses
State transitions by changes in inputs
Clockless storage elements or
Delay elements (D Latch)
Normally much harder to design
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Asynch. Sequential Circuit
x1 z1
x2 z2
inputs outputs
Combinational
xn zm
Circuit
y1 Y1
y2 Y2 Next
Current
State
State yk Yk (Excitation
(Secondary
Variables)
Variables)
delay
delay
delay
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Properties of Asynch. Seq Circuit
yi = Yi in steady state (but may be
different during transition)
Simultaneous change in two (or
more) inputs is prohibited.
The time between two changes must
be less than the time of stability.
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Advantages and Disadvantages
• Advantages:
Low power
High performance
No need for clock
• Disadvantages:
Complexity of design process
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Analysis
y1
x Y1
y2
Y2
1. Find feedback loops and name feedback variables appropriately.
2. Find boolean expressions of Yi’s in terms of yi’s and inputs.
Y1 = x.y1 + x’.y2
Y2 = x.y1’ + x’.y2
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Analysis
3. Draw a map:
rows: yi’s
columns: inputs
entries: Yi’s
x x x
y1 y2 0 1 y1 y2 0 1 y1 y2 0 1
00 0 0 00 0 1 00 00 01
01 1 0 01 1 1 01 11 01
11 1 1 11 1 0 11 11 10
10 0 1 10 0 0 10 00 10
Y1 = x.y1 + x’.y2 Y2 = x.y1’ + x’.y2 (Transition Table) Y1 Y2
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Analysis
4. To have a stable state, Y must be = y
(circled) 0
x
1y1 y2
00 00 01
01 11 01
(Transition Table) Y1 Y2
11 11 10
10 00 10
At y1y2x = 000, if x: 0 1
then Y1Y2: 00 01
then y1y2 = 01 (2nd row): stable
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Analysis
In general, if an input takes the circuit to
an unstable state, yi’s change until a
stable state is found.
x
y1 y2 0 1
00 00 01
General state of circuit:
01 11 01
y1y2x:
There are 4 stable states: 11 11 10
000, 011, 110, 101
10 00 10
and 4 unstable states.
001,010,111,100
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State Table
As synchronous:
next state
present
state X 0 X 1
00 00 01
01 11 01
10 00 10
11 11 10
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Flow Table
The binary representation of a state in transition table with a letter
represents a Flow Table (with symbolic states):
x
0 1
a a b From the above
transition table:
b c b
00 a
c c d 01 b
d a d
11 c
10d
The above table is called primitive flow table as there is only one
stable state for each row.
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Flow Table: Example 2
Two states, two inputs, one output.
x1 x2
00 01 11 10
a a ,0 a ,0 a ,0 b ,0
b a ,0 a ,0 b ,1 b ,0
Each row has more than one stable state.
If x1 = 0, state is a.
If x1x2 = 00 x1x2 = 10, then state becomes b.
For x1x2 = 11, state is either a or b.
If previously in x1x2 = 01, keeps state a,
If previously in x1x2 = 10, keeps state b.
Reminder: cannot go from 00 to 11. 12
Circuit Design
From flow table to circuit:
Assign a unique binary value to each state,
x1 x 2 x1 x2
00 01 11 10 00 01 11 10
y
a a ,0 a ,0 a ,0 b ,0 0 0 ,0 0 ,0 0 ,0 1 ,0
b a ,0 a ,0 b ,1 b ,0 1 0 ,0 0 ,0 1 ,1 1 ,0
x1 x2 x1 x2
00 01 11 10 00 01 11 10
y y
0 0 0 0 1 0 0 0 0 0
1 0 0 1 1 1 0 0 1 0
Map for Y (=x1x2’+x1y) Map for output z (=x1x2y)
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Circuit Diagram
z = x1x2y
x1
x2 Y
Y = x1x2’+x1y
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Race Condition
If two (or more) state variables
change in response to a change in
an input, there is a race condition.
E.g. from 00 to 11, due to delays
00 01 11 OR
00 10 11.
• Critical Race:
If final steady state depends on the
order of changes in state vars.
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Race: Examples
• Noncritical Cases:
x x
y1y2 0 1
y1y2 0 1
00 00 11 00 00 11
01 11 01 01
11 11 11 01
10 11 10 11
00 11 00 11 01
00 01 11 00 01
00 10 11 00 10 11 01
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Race: Examples
• Critical Cases:
x x
y1y2 0 1
y1y2 0 1
00 00 11 00 00 11
01 11 01 01
11 11 11 11
10 10 10 10
00 11 00 11
00 01 11 00 01
00 10 00 10
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