POST GDSII CHECKS
GDSII
GDSII Stream format is the standard file format for
transferring/archiving graphical design data
It is a binary file format that represents layout data in a hierarchical
format
Data such as labels, shapes, layer information and other 2D and
3D layout geometric data
This file is then provided to the fabrication plant that uses this file
to etch the chip based on the parameters provided in the file
PnR FLOW
I. NetlistIn & Floorplan
II. Placement
III. Clock Tree Synthesis
IV. Routing
Checks
1. Physical verification
2. Equivalence Checking
3. Timing Analysis
EQUIVALENCE CHECKS
Equivalence check will compare the netlist we started out with (pre
layout/synthesis netlist) to the netlist written out by the tool after PnR
(post layout netlist)
Physical verification
After routing, PnR tool should give zero DRC/LVS violations
However, the PnR tool deals with abstracts like FRAM or LEF
views. We use dedicated physical verification tools for signoff
LVS and DRC checks
1. Hercules from Synopsis
2. Assura from Cadence
3. Calibre from Mentor Graphics
The major checks are:
1. DRC
2. LVS
3. Antenna
DRC
The first question that comes to the mind of an ASIC designer is “what is
a design rule check?”, why we are doing this at SOC level, and what
would happen if the design does not meet the design rule checks?
DRC checks determine if the layout satisfies a set of rules required for
manufacturing. The most common of these are spacing rules between
metals, minimum width rules, via rules etc
Types of drc’s
1. Minimum
width and
spacing for metal
Cont..
CASE A: Shorts violation
Description: In short violation, two or more
different net segments of the same layer were
crossing each other
Solution:
To fix this type of short violation, different net
segments on same layer has to be placed away
so that they will not cross each other and also
Cont..
CASE B: Different Spacing violation
Description : In some cases, the via enclosure is
quite large compared to metal width due to large
via enclosure. The other long net passing each
other and dropped in via will create a different
spacing violation.
Solution:
To fix this type of spacing violation, the net needs
Cont..
CASE C: Same layer spacing with net and cell
geometry blockage
Description: there is same layer spacing with the
cell blockage and via enclosure
Solution:
To fix violation, we should check net is routed in
non-preferred direction or not , the inserted via
Cont..
CASE D: Minimum area requirement
Description: There is a minimum area requirement
for every segment in a layout.
Solution:
To meet this minimum area requirement, we need
to increase the area of the segment that will not
violate the other design rule (spacing, short)
Cont..
CASE E: VIA Misalignment
Description: This type violation pops up when two
different layer of same logical net connected by
inserting the VIA. If inserted via is not aligning
with the metal crossing we are seeing the VIA
misalignment
Solution:
Proper VIA instance need to insert so the VIA
LVS
LVS check includes following comparisons:
1. Number of devices in schematic and its layout
2. Type of devices in schematic and its layout
3. Number of nets in schematic and its layout
Cont..
Some of the LVS errors are:
Shorts – Wires that should not be connected are overlapping
Opens – Connections are not complete for certain nets.
Parameter mismatch – LVS also checks for parameter mismatches. e.g.
It may match a resistor in both layout and schematic, but the resistor
values may be different. This will be reported as a parameter
mismatch.
Unbound pins – If the pins don’t have a geometry, but all the connection
to the net are made, and unbound pin is reported
