Unit V
Digital Signal Processors –I
Introduction
• DSP processors are microprocessors designed for
efficient mathematical manipulation of digital signals.
• DSPs tend to run one program, not many programs.
– Hence OSes are much simpler, there is no virtual memory
• DSPs usually run applications with hard real-time
constraints:
– You must account for anything that could happen in a time
slot
• DSPs usually process infinite continuous data streams.
Computer Architectures for signal processing
• A Typical DSP System
Computer Architectures for signal processing
Need for DSP Architecture
•Harvard Architecture
• Filtering, correlation, •Pipelining
FFT •Fast dedicated
Parallelism
• Heavy data flow hardware MAC
through CPU •Special Instruction
• Real time operations •On-chip memory and
cache
•Extended Parallelism-
SIMD, VLIW, Superscalar
Simplified Architecture of Standard Microprocessor
Van Newman Architecture
Independency between the operations
Limitations on the increase in speed
Hardware Architecture for Signal Processing
Multiple Bus Structure
•Separate data and program memory
Non-Pipelining Architecture
Pipeline Architecture
MAC Configuration
Special Instructions
Special Instruction: MAC
Repeat: RPT
Single Instruction Multiple Data (SIMD) Processing
Data bus-A
Data bus-B
ALU MAC Shifter ALU MAC Shifter
Execution Unit A Execution Unit B
SIMD Processing
16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 16 bi
16x16 16x16 16x16 16x16
MAC MAC MAC MAC
32- bit result 32- bit result 32- bit result 32- bit result
General purpose DSP architecture
DSP Processors
Fixed point processors • Floating point processors
• Represent each number with a minimum of • Represent each number with a minimum of 32 bits
16 bits • 232 = 4,294,967,296 possible bit patterns can represent
• 216 = 65536 possible bit patterns can a number
represent a number • ANSI/IEEE Std. 754-1985-- the largest and smallest
• Unsigned integer : 0 to 65,535 numbers are ±3.4×1038 and ± 1.2x10-38, respectively
• Signed integer : -32,768 to 32,767
Fixed point digital signal processors
First Generation Second Generation Third Generation Fourth Generation
• TMS320C54xx,D
• TMS320C1X by TI • TMS320C5X from SP563X and • TMS320C62XX
in 1982 TI, DSP5600X DSP16000 (VLIW Very Long
• Dedicated AU with from Motorola, • Aimed for instruction word )
multiplier and ADSP21XX from Digital • Included
accumulator Analog Devices, communication extensive
• Harvard DSP16XX from • Special parallelism while
architecture with Lucent instructions for maintaining the
separate program Technologies Adaptive features of earlier
and data memory • Enhanced filtering which versions
• On-chip memory features than first included echo • Wider
and special generation cancellations instructions,
instructions for • Larger on-chip and adaptive wider data paths
execution of basic memory and equalization more registers,
DSP algorithms more special and Viterbi larger instruction
instructions to decoding cache and
execute DSP • Low power and multiple AU
algorithms had power
• MAC with Repeat management
facility
Floating point DSP processors
First Generation Second Generation Third Generation
• TMS320C3X TI • TMS320C4X, • TMS320C67xx,
• Larger memory ADSP-2106x ADSP-TS001
and many on-chip SHARCH • VLIW
peripheral • Emphasis on
facilities multiprocessing
• Program cache and
and on-chip dual multiprocessor
access memories support
• Graphics and
Image processing
• Supported three
floating point
formats
Selecting Digital Signal Processor
• System engineers must select the device that provides
the most effective solution to meet the requirements of
their DSP application.
• Compare the raw processing power i.e. performance, of
the two processors.
• The mapping of DSP algorithms to DSP devices. This
may be complex, and requires an understanding of:
– I/O data paths,
– Memory management,
– Inter processor communication capability,
– Synchronization mechanisms
Special purpose DSP Hardware
There are two types of special-purpose hardware,
1. Hardware designed for efficient execution of specific DSP
algorithms such as digital filters, Fast Fourier Transform.
This type of special- purpose hardware is sometimes called
an algorithm-specific digital signal processor
2. Hardware designed for specific applications: for example
telecommunications, digital audio, or control applications.
This type of hardware is sometimes called an application-
specific digital signal processor.
Architecture of TMS320C67X
Features of C67X processors
• Execute up to eight 32-bit instructions per cycle.
• Consists of 32 general-purpose 32-bit registers
• VLIW (Very long instruction word)CPU
• Eight functional units contains:
– Two multipliers
– Six ALUs
• 8/16/32-bit data support, providing efficient memory
support for a variety of applications.
• Hardware support for single-precision (32-bit) and double-
precision (64-bit) IEEE floating-point operations.
• 32 × 32-bit integer multiply
• 32-KByte instruction cache
CPU of TMS320C67X
• The CPU contains:
– Program fetch unit
– Instruction dispatch unit
– Instruction decode unit
– Two data paths, each with four functional units
– 32 general purpose registers each of 32-bit
– Control registers
– Control logic
– Test, emulation, and interrupt logic
General purpose register files of
TMS320C67X
• There are two general-purpose register files (A and B)
– 16 32-bit registers (A0–A15 for file A and B0–B15 for file B)
– The general-purpose registers can be used for data, data address
pointers, or condition registers.
Functional units and operation of
TMS320C67X
• Eight functional units:
• data paths can be divided into two groups of
four
• All units ending in 1 (for example, .L1) write to
register file A, and all units ending in 2 write to
register file B.
• Each functional unit has two 32-bit read ports
for source operands src1 and src2.
Functional units and operation of TMS320C67X
Data Address Paths of TMS320C67
• The data address paths (DA1 and DA2) are each
connected to the .D units in both data paths.
– This allows data addresses generated by any one path to
access data to or from any register.
• The DA1 and DA2 resources and their associated
data paths are specified as T1 and T2, respectively.
– T1 consists of the DA1 address path and the LD1 and ST1
data paths.
– Similarly, T2 consists of the DA2 address path and the LD2
and ST2 data paths.
Control Register File
Control Registers (accessed by .S2 alone using MVC)
Register Name Abbre. Description
Addressing Mode Reg. AMR Specifies linear or circular addressing of A4-A7 &B4-B7
Control Status Reg. CSR Contains important control and status bits of the processor
Program Counter E1 PCE1 Contains the address of the fetch packet that is in the E1
Phase Reg. phase of the pipeline
Interrupt Flag Reg. IFR Contains the status of INT4-INT5 and NMI maskable
interrupts
Interrupt Set Reg. ISR Used to manually set maskable pending interrupts
Interrupt Clear Reg. ICR Used to manually clear maskable pending interrupts
Interrupt Enable Reg. IER Used to enable/disable the individual maskable interrupts
Interrupt Service Table ISTP Points to beginning of interrupt service table
Reg.
Interrupt Return IRP Contains the address to be used to return from a maskable
Pointer interrupt
Non-maskable NRP Contains the address to be used to return from a non-
Interrupt Return maskable interrupt
Pointer
Control Register File
• Addressing Mode Register (AMR)
– The addressing mode register (AMR) specifies the addressing
mode.
– For each of the eight registers (A4–A7, B4–B7) that can perform
linear or circular addressing.
– The mode select fields and block size fields are shown in Figure
Addressing mode Register
Addressing mode Register
Addressing mode Register
