Module No.: 1.

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WHY SILICON ,WHY NOT GERMANIUM?????????
The technology progressed during the early 1950s, using germanium as the
semiconductor material.
 Germanium proved unsuitable in certain applications because of its property to
exhibit high junction leakage currents. These currents result from germanium's
relatively narrow band gap (0.66 eV).
 For this reason, silicon (1.1 eV) became a practical substitute and has almost fully
supplanted germanium as a material for solid-state device fabrication.
 Silicon devices can operate up to 150°C versus 100°C for germanium.
 A stable thermal oxide can be grown on silicon with excellent interface electrical
properties. Other materials do not have such native oxide. Germanium oxide is
unsuited for device applications.
 The intrinsic (undoped) resistivity of germanium is about 47 ohm-cm, which
would have precluded the fabrication of rectifying devices with high break down
voltages.
 In contrast, the intrinsic resistivity of silicon is about 230,000 ohm-cm. Thus, high-
voltage rectifying devices and certain infrared sensing devices are practical with
silicon.
 Finally, there is an economic consideration; electronic grade germanium is now
more costly than silicon.
 Similar problems impeded the widespread use of compound semiconductors. For
example, it is difficult to grow a high-quality oxide on GaAs.
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  The first transistor s were built in ploycrystaline Ge
 All modern ICs use Single crystal material
 Polycrytaline or even amorphous materials can be used
but????
the defects present in these materials acts as generation and
recombination ceters
and have significant effects on basic device properties like
mobility and minority carrier lifetime
The result is
i) poor performance in device-lower o/p current for given
applied voltage
ii) higher leakage currents in junctions & poor reproducibility
from one device to another

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Crystals NaCl crystal
Courtesy: Minnesota University

• A material that exhibits perfect periodicity in atomic structure

Crystalline Polycrystalline amorphous

(mono crystalline) (multi crystalline)
• Crystal can be defined in terms of a symmetric array of points in space called
lattice

11/03/2013 Udayan Ganguly, IIT Bombay 4

CRYSTAL STRUCTURE
 In crystalline materials, the atoms are arranged
spatially in a periodic fashion
 Unit cell repeats in all three dimensions
 For CMOS process we chose silicon wafer with (100)
orientation
 Orientation dependent effects are associated with
wafer surfaces or material interfaces where crystal
terminates

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CRYSTAL UNIT CELL
 Si and other semiconductor have more complex unit
cells
 An xyz coordinate system defines the direction in the
crystal
 The dimension ‘a’ is called lattice constant and is the
basic distance over which the unit cell repeats in the
cubic crystal
 Directions in the crystals are expressed in terms of
three integers, which are the same as the components
of a vector in that direction
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Unit cell in simple cubic crystals

CUBIC BCC FCC

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 Crystallographic Planes

• It is also useful to describe planes in a crystal

• Figure illustrates three simple planes in a cubic crystal
• Such planes are described by Miller indices, which are a set of three integers

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  There are two principal silicon crystal orientations that are used in manufacturing
 integrated circuits, (111) and (100) (meaning that the crystal terminates at the wafer
 surface on {111} or {100} planes respectively). As mentioned earlier bulk properties of
 silicon are generally isotropic since the cubic crystal is symmetric Thus we find, for
 example, that dopant diffusion coefficients are independent of the direction in which the
 dopant is diffusing as long as surfaces play no role in the process (Chapter 7)
 Real devices are always built near surfaces
 Which crystal plane the surface terminates on can make a difference in the surface electrical and
physical properties

 {111} planes in silicon have the largest number of silicon atoms per cm2 and {100} planes have lowest
 {111} planes oxidies faster than {100} because oxidation rate is proportional to the number of silicon
atoms available for reaction
 {111} surfaces have higher densities of electrical defects(interface states) , some of these defects
because of dangling bond
 Si with (100) orientation is dominant today because of the superior electrical properties of the
Si/SiO2 interface
 Historically many bipolar technologies used (111) crystals because this orientation is somewhat easier
to grow by Czochralski method

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What is the Crystal Orientation in a
Silicon Wafer?
 The crystal orientation of a wafer is defined by the
plane of its top surface.
 (100) wafers are most common, but other orientations
are available.

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crystallographic defects (crystal defects)

 Crystalline solids exhibit a periodic crystal structure

 The positions of atoms or molecules occur on repeating
fixed distances, determined by the unit cell parameters
 However, the arrangement of atoms or molecules in most
crystalline materials is not perfect
 The regular patterns are interrupted by crystallographic
defects
 Real crystals contain large numbers of defects (typically
more than 104 per milligram), ranging from variable
amounts of impurities to missing or misplaced atoms or
ions.
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Crystal defects occur for three
main reasons:
1. It is impossible to obtain any substance in 100% pure form,Some
impurities are always present
2. Even if a substance were 100% pure, forming a perfect crystal
would require cooling the liquid phase infinitely slowly to allow all
atoms, ions, or molecules to find their proper positions
 Cooling at more realistic rates usually results in one or more
components being trapped in the “wrong” place in a lattice or in
areas where two lattices that grew separately intersect
3. Applying an external stress to a crystal, such as a hammer blow,
can cause microscopic regions of the lattice to move with respect to
the rest, thus resulting in imperfect alignment.

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 DEFECTS IN CRYSTALS
 Point defects

 Line defects

 Surface Imperfections

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CLASSIFICATION OF DEFECTS BASED ON DIMENSIONALITY

0D 1D 2D 3D
(Point defects) (Line defects) (Surface / Interface) (Volume defects)

Surface Twins
Vacancy Dislocation
Interphase Precipitate
Impurity Disclination
boundary
Faulted
Frenkel Dispiration Grain
region
defect boundary
Twin Voids /
Schottky
boundary Cracks
defect
Stacking Thermal
faults vibration
Anti-phase
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boundaries 15
 Vacancy
Non-ionic Interstitial
Impurity
crystals
Substitutional
0D
(Point defects) Frenkel defect
Ionic
crystals
Schottky defect

 Imperfect point-like regions in the crystal about the size of 1-2 atomic
diameters

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Point defects

 Point defects are defects that occur only at or around a

single lattice point
 They are not extended in space in any dimension
 Point defects are the simplest to visualize and they play
crucial roles in impurity diffusion, in ion implantation
damage, and lesser roles in oxidation kinetics
 In general, anything other than a silicon atom on a lattice
site constitutes a point defect

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Vacancy

 Missing atom from an atomic site

One of the most common types of point defect is a lattice site without
an atom. This defect is a vacancy.
 Atoms around the vacancy displaced
 Tensile stress field produced in the vicinity

Tensile Stress
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Fields ? 18
 Relative
size

Interstitial Compressive
Stress
Fields
Impurity

Substitutional
Tensile
Compressive stress Stress
fields Fields
 SUBSTITUTIONAL IMPURITY
 Foreign atom replacing the parent atom in the crystal
 E.g. Cu sitting in the lattice site of FCC-Ni
• The second type of point defect that may exist in a semiconductor is an extrinsic defect
• This is caused either by an impurity atom at an interstitial site or at a lattice site
• In the latter case, it is referred to as a substitution impurity
• The word "defect" should not necessarily carry with it a negative connotation
• For example, dopant atoms that are required to modulate semiconductor conductivity are
substitutional defects.
 INTERSTITIAL IMPURITY
 Foreign atom sitting in the void of a crystal
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 E.g. C sitting in the octahedral void in HT FCC-Fe
Point Defects
Schematic representation of different point
defects in a crystal. (1) vacancy; (2) selfinterstitial;
(3) interstitial impurity; (4), (5)
substitutional impurities. The arrows show
the local stresses introduced by the point
defects.
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 Schottky defect

• A Schottky defect is a type of point defect in a crystal lattice named after Walter H.
Schottky
• In non-ionic crystals it means a lattice vacancy defect
• In ionic crystals, the defect forms when oppositely charged ions leave their lattice
sites, creating vacancies
• These vacancies are formed in stoichiometric units, to maintain an overall neutral
charge in the ionic solid
• The vacancies are then free to move about as their own entities
• Normally these defects will lead to a decrease in the density of the crystal.

The defect-free NaCl structure

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Schottky defects within the NaCl structure22
 Observing dislocations

Dislocations appear as lines when observed under

transmission electron microscope (TEM)

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 ear of corn contains an extra row of
kernels between the other rows

1D
(Line defects)

Dislocation

Disclination

Dispiration

• Inserting an extra plane of atoms into a crystal lattice produces an edge dislocation.
• An edge dislocation in a crystal causes the planes of atoms in the lattice to deform
where the extra plane of atoms begins
• The edge dislocation frequently determines whether the entire solid will deform and fail
under stress
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• Edge dislocations are caused by the termination of a plane of atoms in the middle of a
crystal
• The adjacent planes are not straight, but instead bend around the edge of the
terminating plane so that the crystal structure is perfectly ordered on either side
• The analogy with a stack of paper is apt: if a half a piece of paper is inserted in
a stack of paper, the defect in the stack is only noticeable at the edge of the
half sheet
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Line defects extend in one dimension
In this defect, an extra line of atoms is inserted between two other lines of atoms
The simplest type of dislocation is an edge dislocation
An extra plane is terminated on one end by the edge of the crystal
If the extra plane is completely contained in the crystal, the defect is referred to as a
dislocation loop
The presence of a dislocation in the crystal is a sign of stress
The bonds just before the insertion of the extra plane are stretched, and bonds just after
the plane are compressed

The screw dislocation is more difficult to visualise, but basically comprises a

structure in which a helical path is traced around the linear defect (dislocation line)
by the atomic planes of atoms in the crystal lattice.

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 Movement of an edge dislocation
Dislocations move by two primary mechanisms, as illustrated in Figure 2.8: climb
and glide.
Glide is the movement of a dislocation line in a direction other than along the line.
It is the result of shear stress. In this situation, one of the planes of
lattice atoms breaks to form a continuous plane with the
previous extra plane leaving behind a new defect. This
process, called slip, can continue until the entire width
of the wafer has moved by one lattice site. Climb, on
the other hand, is simply the growth (or shrinkage) of a
dislocation line. Vacancies and/or interstitials are
created in response to stress. These point defects then
become part of the line defect.

(A) Climb (B) Glide

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 2D
(Surface / Interface)

Surface

Interphase
boundary

Grain
boundary
Twin
boundary
Stacking
faults

Anti-phase
boundaries

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Surface defects
Grain Boundaries
• Most crystalline solids are an aggregate of several crystals. Such materials are called
polycrystalline
• Each crystal is known as a grain. The boundary between the grains is the grain boundary
(the irregular lines in Fig.a)
• A grain boundary is a region of atomic disorder in the lattice only a few atomic diameter
wide
• The orientation of the crystals changes across the grain boundary as shown
schematically in Fig. b
• Grain boundaries act as obstacles to dislocation motion , Hence, presence of more grain
boundaries (finer grain size) will increase the strength Grain
boundaries
Grain 1

Grain 2

Grain 3

(b) Schematic of orientation change

(a) Optical micrograph of across the grain boundary
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polycrystalline material 29
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Polycrystalline Materials

Grain Boundaries
 regions between crystals
 transition from lattice of one
region to another
(a) The atoms near the boundaries of
the 3 grains do not have an
equilibrium spacing or
arrangement; slightly disordered.
(b) Grains and grain boundaries in a
stainless steel sample. low density
in grain boundaries

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• The most common kind of 2D or area defect found in silicon is the stacking fault.
• Stacking faults always form along {111} planes and are simply the insertion or removal of
an extra {111} plane
• In the silicon crystal structure shown in Figure , there are actually 3 parallel {111} planes
in each unit cell commonly referred to as A, B, and C

• In a perfect crystal, the stacking order is ABCABC, and so on

• When a stacking fault is present, either an extra plane is inserted (ABCACBC, etc.) or a
plane is missing (ABCABABC, etc.)
• Such faults are referred to as "extrinsic" if there is an extra plane of atoms, or
"intrinsic" if a plane is missing.
•

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Figure :
• An intrinsic stacking fault is the removal of part of a plane of atoms in the
{111} directions
• An extrinsic stacking fault is the addition of a partial plane of atoms in the
{111} directions
• The labels A, B, and C correspond to the three different (111) planes in the
diamond lattice

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 Volume Defects
• Volume defects in crystals can include agglomerations of point defects such as void
caused by a collection of vacancies, precipitates of dopants or impurities
• Crystalline precipitate" is used in this case because each of the precipitated atoms
occupies a lattice site

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Bulk or volume defects
• Porosity
• Inclusions
• Cracks
These defects form during manufacturing processes for various reasons and are
harmful to the material

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 Raw Materials and Purification

 Fortunately, silicon is a very abundant material, representing about 25.7% of the earth's
Crust
 Naturally occurring minerals containing silicon are very impure, so must be refined as
well as be converted into the crystalline form
 This is usually a multistage process, beginning with quartzite, a type of sand
 Chemically quartzite is SiO2
 MGS:
• The first step in the refining process is to convert the quartzite to Metallurgical
Grade Silicon or MGS
• This process usually takes place in a furnace in which a mixture of the quartzite and
a carbon source (usually coal or coke) is heated to temperatures approaching
2000°C
• A number of reactions take place in the furnace, the overall result of which is that
liquid silicon is drawn off and CO is given off as a gas
• The MGS that results about 98% pure, iron and aluminum being the two dominant
impurities

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2C{solid) + SiO2(solid) -» Si(liquid) + 2CO 38
Converting MGS to EGS:
MGS reacts with gaseous HCl :
• Fine powder of MGS reacted in presence of catalyst at elevated temperature
• This process can form any of a number of SiHCl compounds (SiH4-silane; SiH3Cl-
chlorosilane; SiH2Cl2-dichlorosilane; SiHCl3-trichlorosilane, or SiCl4-silicon
tetrachloride)
• The formation of SiHCl3 is most commonly used today
• SiHCl3 is a liquid at room temperature, so it can be purified by fractional distillation
• The SiHCl3 is extremely pure and is ready to be converted back to purified polysilicon
• This is accomplished in a large Chemical Vapor Deposition (CVD) reactor using the
following reaction:

2SiHCl3(gas) + 2H2{gas) -» 2Si{solid) + 6HCl{gas)

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• A thin silicon rod is used as the nucleation surface, on which the silicon deposits
• The rod is not a single-crystal, polysilicon is deposited
• Typically the rod is heated by passing an electric current through it
• The polysilicon, which is deposited, may be several meters long and several hundred
mm in diameter
• The overall deposition can take many days
• Finally, the resulting polysilicon is broken up into pieces to load into crucibles for
Czochralski crystal growth

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 Czochralski(CZ) Growth
History:
The process was first developed by Teal in the early 1950s although it was first developed
by Czochralski who used it to draw thin metal filaments from the melt as early as 1918.
distillation, it is not

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• Czochralski growth involves the solidification of a crystal from a melt
• The material used in single crystal silicon growth is electronic grade polycrystalline
silicon (polysilicon), which has been refined from quartzite (SiO2) until it is
99.999999999% pure
• The poly is loaded into a fused silica crucible(50cm in diameter) that is contained in
an evacuated chamber
• The chamber is back filled with an inert gas, and the crucible is heated to
approximately 1500°C(just above the melting point of silicon)
• A small chemically etched seed crystal (about 0.5 cm in diameter and 10 cm long) is
lowered into contact with the melt
• This crystal must be carefully oriented since it will serve as the template for the
growth of the much larger crystal, called the boule(ingot)
• Modern boules(ingots) of silicon can reach a diameter of over 300 mm and are 1 to 2 m
long.

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 Schematic of Czochralski growth system
A Czochralski crystal growth apparatus, also called a "puller,"

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The puller has four subsystems as follows

[Link]: Crucible, susceptor (crucible support), heating element ,power supply and
chamber
2. Crystal-pulling mechanism: seed shaft or chain, rotation mechanism, and seed
chuck
3. Ambient control: gas source, flow control, purge tube, and exhaust or vacuum
system
4. Control system: microprocessor, sensors, and outputs

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• A small single-crystal seed is then lowered into the melt
• The crystal orientation of this seed will determine the orientation of the resulting
pulled crystal and wafer
• The amount of dopant placed in the crucible with silicon charge will determine the
doping concentration in the resulting crystal
• The seed is then slowly pulled out of the melt
• Silicon atoms from the melt bond to the atoms in the seed, lattice plane by lattice plane,
forming a single crystal as the seed is pulled upwards
• The diameter of the resulting crystal is controlled primarily by the rate at which the
crystal is pulled
• During crystal growth, the seed and the crucible are normally rotated in opposite
directions to promote mixing in the liquid and more uniform growth
• Very few options are available in terms of crucible materials that are inert to molten
silicon, dominant choice today is quartz
• But still such crucibles are slowly dissolved by the silicon, resulting in both silicon and
oxygen being incorporated into the melt
• To avoid additional impurities from the ambient, the growth is normally performed in
an argon ambient

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 Bridgman Growth of GaAs

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 Float Zone Growth

• When extremely high purity silicon is required the growth technique of choice is float
zone refining
• The principal difference between this process and the CZ process is that no crucible is
used
• The basic feature of this growth technique is that the molten part of the sample is
supported entirely by the solid part
• This markedly reduces impurity levels in the resulting crystal, particularly oxygen, and
makes it easier to grow high-resistivity material
• Material grown from FZ is used primarily in applications which require high
resistivities, low oxygen content or both e.g. some types of detectors and power devices
• In CZ process, a rod of EGS poly-silicon is clamped at both ends, with the bottom in
contact with a single crystal seed
• A small RF coil provides a power, which generates large currents in the silicon and
locally melts it through I2R heating
• Usually the molten zone is about 2cm long
• The melting is initiated in a zone at the seed end and slowly moved up the rod, a single
crystal results
• Doping of the crystal can be accomplished either by starting with a doped poly-silicon
rod, a doped seed, or by maintaining a gas ambient during the FZ process
• Gas doping is accomplished through the use of gasses such as PH3, AsCl3, or BCl3
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 • The difficulty of the top seeded technique is that the
molten region must be able to support the weight of the
entire rod
• As a result, this technique is limited to boules of no more
than a few kilograms
• Figure shows an arrangement that can be used for the float
zone growth of large diameter crystals
• The crystal is bottom seeded
• After a sufficient length of dislocation free material has
been produced, a funnel filled with small spheres is slid
upward until it supports the weight of the boule

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 Wafer Preparation and Specifications

Wafer Preparation:
• After the boule has been grown the wafers must be made
• The boule is first characterized for resistivity and crystal perfection
• Then the seed and tail are cut off and the boule is mechanically trimmed to proper
diameter
• Wafer preparation involves series of mechanical steps: making perfectly flat,
polished to a mirror finish on the topside
• To shape and cut industrial diamonds are used, although other materials like SiC and
AI2O3 have been used and even materials like SiO2 are used as part of the polishing
operation
• Shaping of boule(Ingot):
 Trimming of oversized ingot to desired final diameter( this is done on lathe like m/c by
grinding operation )
 After grinding, etching is done to remove mechanical damage
• After boule is ground to desired diameter , one or more flats are made along its length
• Purpose of making flats:
 The first is as a reference plane for many types of automatic equipment that handle
wafers during manufacturing.
 The second purpose is to indicate the type and crystal orientation of the wafer
• The longest ("primary") flat is, by convention, oriented perpendicular to<110> direction
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Standard flat orientations for different semiconductor wafers

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• After grinding the flats, the wafer is dipped in a chemical etchant to remove the
damage caused by the mechanical grinding
• After etching, the boule is sliced into wafers
• This is a critical step in the process as it will determine the wafer bow and flatness
• Typically, a wire impregnated with diamond particles is used
• The wafers may then be edge rounded in another mechanical grinding process
• It has been found that edge rounded wafers are less susceptible to defects created by
mechanical handling during the subsequent processing
• The wafers are mechanically lapped in a slurry of alumina and glycerine, then etched
as before to reduce the damage
• Finally, one or both sides receive a polish in an electrochemical process involving a
slurry of NaOH and very fine silica particles followed by a chemical clean to remove
any residual contaminants

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