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Microprocessor Interface Guide

The 8086 and 8088 microprocessors are 16-bit processors introduced in the late 1970s. The 8086 has a 16-bit data bus while the 8088 has an 8-bit data bus due to address and data lines being multiplexed. Both chips contain around 29,000 transistors and have minimum and maximum memory and I/O interface modes. The document then describes the memory organization and bus cycles of the 8088 and 8086 in detail.

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Nutan Varshney
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92 views30 pages

Microprocessor Interface Guide

The 8086 and 8088 microprocessors are 16-bit processors introduced in the late 1970s. The 8086 has a 16-bit data bus while the 8088 has an 8-bit data bus due to address and data lines being multiplexed. Both chips contain around 29,000 transistors and have minimum and maximum memory and I/O interface modes. The document then describes the memory organization and bus cycles of the 8088 and 8086 in detail.

Uploaded by

Nutan Varshney
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Chapter 8

The 8088 and 8086 Microprocessors

Their Memory and Input/Output Interfaces


8086 and 8088 Microprocessors
• 8086 is a 16 bit microprocessor with a 16 bit data
bus (1978)
• 8088 is a 16 bit microprocessor with an 8 bit data
bus (1979)
• Both contain about 29,000 transistors, packaged in
40 pin dual-in-line package (DIP)
• Address lines A0-A7 and Data lines D0-D7 are
multiplexed in 8088 as AD0-AD7.
– By multiplexed we mean that the same physical pin
carries an address bit at one time and the data bit
another time
• Address lines A0-A15 and Data lines D0-D15 are
multiplexed in 8086 as AD0-AD15.
Minimum-mode and Maximum-mode Systems
8088 Minimum-Mode Signals
8088 Maximum-Mode Signals
Minimum Mode Interface – Status Signals
• Status signals: A16-A19 multiplexed with status signals S3-
S6 respectively
S3 and S4: a 2 bit binary code that identifies which of the
internal segment registers was used to generate the
physical address that was output on the address bus during
the current bus cycle.
S5 is the logic level of the internal interrupt enable flag
S6 is always logic 0.
Hardware Organization of the memory
Address Space

8088 8086
8088 byte transfer 8088 word transfer
Even-address byte transfer Odd address byte transfer

8086

Even-address word transfer


8086

Odd-address word transfer


Bus Cycle and Time States
T1 - start of bus cycle. Actions include setting control signals to give the
required values for ALE, DTR, IO/M putting a valid address onto the
address bus.

T2 - the RD or WR control signals are issued, DEN is asserted and in


the case of a write, data is put onto the data bus. The DEN turns
on the data bus buffers to connect the CPU to the external data
bus. The READY input to the CPU is sampled at the end of T2 and
if READY is low, a wait state TW (one or more) is inserted before
T3 begins.

T3 - this clock period is provided to allow memory to access the data. If


the bus cycle is a read cycle, the data bus is sampled at the end of T3.

T4 - all bus signals are deactivated in preparation for the next


clock cycle. The 8088 also finishes sampling the data (in a read
cycle) in this period. For the write cycle, the trailing edge of the
WR signal transfers data to the memory or I/O, which activates
and write when WR returns to logic 1 level.
Memory Read Cycle of the 8088
Write Bus Cycle 8088 M-M
Memory Interface Circuits
Address Bus Latches and Buffers
Address Latch Circuit
Data Bus Transceivers
Data bus Transceiver Circuit
Bank Write and Bank Read Control Logic

Bank Write Control Logic Bank Read Control Logic


Address Decoders

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