Introduction to CMOS
VLSI Design
Instructed by Shmuel Wimer
Bar-Ilan University, Engineering Faculty
Technion, EE Faculty
Credits: David Harris
Harvey Mudd College
(Some materials copied/taken/adapted from
Harris lecture notes)
Course Topics
Introduction to CMOS circuits
MOS transistor theory, processing technology
CMOS circuit and logic design
System design methods
CAD algorithms for backend design
Case studies, CAD tools, etc.
Oct 2010
CMOS VLSI Design
Bibliography
Textbook
Weste and Harris.
CMOS VLSI Design
(3rd edition)
Addison Wesley
ISBN: 0-321-14901-7
Available at
amazon.com.
Oct 2010
CMOS VLSI Design
Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Introduction: How to build your own simple CMOS
chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
Oct 2010
CMOS VLSI Design
A Brief History
1958: First integrated circuit
Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2003
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society
Oct 2010
CMOS VLSI Design
Annual Sales
1018 transistors manufactured in 2003
100 million for every human on the planet
Global Semiconductor Billings
(Billions of US$)
200
150
100
50
0
1982
1984
1986
1988
1990
1992
1994
1996
1998
2000
2002
Year
Oct 2010
CMOS VLSI Design
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large,
expensive, power-hungry, unreliable
1947: first point contact transistor
John Bardeen and Walter Brattain at Bell Labs
Read Crystal Fire
by Riordan, Hoddeson
Oct 2010
CMOS VLSI Design
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls
large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current
between source and drain
Low power allows very high integration
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CMOS VLSI Design
MOS Integrated Circuits
1970s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
Intel 1101 256-bit SRAM
Intel 4004 4-bit Proc
1980s-present: CMOS processes for low idle power
Oct 2010
CMOS VLSI Design
Moores Law
1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
1,000,000,000
Integration Levels
100,000,000
10,000,000
Transistors
Intel486
1,000,000
80286
100,000
Pentium 4
Pentium III
Pentium II
Pentium Pro
Pentium
1,000
8008
4004
1970
8080
LSI:
1975
1980
1985
10 gates
MSI: 1000 gates
Intel386
8086
10,000
SSI:
1990
1995
2000
10,000 gates
VLSI: > 10k gates
Year
Oct 2010
CMOS VLSI Design
10
Oct 2010
CMOS VLSI Design
11
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CMOS VLSI Design
12
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CMOS VLSI Design
13
Corollaries
Many other factors grow exponentially
Ex: clock frequency, processor performance
10,000
4004
1,000
8008
Clock Speed (MHz)
8080
8086
100
80286
Intel386
Intel486
10
Pentium
Pentium Pro/II/III
Pentium 4
1970
1975
1980
1985
1990
1995
2000
2005
Year
Oct 2010
CMOS VLSI Design
14
Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
Oct 2010
Si
Si
Si
Si
Si
Si
Si
Si
Si
CMOS VLSI Design
15
Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
Oct 2010
Si
Si
Si
Si
Si
Si
As
Si
Si
Si
Si
Si
Si
Si
+
-
CMOS VLSI Design
Si
Si
Si
16
p-n Junctions
A junction between p-type and n-type semiconductor
forms a diode.
Current flows only in one direction
Oct 2010
p-type
n-type
anode
cathode
CMOS VLSI Design
17
nMOS Transistor
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal oxide semiconductor (MOS)
Source
Gate
Drain
capacitor
Polysilicon
Even though gate is
SiO2
no longer made of metal
n+
n+
p
Oct 2010
CMOS VLSI Design
bulk Si
18
nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
n+
p
Oct 2010
n+
bulk Si
CMOS VLSI Design
19
nMOS Operation Cont.
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source
Gate
Drain
Polysilicon
SiO2
n+
p
Oct 2010
n+
bulk Si
CMOS VLSI Design
20
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
Oct 2010
bulk Si
CMOS VLSI Design
21
Power Supply Voltage
GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
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CMOS VLSI Design
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Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
d
nMOS
pMOS
g=1
d
OFF
ON
OFF
ON
s
Oct 2010
g=0
CMOS VLSI Design
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CMOS Inverter
A
VDD
0
1
A
A
Oct 2010
GND
CMOS VLSI Design
24
CMOS Inverter
A
VDD
0
1
OFF
A=1
Y=0
ON
A
Oct 2010
GND
CMOS VLSI Design
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CMOS Inverter
A
VDD
ON
A=0
Y=1
OFF
A
Oct 2010
GND
CMOS VLSI Design
26
CMOS NAND Gate
A
Oct 2010
Y
A
B
CMOS VLSI Design
27
CMOS NAND Gate
A
Oct 2010
ON
A=0
B=0
CMOS VLSI Design
ON
Y=1
OFF
OFF
28
CMOS NAND Gate
A
Oct 2010
OFF
A=0
B=1
CMOS VLSI Design
ON
Y=1
OFF
ON
29
CMOS NAND Gate
A
Oct 2010
ON
A=1
B=0
CMOS VLSI Design
OFF
Y=1
ON
OFF
30
CMOS NAND Gate
A
Oct 2010
OFF
A=1
B=1
CMOS VLSI Design
OFF
Y=0
ON
ON
31
CMOS NOR Gate
A
Oct 2010
A
B
Y
CMOS VLSI Design
32
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
A
B
C
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CMOS VLSI Design
33
Compound Gates
Compound gates can do any inverting function
Ex: Y AgB C gD (AND-AND-OR-INVERT, AOI22)
A
(a)
(b)
B C
(c)
(d)
A
B
C
D
(f)
(e)
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CMOS VLSI Design
34
Example: O3AI
Y A B C gD
A
B
C
D
Y
D
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CMOS VLSI Design
35
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process
Oct 2010
CMOS VLSI Design
36
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
A
GND
VDD
SiO2
n+ diffusion
n+
n+
p substrate
nMOS transistor
Oct 2010
p+
p+
n well
p+ diffusion
polysilicon
metal1
pMOS transistor
CMOS VLSI Design
37
Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection (used for Schottky Diode)
Use heavily doped well and substrate contacts / taps
A
GND
VDD
p+
n+
n+
p+
n+
n well
p substrate
substrate tap
Oct 2010
p+
well tap
CMOS VLSI Design
38
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND
VDD
nMOS transistor
pMOS transistor
well tap
substrate tap
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CMOS VLSI Design
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Oct 2010
CMOS VLSI Design
40
Detailed Mask Views
Six masks
n well
n-well
Polysilicon
Polysilicon
n+ diffusion
n+ Diffusion
p+ diffusion
p+ Diffusion
Contact
Contact
Metal
Oct 2010
Metal
CMOS VLSI Design
41
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
p substrate
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CMOS VLSI Design
42
Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
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CMOS VLSI Design
43
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
Photoresist
SiO2
p substrate
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CMOS VLSI Design
44
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
Oct 2010
CMOS VLSI Design
45
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
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CMOS VLSI Design
46
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranha etch
Necessary so resist doesnt melt in next step
SiO2
p substrate
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CMOS VLSI Design
47
n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well
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CMOS VLSI Design
48
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
n well
p substrate
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CMOS VLSI Design
49
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Polysilicon
Thin gate oxide
p substrate
Oct 2010
n well
CMOS VLSI Design
50
Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
Polysilicon
Thin gate oxide
p substrate
Oct 2010
n well
CMOS VLSI Design
51
N-diffusion
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact
p substrate
Oct 2010
n well
CMOS VLSI Design
52
N-diffusion (cont.)
Pattern oxide and form n+ regions
n+ Diffusion
n well
p substrate
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CMOS VLSI Design
53
N-diffusion (cont.)
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n+
n+
p substrate
Oct 2010
n+
n well
CMOS VLSI Design
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N-diffusion (cont.)
Strip off oxide to complete patterning step
n+
n+
p substrate
Oct 2010
n+
n well
CMOS VLSI Design
55
P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+
p substrate
Oct 2010
p+
p+
n+
n well
CMOS VLSI Design
56
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+
n+
n+
p+
p+
n+
n well
p substrate
Oct 2010
CMOS VLSI Design
57
Metalization
Sputter on copper / aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Metal
Oct 2010
CMOS VLSI Design
58
Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size scales ~X0.7 every 2 years both lateral
and vertical
Moores law
Normalize feature size when describing design rules
Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process
Todays = 0.01 m (10 nanometer = 10-8 meter)
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CMOS VLSI Design
59
Simplified Design Rules
Conservative rules to get you started
Oct 2010
CMOS VLSI Design
60
Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4 / 2sometimes called 1 unit
In f = 0.01 m process, this is 0.04 m wide, 0.02
m long
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CMOS VLSI Design
61
Summary
MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start
designing schematics and layout for a simple circuit!
Oct 2010
CMOS VLSI Design
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