Instruction set of
8086 Microprocessor
Software
The sequence of commands used to tell a
microcomputer what to do is called a program,
Each command in a program is called an instruction
ADD AX, BX
(Opcode)
(Destination operand)
(Source operand )
Instructions
LABEL: INSTRUCTION
Address identifier
machine code
Ex.
START: MOV AX, BX
into AX
; COMMENT
Does not generate any
; copy BX
Two key benefits of assembly
language programming
It takes up less memory
It executes much faster
An instruction can be coded with 1 to 6 bytes
Byte 1 contains three kinds of information
Opcode field (6 bits) specifies the operation (add,
subtract, move)
Register Direction Bit (D bit) Tells the register operand
in REG field in byte 2 is source or destination operand
1: destination
0: source
- Data Size Bit (W bit) Specifies whether the operation
will be performed on 8-bit or 16-bit data
0: 8 bits
1: 16 bits
Byte 2 has three fields
Mode field (MOD)
Register field (REG) used to identify the register for the first
operand
Register/memory field (R/M field)
Data Transfer Instructions - MOV
Mnemonic
Meaning
Format
Operation
Flags affected
MOV
Move
Mov D,S
(S) (D)
None
Destination
Source
Memory
Accumulator
Accumulator
Memory
Register
Register
Register
Memory
Memory
Register
Register
Immediate
Memory
Immediate
Seg reg
Reg 16
Seg reg
Mem 16
Reg 16
Seg reg
Memory
Seg reg
NO MOV
Memory
Immediate
Segment Register
EX:
Memory
Segment Register
Segment Register
MOV AL, BL
Data Transfer Instructions - XCHG
Mnemonic
Meaning
Format
XCHG
Exchange
XCHG D,S
Destination
(S)
(D)
Flags affected
None
Source
Accumulator Reg 16
Memory
Register
Register
Register
Register
Memory
Operation
Example: XCHG [1234h], BX
NO XCHG
MEMs
SEG REGs
Data Transfer Instructions LEA, LDS,
Mnemo Meaning
Format
Operation
Flags
LES
nic
affected
LEA
Load
Effective
Address
LEA Reg16,EA
LDS
Load
Register
And DS
LDS Reg16,MEM32
Load
Register
and ES
LES Reg16,MEM32
LES
EA
(Reg16)
(MEM32) (Reg16)
None
None
(Mem32+2) (DS)
(MEM32) (Reg16)
(Mem32+2) (ES)
LEA SI DATA (or) MOV SI Offset DATA
None
The XLAT Instruction
10
Mnemonic
Meaning
Format
XLAT
Translate
XLAT
Operation
((AL)+(BX)+(DS)0)
Flags
(AL)
None
Arithmetic Instructions: ADD, ADC, INC, AAA, DAA
Mnemonic
Meaning
Format
Operation
Flags
affected
ADD
Addition
ADD D,S
(S)+(D) (D)
carry
(CF)
ALL
ADC
Add with
carry
ADC D,S
INC
Increment by
one
INC D
AAA
ASCII adjust
for addition
AAA
DAA
Decimal
adjust for
addition
DAA
11
(S)+(D)+(CF)
carry
(D)+1
(D)
(CF)
ALL
(D)
ALL but CY
If the sum is >9, AH
is incremented by 1
Adjust AL for decimal
Packed BCD
AF,CF
ALL
Examples:
Ex.1
Ex.2
ADD AX,2
ADC AX,2
INC BX
INC WORD PTR [BX]
Ex.3 ASCII CODE 0-9 = 30-39h
MOV AX,38H
; (ASCII code for number 8)
ADD AL,39H
; (ASCII code for number 9)
AL=71h
AAA
; used for addition
AH=01,
AL=07
Ex.4
AL contains 25 (packed BCD)
AX,3030H
; answer
0107
BLADD
contains
56 (packed BCD)
25 to ASCII
AX=3137
+ 56
ADD AL, BL
DAA
12
-------7B 81
Arithmetic Instructions SUB, SBB, DEC, AAS, DAS, NEG
Mnemonic
Meaning
Format
SUB
Subtract
SUB D,S
SBB
Subtract
with
borrow
SBB D,S
DEC
Decrement
by one
DEC D
NEG
Negate
NEG D
DAS
Decimal
adjust for
subtraction
DAS
Convert the result in AL to
packed decimal format
All
AAS
ASCII
adjust for
subtraction
AAS
(AL) difference
(AH) dec by 1 if borrow
CY,AC
13
Operation
(D) - (S)
Borrow
Flags
affected
(D)
(CF)
(D) - (S) - (CF)
(D) - 1
(D)
(D)
All
All
All but CF
All
Multiplication and Division
14
Multiplication and Division
15
Multiplication and Division
16
Multiplication
(MUL or IMUL)
Multiplicand
Operand
(Multiplier)
Result
Byte*Byte
AL
Register or memory
AX
Word*Word
AX
Register or memory
DX :AX
Dword*Dword
EAX
Register or memory
EAX :EDX
Division
(DIV or IDIV)
Dividend
Operand
(Divisor)
Quotient: Remainder
Word/Byte
AX
Register or Memory
AL : AH
Dword/Word
DX:AX
Register or Memory
AX : DX
Qword/Dword
EDX: EAX
Register or Memory
EAX : EDX
Multiplication and Division
Examples
Ex1:
Assume that each instruction starts from these values:
AL = 85H, BL = 35H, AH = 0H
1. MUL BL AL . BL = 85H * 35H = 1B89H AX = 1B89H
2. IMUL BL AL . BL = 2S AL * BL = 2S (85H) * 35H
= 7BH * 35H = 1977H 2s comp E689H AX.
AH
0085 H
AX
= 35 H = 02 (85-02*35=1B) 1B
BL
AH AL
AX 0085 H
1B 02
4. IDIV BL BL = 35 H =
DIV BL
17
AL
02
Ex2:
AL = F3H, BL = 91H, AH = 00H
1. MUL BL AL * BL = F3H * 91H = 89A3H AX = 89A3H
2. IMUL BL AL * BL = 2S AL * 2S BL = 2S (F3H) * 2S(91H) =
0DH * 6FH = 05A3H AX.
00 F 3H
00 F 3H
AX
3.IDIV BL
=
=
= 2 (00F3 2*6F=15H)
2
'
S
(
91
H
)
6
FH
BL
AH
AL
15
R
02
Q
AH
POS
NEG 2s(02) = FEH 15
NEG
00 F 3H
AX
4. DIV BL
=
= 01(F3-1*91=62)
91
H
BL
18
AL
FE
AH
62
AL
01
Ex3:
AX= F000H, BX= 9015H, DX= 0000H
1. MUL BX = F000H * 9015H =
DX
8713
AX
B000
2. IMUL BX = 2S(F000H) * 2S(9015H) = 1000 * 6FEB =
DX
AX
06FE
B000
F 000 H
3. DIV BL =
= B6DH More than FFH Divide Error.
15 H
2' S ( F 000 H ) 1000 H
4. IDIV BL
=
= C3H > 7F Divide Error.
15 H
15 H
19
Ex4:
AX= 1250H, BL= 90H
AX 1250 H
POS
POS
1250 H
1250 H
1. IDIV BL
=
=
=
=
=
BL
NEG 2' sNEG 2' s (90 H )
70 H
90 H
= 29H (Q) (1250 29 * 70) = 60H (REM)
29H ( POS) 2S (29H) = D7H
R
60H
Q
D7H
1250 H
AX
2. DIV BL
=
= 20H1250-20*90 =50H
90
H
BL
20
R
50H
AH
Q
20H
AL
Logical Instructions
Mnemonic
Meaning
Format
Operation
Flags Affected
AND
Logical AND
AND D,S
(S) (D) (D)
OR
Logical Inclusive
OR
OR D,S
(S)+(D) (D)
XOR
Logical Exclusive
OR
XOR D,S
OF, SF, ZF, PF,
CF
AF undefined
OF, SF, ZF, PF,
CF
AF undefined
OF, SF, ZF, PF,
CF
AF undefined
None
NOT
21
LOGICAL NOT
Destination
Source
Register
Register
Memory
Register
Memory
Accumulator
Register
Memory
Register
Immediate
Immediate
Immediate
NOT D
Destination
Register
Memory
(S) +
(D)(D)
_
(D) (D)
Shift and Rotate
Instructions
SHL/SAL: shift logical left/shift
arithmetic
left
SHR: shift logical right
SAR: shift arithmetic right
ROL: rotate left
ROR: rotate right
RCL: rotate left through carry
RCR: rotate right through carry
22
Logical vs Arithmetic
Shifts
A logical shift fills the newly created bit position with zero:
An arithmetic shift fills the newly created bit
position with a copy of the numbers sign bit:
23
Shift Instructions
Mnemo
-nic
SAL/SH
L
SHR
SAR
24
Meaning
Format
Shift
SAL/SHL D, Count
arithmetic
Left/shift
Logical left
Shift
logical
right
Shift
arithmetic
right
SHR D, Count
SAR D, Count
Operation
Flags
Affected
Shift the (D) left by the
number of bit positions
equal to count and fill the
vacated bits positions on
the right with zeros
CF,PF,SF,ZF
AF undefined
OF undefined
if count 1
Shift the (D) right by the
number of bit positions
equal to count and fill the
vacated bits positions on
the left with zeros
CF,PF,SF,ZF
AF undefined
OF undefined
if count 1
Shift the (D) right by the
number of bit positions
equal to count and fill the
vacated bits positions on
the left with the original
most significant bit
CF,PF,SF,ZF
AF undefined
OF undefined
if count 1
25
SHL Instruction
The SHL (shift left) instruction performs a logical left shift
on the destination operand, filling the lowest bit with 0.
26
Operand types:
SHL reg,imm8
SHL mem,imm8
SHL reg,CL
SHL mem,CL
SHR Instruction
The SHR (shift right) instruction performs a
logical right shift on the destination operand.
The highest bit position is filled with a zero.
27
SAR Instruction
SAR (shift arithmetic right) performs a right
arithmetic shift on the destination operand.
28
Rotate Instructions
Mnem
-onic
Meaning
ROL
Rotate
Left
ROL D,Count
ROR
Rotate
Right
ROR D,Count Rotate the (D) right by the
number of bit positions equal
to Count. Each bit shifted out
from the rightmost bit goes
back into the leftmost bit
position.
CF
OF undefined
if count 1
RCL
Rotate
Left
through
Carry
RCL D,Count
Same as ROL except carry is
attached to (D) for rotation.
CF
OF undefined
if count 1
RCR
Rotate
right
through
Carry
RCR D,Count Same as ROR except carry is
attached to (D) for rotation.
CF
OF undefined
if count 1
29
Format
Operation
Flags Affected
Rotate the (D) left by the
CF
number of bit positions equal
OF undefined
to Count. Each bit shifted out
if count 1
from the left most bit goes back
into the rightmost bit position.
ROL Instruction
ROL (rotate) shifts each bit to the left
The highest bit is copied into both the
Carry flag and into the lowest bit
No bits are lost
30
MOV Al,11110000b
ROL Al,1
; AL = 11100001b
MOV Dl,3Fh
ROL Dl,4
; DL = F3h
ROR Instruction
ROR (rotate right) shifts each bit to the right
The lowest bit is copied into both the Carry
flag and into the highest bit
No bits are lost
31
RCL Instruction
RCL (rotate carry left) shifts each bit to the left
Copies the Carry flag to the least significant bit
Copies the most significant bit to the Carry flag
CF
32
RCR Instruction
RCR (rotate carry right) shifts each bit to the right
Copies the Carry flag to the most significant bit
Copies the least significant bit to the Carry flag
33
Flag control instructions
MNEMONIC
MEANING
OPERATION
Flags
Affected
CLC
Clear Carry Flag (CF) 0
CF
STC
Set Carry Flag
(CF) 1
CF
CMC
Complement
Carry Flag
(CF) (CF)l
CF
CLD
Clear Direction
Flag
(DF) 0
SI & DI will be auto incremented while
string instructions are executed.
DF
Set Direction
Flag
(DF) 1
SI & DI will be auto decremented
while string instructions are executed.
DF
CLI
Clear Interrupt
Flag
(IF) 0
IF
STI
Set Interrupt
Flag
(IF) 1
IF
STD
34
Compare Instruction,
Mnemo
Operation
CMPMeaning Format
nic
CMP
Compare
CMP D,S
Flags
Affected
(D) (S) is used in CF, AF, OF,
setting or resetting the PF, SF, ZF
flags
Allowed Operands
(D) = (S)
; ZF=0
(D) > (S)
; ZF=0, CF=0
(D) < (S)
; ZF=0, CF=1
Destination
Source
RegisterRegister
RegisterMemory
Memory
Register
RegisterImmediate
35
Memory
Immediate
Accumulator
Immediate
String?
An array of bytes or words
located in memory
Supported String Operations
Copy (move, load)
Search (scan)
Store
Compare
36
String Instruction
Basics
Source DS:SI, Destination ES:DI
You must ensure DS and ES are correct
You must ensure SI and DI are offsets into
DS and ES respectively
Direction Flag (0 = Up, 1 = Down)
CLD - Increment addresses (left to right)
STD - Decrement addresses (right to left)
37
String Instructions
Instruction prefixes
Prefix
REP
Used with
Meaning
MOVS
STOS
Repeat while not end of string
CX 0
REPE/REPZ
CMPS
SCAS
Repeat while not end of string
and strings are equal. CX 0
and ZF = 1
REPNE/REP
NZ
CMPS
SCAS
Repeat while not end of string
and strings are not equal. CX
0 and ZF = 0
38
Instructions
MnemoNic
meaning
format
Operation
Flags
effect
-ed
MOVS
Move string
DS:SI
ES:DI
MOVSB/ ((ES)+(DI)) ((DS)+(SI))
MOVSW (SI) (SI) 1 or 2
(DI) (DI) 1 or 2
none
CMPS
Compare
string
DS:SI
ES:DI
CMPSB/ Set flags as per
CMPSW ((DS)+(SI)) - ((ES)+(DI))
(SI) (SI) 1 or 2
(DI) (DI) 1 or 2
All
status
flags
39
MnemoNic
meaning
format
SCAS
Scan string
AX ES:DI
SCASB/
SCASW
LODS
Load string LODSB/
DS:SI AX LODSW
(AL or AX) ((DS)+(SI))
(SI) (SI) 1 or 2
STOS
Store string STOSB/
ES:DI AX STOSW
((ES)+(DI)) (AL or A) 1 or 2
(DI) (DI) 1 or 2
40
Operation
Set flags as per
(AL or AX) - ((ES)+(DI))
(DI) (DI) 1 or 2
Branch group of instructions
Branch instructions provide lot of convenience to the
programmer to perform operations selectively, repetitively
etc.
Branch group of instructions
Conditional
jumps
41
Unconditional
jump
Iteration
instructions
CALL
instructions
Return
instructions
SUBROUTINE & SUBROUTINE HANDILING
INSTRUCTIONS
Main program
Subroutine A
First Instruction
Call subroutine A
Next instruction
Call subroutine A
Next instruction
42
Return
A subroutine is a special segment of program that can be called
for execution from any point in a program.
An assembly language subroutine is also referred to as a
procedure.
Whenever we need the subroutine, a single instruction is
inserted in to the main body of the program to call subroutine.
To branch a subroutine the value in the IP or CS and IP must be
modified.
After execution, we want to return the control to the instruction
that immediately follows the one called the subroutine i.e., the
original value of IP or CS and IP must be preserved.
Execution of the instruction causes the contents of IP to be saved
on the stack.
A new 16-bit (near-proc, mem16, reg16 i.e., Intra Segment) value
which is specified by the instructions operand is loaded into IP.
Examples: CALL 1234H
CALL BX
CALL [BX]
43
Inter Segment
At starting CS and IP placed in a stack.
New values are loaded in to CS and IP given
by the operand.
After execution original CS, IP values placed
as it is.
Far-proc
Memptr32
These two words (32 bits) are loaded directly into IP and
CS with execution at CALL instruction.
First 16 IP
Next 16 CS
44
Mnem- Meaning
onic
CALL
Format
Flags
Affected
Subroutine CALL operand Execution continues from none
call
the
address
of
the
subroutine specified by
the operand. Information
required to return back to
the main program such as
IP and CS are saved on
the stack.
Operand
Near-proc
Far proc
Memptr 16
Regptr 16
45
Operation
Memptr 32
RETURN
Every subroutine must end by executing an instruction that returns
control to the main program. This is the return (RET) instruction.
By execution the value of IP or IP and CS that were saved in the
stack to be returned back to their corresponding regs.
Mnem Meaning
-onic
Format
RET
RET or
Return
RET operand program
(and CS
operands
added to
SP.
Return
Operand
46
None
Disp16
Operation
Flags
Affected
to
the
main None
by restoring IP
for far-proc). If
is present, it is
the contents of
Loop Instructions
These instructions are used to repeat a set of instructions
several times.
Format:
LOOP Short-Label
Operation: (CX) (CX)-1
Jump is initialized to location defined by short label if CX0.
otherwise, execute next sequential instruction.
Instruction LOOP works w.r.t contents of CX. CX must be
preloaded with a count that represents the number of times
the loop is to be repeat.
Whenever the loop is executed, contents at CX are first
decremented then checked to determine if they are equal to
zero.
If CX=0, loop is complete and the instruction following loop is
executed.
If CX 0, content return to the instruction at the label
specified in the loop instruction.
47
LOOP Instruction contd.
General format : LOOP r8
; r8 is 8-bit signed value.
It is a 2 byte instruction.
Used for backward jump only.
Maximum distance for backward jump is only 128 bytes.
LOOP AGAIN is almost same as:
DEC CX
JNZ AGAIN
LOOP instruction does not affect any flags.
48
Mnemonic meaning
format
Operation
LOOP
Loop
Loop short-label
(CX) (CX) 1
Jump to location given by
short-label if CX 0
LOOPE/
LOOPZ
Loop while
equal/ loop
while zero
LOOPE/LOOPZ
short-label
(CX) (CX) 1
Jump to location given by
short-label if CX 0 and
ZF=1
LOOPNE/LOOPNZ
short-label
(CX) (CX) 1
Jump to location given by
short-label if CX 0 and
ZF=0
LOOPNE/ Loop while
LOOPNZ not equal/
loop while
not zero
49
Control flow and JUMP instructions
Unconditional Jump
Part 1
JMP AA
Part 2
Unconditional JMP
Skipped part
Part 3
AA
XXXX
JMP unconditional jump
JMP Operand
50
Next instruction
Unconditional Jump
Unconditional Jump Instruction
Near Jump or
Far Jump or
Intra segment Jump
Inter segment Jump
(Jump within the segment) (Jump to a different segment)
Is limited to the address with in
the current segment. It is achieved
by modifying value in IP
Permits jumps from one code
segment to another. It is
achieved by modifying CS and IP
Operands
Short label
Near label
Far label
Inter Segment Jump
Memptr16
51
Regptr16
memptr32
Inter Segment Jump
Conditional Jump
Part 1
Jc AA
Conditional Jump
Part 2
NO
XXXX
condition
Skipped part
YES
Part 3
AA
52
XXXX
Next instruction
Conditional Jump instructions
Conditional Jump instructions in 8086 are just 2 bytes long. 1-byte
opcode followed by 1-byte signed displacement (range of 128 to
+127).
Conditional Jump Instructions
Jumps based on
a single flag
53
Jumps based on
more than one flag
Conditional Jump Instructions
Mnemonic :
Jc
Meaning :
Conditional Jump
Format :
Jc operand
Operation :
If condition is true jump to the address specified by operand.
Otherwise the next instruction is executed.
Flags affected : None
54
TYPES
Mnemonic
meaning
condition
JA
Above
CF=0 and ZF=0
JB
Above or Equal
CF=0
JB
Below
CF=1
JBE
Below or Equal
CF=1 or ZF=1
JC
Carry
CF=1
JCXZ
CX register is Zero
(CF or ZF)=0
JE
Equal
ZF=1
JG
Greater
ZF=0 and SF=OF
JGE
Greater or Equal
SF=OF
JL
Less
(SF XOR OF) = 1
55
Mnemonic
56
meaning
condition
JLE
Less or Equal
((SF XOR OF) or ZF) = 1
JNA
Not Above
CF =1 or Zf=1
JNAE
Not Above nor Equal
CF = 1
JNB
Not Below
CF = 0
JNBE
Not Below nor Equal
CF = 0 and ZF = 0
JNC
Not Carry
CF = 0
JNE
Not Equal
ZF = 0
JNG
Not Greater
((SF XOR OF) or ZF)=1
JNGE
Not Greater nor
Equal
(SF XOR OF) = 1
JNL
Not Less
SF = OF
Mnemonic
meaning
condition
JNLE
Not Less nor Equal
ZF = 0 and SF = OF
JNO
Not Overflow
OF = 0
JNP
Not Parity
PF = 0
JNZ
Not Zero
ZF = 0
JNS
Not Sign
SF = 0
JO
Overflow
OF = 1
JP
Parity
PF = 1
JPE
Parity Even
PF = 1
JPO
Parity Odd
PF = 0
JS
Sign
SF = 1
JZ
Zero
ZF = 1
57
Jumps Based on a single flag
JZ
r8 ;Jump if zero flag set to 1 (Jump if result is zero)
JNZ
r8 ;Jump if Not Zero (Z flag = 0 i.e. result is nonzero)
JS
r8 ;Jump if Sign flag set to 1 (result is negative)
JNS
r8 ;Jump if Not Sign (result is positive)
JC
r8 ;Jump if Carry flag set to 1
JNC
r8 ;Jump if No Carry
JP
r8 ;Jump if Parity flag set to 1 (Parity is even)
JNP
r8 ;Jump if No Parity (Parity is odd)
JO
r8 ;Jump if Overflow flag set to 1 (result is wrong)
JNO
r8 ;Jump if No Overflow (result is correct)
58
There is no jump
based on AC flag
JZ r8 ; JE (Jump if Equal) also means same.
JNZ r8 ; JNE (Jump if Not Equal) also means same.
JC r8 ;JB (Jump if below) and JNAE (Jump if Not
Above or Equal) also mean same.
JNC r8 ;JAE (Jump if Above or Equal) and JNB (Jump if
Not Above) also mean same.
JZ, JNZ, JC and JNC used after arithmetic operation
JE, JNE, JB, JNAE, JAE and JNB are used after a
compare operation.
JP r8 ; JPE (Jump if Parity Even) also means same.
JNP r8 ; JPO (Jump if Parity Odd) also means same.
59
Examples for JE or JZ instruction
Ex. for forward jump (Only examples for JE given)
CMP SI, DI
JE SAME
Should be
<=127
bytes
ADD CX, DX
:
;Executed if Z = 0
(if SI not equal to DI)
:
SAME: SUB BX, AX
;Executed if Z = 1
(if SI = DI)
60
Examples for JE or JZ instruction
Ex. for backward jump
BACK: SUB BX, AX
Should be
<= 128
bytes
; executed if Z = 1
(if SI = DI)
:
CMP SI, DI
JE BACK
ADD CX, DX
;executed if Z = 0
(if SI not equal to DI)
61
Machine control
instructions
HLT instruction HALT processing
the HLT instruction will cause the 8086 to stop fetching and
executing instructions. The 8086 will enter a halt state.
NOP instruction
this instruction simply takes up three clock cycles and does no
processing. After this, it will execute the next instruction. This
instruction is normally used to provide delays in between instructions.
ESC instruction
whenever this instruction executes, the microprocessor does
NOP or access a data from memory for coprocessor. This instruction
passes the information to 8087 math processor. Six bits of ESC
instruction provide the opcode to coprocessor.
62
Machine control instructions
contd
LOCK instruction
this is a prefix to an instruction. This prefix makes sure that during
execution of the instruction, control of system bus is not taken by
other microprocessor.
in multiprocessor systems, individual microprocessors are
connected together by a system bus. This is to share the common
resources. Each processor will take control of this bus only when it
needs to use common resource.
the lock prefix will ensure that in the middle of an instruction,
system bus is not taken by other processors. This is achieved by
hardware signal LOCK available on one of the CPU pin. This signal
will be made active during this instruction and it is used by the bus
control logic to prevent others from taking the bus.
once this instruction is completed, lock signal becomes inactive and
microprocessors can take the system bus.
WAIT instruction
this instruction takes 8086 to an idle condition. The CPU will not do
any processing during this. It will continue to be in idle state until
TEST pin of 8086 becomes low or an interrupt signal is received on
INTR or NMI. On valid interrupt, ISR is executed and processor
enters the idle state again.
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