Part Four – Protection

Fundamentals and Basic Design

Principle

Wei-Jen Lee, Ph.D., PE

Professor of Electrical Engineering Dept.
The Univ. of Texas at Arlington
Introduction
• The best protection technique now and for more
than 50 years is that known as differential
protection.
• Differential protection is universally applicable to
all parts of the power system.
• Other protections, such as overcurrent, over/under
frequency, and over/under voltage protections, are
also use among utility industry.
The Differential Principle
• For normal operation and
all external faults, the Iop of
the relay is very small.
• During external faults, the
transient of the CTs can
produce rather large
currents. Therefore, it is
difficult and impractical to
apply an instantaneous
relay. Time delay relay can
be used with care.
The Differential Principle
• For internal faults, the differential relay operating
current is the sum of the input currents feeding the
faults.
The Differential Principle
• To provide high sensitivity to light internal faults
with high security for external faults, most the
relays are of the percentage differential type. The
secondary of the CT is connected to restraint coil.
The Differential Principle
• For the circuit with 50% characteristics, an
external or through current of 10A would require a
difference or operating current of 5 A or more for
the relay to operate.
The Differential Principle
• The through current characteristics apply only for
external fault.
• Differential relays are very sensitive to the internal
faults.
• Typical pick-up currents for differential relays are
on the order of 0.14 – 3.0 A
Overcurrent and Distance
Protection
• Where differential is not utilized, overcurrent and
distance relays are the major protection schemes.
• The minimum operating criteria for overcurrent
relays is shown below:
Overcurrent and Distance
Protection
• Relay coordination
Basic Design Principles
• Electromechanical
• Solid State
• Hybrid
• Numerical (Microprocessor)
Basic Design Principles
• Time-Overcurrent Relays
Basic Design Principles
• Time-Overcurrent Relays
• Definite minimum time (CO-6)
• Inverse (CO7 or CO-8)
• Very inverse (CO-9)
• Extremely inverse (CO-11)
• Tap setting and time dial
setting
Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
System diagram
Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
• Arrangement of breaker, CT, and relay
Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
• Arrangement of breaker, CT, and relay
BREAKER BREAKER OPERATING CT RELAY
TIME RATIO TYPE
B1 5 Cycles 400:5 CO-8

B2 5 Cycles 200:5 CO-8

B3 5 Cycles 200:5 CO-8

Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
• System loading and fault current
Bus Load (MVA) PF (Lagging)
1 11.0 0.95
2 4.0 0.95
3 6.0 0.95
Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
• I-T curve of Co-8 relay
Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
• System loading and fault current
Bus Max. fault current Min. fault current
1 3000 2200
2 2000 1500
3 1000 700
Basic Design Principles
• Example: Time-overcurrent relays for radial system
protection
• Calculation and coordination
• Select Tap setting that the relay will not operate for maximum
load current.
• For CT at B3, the maximum CT current for maximum load L3
is:
6 *10 6
I load = 3
= 100.4 A
3 * 34.5 * 10
100.4
I CT = = 2.51A
(200 / 5)
• For this example, 3-A TS was selected for B3 relay.
Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
• Calculation and coordination
• For CT at B2, the maximum CT secondary current for
maximum load is:
(6 + 4) * 10 6
I load = 3
= 167.35 A
3 * 34.5 * 10
167.35
I CT = = 4.18 A
(200 / 5)
• For this example, 5-A TS was selected for B2 relay.
Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
• Calculation and coordination
• For CT at B1, the maximum CT secondary current for
maximum load is:
(6 + 4 + 11) * 10 6
I load = 3
= 351.43 A
3 * 34.5 * 10
351.43
I CT = = 4.39 A
(400 / 5)
• For this example, 5-A TS was selected for B1 relay.
Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
• Calculation and coordination
• The largest fault current through B3 is 2000A. (Fault at right
of B3)
• Ignore CT saturation, the fault-to-pickup current ratio at B3 is
2000/(40*3)=16.67
• Since the speed of operation is the main concern, 0.5 Time-
Dial setting (TDS) is selected.
• Under this fault current, the operating time of B3 is 0.05
second
Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
• Calculation and coordination
• Adding the breaker operating time (0.083 second), primary
protection needs 0.113 second (0.05 + 0.083) to clear this
fault.
• For the same fault, the fault-to-pickup current ratio at B2 is
10.0. (2000/40*5)
• Adding the B3 relay operating time, breaker operating time,
and 0.3 second coordination time interval, the B2 relay’s
operating time should be 0.43 seconds.
• Select TDS=2 for the B2 relay.
Basic Design Principles
• Example: Time-overcurrent relays for radial
system protection
• Calculation and coordination
• The largest fault current through B2 is 3000A. The fault-to-
pickup ratio for B2 is 15.
• The operating time of B2 relay under this fault current is 0.38
seconds.
• For the same fault, the fault-to-pickup ratio of B1 relay is 7.5.
• Adding the B2 relay operating time, breaker operating time,
and 0.3 second coordination time interval, the B1 relay’s
operating time should be 0.76 seconds (0.38+0.3+0.083).
• Select TDS=3 for B1 relay. [Confirm this results with Min.
fault current]
Basic Design Principles
• Instantaneous current-voltage relays
Basic Design Principles
• Directional sensing power relay
Basic Design Principles
• Polar unit
Basic Design Principles
• Phase distance relay
• Balance beam type
Basic Design Principles
• Phase distance relay
• Distance relay characteristics on the R-X diagram

Impedance mho Offset mho

Basic Design Principles
• Phase distance relay
• Distance relay characteristics on the R-X diagram

lens Simple blinder reactance

Basic Design Principles
• Phase distance relay
• Figures (b) through (e) can operate on a fault current
less than the load current.
• A load of 5 A (secondary CT) and 120 V line to line
appear to the relay as
120
Z load = = 13.86Ω
3 *5
Basic Design Principles
• Phase distance relay
• The equation of the mho circle through the origin is

Z R Z R ∠φ
Z= − (Typo in the book)
2 2
where
ZR is the offset from the origin
2
Z R ∠φ
2
is the radius from the offset point
(Typo in the book)

• When the mho circle is tilted, φ is the angle of φ R of

the offset
Basic Design Principles
• Phase distance relay
• Various operating point of the mho circle characteristic
are determined by the following equation:
Z X = Z R cos(φ R − φ X )
where
ZX is the impedance from the origin to any point on the
circle at angle φ X.
Basic Design Principles
• Phase distance relay
• For example, determine the reach of a mho relay unit
along a 75o angle line if the maximum load into the line
is 5 A secondary at 30o lagging. From previous
calculation, the load impedance is 13.86Ω secondary.
13.86 = ZR*cos(75o-30o)=19.6Ω .(secondary)
• This can be translated into primary line ohms by
considering the CT and VT ratio.
Basic Design Principles
• Zone protection of phase distance relay
Basic Design Principles
• Single phase MHO unit
• Three MHO units are required for a protective zone.
All three units operate for three-phase fault, but for
phase-to-phase and double-phase-to-ground faults, only
one unit operates. Thus,
• The A unit, energized by Iab, and Vab, operates for ab and ab-
gnd faults.
• The B unit, energized by Ibc, and Vbc, operates for bc and bc-gnd
faults.
• The C unit, energized by Ica, and Vca, operates for ca and ca-gnd
faults.
Basic Design Principles
• Single phase MHO unit
• Single phase MHO unit (shown for the A unit)
• An air-gap transformer provides a secondary voltage IabZc for
the A unit. Leading the primary current for lee than 90o.
• The combined output voltage is equal to IabZc – Vab. This
voltage with a polarizing voltage is compared to provide the
mho circle.
Basic Design Principles
• Poly-phase MHO unit
• This type of MHO unit has two units for a zone
protection:
• An mho circle through the origin for three-phase faults.
• A phase-to-phase unit, with a large operating circle
Basic Design Principles
• Poly-phase MHO unit
• This type of MHO unit has two units for a zone
protection:
• Three-phase faults unit
V x = Van − 1.5( I a − 3I 0 ) Z c
V y = Vbn
V z = Vcn
• The cylinder unit is like a two phase motor operating negative
sequence xzy is applied and retrains on positive sequence xyz.
• When a solid comparator is used, Vxy = Vab – (Ia –Ib)Zc and Vzy =
-jkVab are compared.
Basic Design Principles
• Poly-phase MHO unit
• This type of MHO unit has two units for a zone
protection:
• Phase-to-phase fault unit
V x = Van − ( I a − I b ) Z c
V y = Vbn
V z = Vcn − ( I c − I b ) Z c

• For a phase-to-phase faults at the balance or decision point,

VxVyVz provides a zero-area triangle (Vzy and Vxy in phase for solid
state comparator)
• Any fault inside the triple-zone negative sequence xzy, or when
Vzy lags Vxy cause operation.
Basic Design Principles
• Poly-phase MHO unit
• This type of MHO unit has two units for a zone protection:
• Phase-to-phase fault unit

Vzy
Basic Design Principles
• Ground distance relays
• Consider a phase-a-to-ground fault on a line with Z1L and Z0L
as the positive and zero sequence line impedance and n is
the location of the fault from the relay. The fault currents
through the relay are I0, I1, and I2. Then for a fault at nZ1L
with a single-phase unit:
Vag nZ 1L ( I 1 + I 2 ) + nZ 0 L I 0
= (typo)
Ia I1 + I 2 + I 0
• For voltage compensation, subtract out nZ1L(I1+I2) and use I0 (not Ia),
then:
Vag − nZ 1L ( I 1 + I 2 ) nZ 0 L I 0
ZR = = = nZ 0 L
I0 I0
Basic Design Principles
• Ground distance relays
• For current compensation, let nZ0L=pnZ1L (p=Z0L/Z1L). Then
Vag nZ1L ( I 1 + I 2 ) + pnZ1L I 0 nZ1L ( I 1 + I 2 + pI 0 ) nZ1L ( I a + ( p − 1) I 0 )
Z R' = = = =
Ia I1 + I 2 + I 0 I1 + I 2 + I 0 I1 + I 2 + I 0
Vag
ZR = = nZ1L
I a + mI 0
Z 0 L − Z 1L
where m =
Z 1L
Basic Design Principles
• Ground distance relays
• Considering fault resistance and mutual coupling from an
adjacent parallel line, the complete formula for current
compensated single-phase ground distance relay is:
Vag  3I 
ZR = = nZ 1L + R fault  0 
I relay I 
 relay  (typo)
( Z − Z 1L )
I a + I 0 0L
Z 1L
I relay =
I Z
1 + 0E 0M
I 0 Z 1L
where I0E is the zero sequence current in the parallel line and Z0M is the
mutual coupling impedance between two lines.
Microprocessor Based System
Protection
Introduction
 Inthe Utility Industry, Regardless Their Operation
Mechanisms, the Protective Relays are
Categorized and Evaluated by Their Functions.
 Same Test Procedures are Applied to a Group of
Relays With the Same Protective Function.
 The Performance of a Microcomputer Based
Relay Depends on the Hardware Design, the
Accuracy of the Input Signals, and the Algorithms
Embedded Inside the Unit
Introduction
 EachVendor Has Its Own Hardware Selection and
Software Design Preference. Therefore, the
Physical Capability and Constraints of a
Microcomputer Based Relay Are Different from
Vendor to Vendor Even with Similar Protective
Functions
General Structure of a Microcomputer
Based Relay
SUBSTATION & SWITCH YARD
Current & Voltage Contacts I/P Contacts O/P

Surge Surge Surge

Supressor Supressor Supressor
Output
Signal Signal Driver
Conditioning Conditioning

Sample/Hold Central Communication

A/D Conversion Processor
& Multiplexer Module
Unit

Memory Sub-System Surge

RAM, EPROM, EEPROM Supressor
Hardware Design Consideration

Central Processing Unit (CPU)

 Word Length
 Clock Speed
 Floating Point Calculation
 Single or Multiple Processor
 Technical Support
Hardware Design Consideration

Memory Subsystem
 Memory Types
– Read Only Memory (ROM): It is designed to
permanently store a fixed program which is not
alterable. It can only be programmed once and requires
special equipment to program the chips (Most of them
are pre-programmed by manufacturers). The
information is preserved even without power.
Hardware Design Consideration

Memory Subsystem
 Memory Types
– Random Access Memory (RAM): It is designed so that
information can be written into or read from any unique
location. There are two types of RAM: Static RAM and
Dynamic RAM. RAM does not retain its contents if
power is lost.
Hardware Design Consideration

Memory Subsystem
 Memory Types
– Programmable Read Only Memory (PROM): The
characteristics of PROM is similar to ROM except that
it is user programmable.
Hardware Design Consideration

Memory Subsystem
 Memory Types
– Erasable Programmable Read Only Memory
(EPROM): The EPROM is a specially designed PROM
that can be reprogrammed after being entirely erased
with the use of ultra-violet (UV) light source. The
EPROM can be considered as a semi-permanent data
storage device.
Hardware Design Consideration

Memory Subsystem
 Memory Types
– Non-Volatile Random Access Memory (NOVRAM):
Combination of RAM and EEPROM on a single chip.
This chip can protect data against power failure.
Hardware Design Consideration
Hardware Design Consideration

Usage of Memory
 Real-Time Data and Pre/Post-Fault Recorder:
RAM
 Program Memory: ROM, PROM, EPROM, or
Combination of RAM and EPROM
 Settings: Flash Memory or EEPROM
Hardware Design Consideration

Signal Conditioning
 The Outputs of the PT and CT Require Auxiliary
Transformers or Divider Circuits to Convert
Current and Voltage Signals Into Low Level
Voltage Signals Before They Can be Processed

Note: Some relay manufacturers are pushing the possibility of low

level input signals
Hardware Design Consideration

Signal Conditioning (Conti.)

 Since the Signals Are Highly Distorted During a
Disturbance and the Relay Operation is Mainly
Based on the Magnitude of Some Specific Signals,
an Analog Filter Circuit is Generally Used to
Perform First Stage Signal Screening. Later, it
Relies on the Digital Filter to Perform Further
Clean Up
Hardware Design Consideration

Signal Conditioning (Conti..)

 Anti-Alaising Filter Design
– Band-Pass Filter
– Low-Pass Filter
Hardware Design Consideration

Frequency Response of a Band-Pass Filter

Gain dB
0
Q=1
Q=5

-50
Q=10

-100
ωo Frequency (rad/sec)
Hardware Design Consideration

Phase Shift of a Band-Pass Filter

Phase deg
90

Q=10
Q=1
0

Q=5
-90
ωo Frequency (rad/sec)
Hardware Design Consideration

Frequency Response of a Low-Pass Filter

Gain dB
0

1st Order
-50
2nd Order
3rd Order

-100
ωc Frequency (rad/sec)
Hardware Design Consideration

Phase Shift of a Low-Pass Filter

Phase deg
0

-90
1st Order
-180 2nd Order

270- - 3rd Order

ωc Frequency (rad/sec)
Hardware Design Consideration

Data Sampling Circuit Designs

M M
U A/D U S/H A/D
X X

(a) (b)

S/H S/H A/D B

M U
S/H S/H A/D F
U A/D F
X E
S/H S/H A/D R

(c) (d)
Hardware Design Consideration

 A/D Conversion Techniques

– Dual Slope Tracking A/D Converter
Hardware Design Consideration

 A/D Conversion Techniques

– Dual Slope Successive-Approximation A/D
Converter
Hardware Design Consideration

 A/D Conversion Techniques

– Flash or Parallel Conversion
Hardware Design Consideration

 Sampling Algorithms of A/D Converter

– Sampling speed and available calculation time
– Constant time interval sampling or constant samples
per cycle
– Frequency calculation technique
Hardware Design Consideration

 Errors Associated with A/D Conversion

– Word Length
– Quantization Error of a N-bit A/D Converter is Equal to
2-N
– Gain, and Offset Errors
Hardware Design Consideration

 Errors Associated with A/D Conversion

Output

Desired Output
x

x Actual
Output
Quantization
Error
x

Offset
Error
10% 50% 90%
Input
Hardware Design Consideration

 Errors Associated with A/D Conversion

– Sampling Speed and Alaising Errors
Hardware Design Consideration

 Errors Associated with A/D Conversion

– Reconstruction Errors (Original Signal)
Hardware Design Consideration

 Errors Associated with A/D Conversion

– Reconstruction Errors (Sampled Data)
Hardware Design Consideration

 Errors Associated with A/D Conversion

– Reconstruction Errors (Reconstructed Waveform)
Hardware Design Consideration

 Errors Reduction Techniques for A/D Conversion

– Word Length Selection of A/D Converter
– Full Scale Value Selection
– Coordination Between Anti-Alaising Filter and
Sampling Speed
– Compensation of Gain and Offset Errors
– Programmable Gain Control
Hardware Design Consideration

Data Communication Subsystem

 Isolation of Communication Network
– Isolation of Power Supply
– Isolation of Signal Inputs (RJ-11 and RS232)
– Isolation of Grounding
– Survivability of Protection Function After Communication
Failure
Hardware Design Consideration

Data Communication Subsystem

 External or Internal Modem
– Baud Rate
– Future Upgrade
– Compatibility
– Power Supply
– Automatic Answer
Hardware Design Consideration

Data Communication Subsystem

 More Than One Units Share One Phone Line
– Mini Switch Board
– Local Area Network
– Communication Software Compatibility of Different Relays
From Different Venders
Hardware Design Consideration

Data Communication Subsystem

 Surge Withstand Capability and Walkie Talkie Test
– All the Open Connectors Should Comply With Surge
Withstand Capability and Radiated Electromagnetic
Interference Specified in IEEE Std. C-37.90.1 and C-
37.90.2.
Software Implementation Considerations

Programming Languages
 Execution Speed
 Portability
 Upgrade
 Graphical User Interface (GUI)
Software Implementation Considerations

Computation Algorithms
 Digital Filtering
– Non-Recursive Filter

Ym = X m + X m−2 3, 9, …

Ym = X m − X m−2 DC, 6, 12, …

Ym = X m + 3 X m−1 + X m−2 5, 7, ...

Software Implementation Considerations

Computation Algorithms
 Digital Filtering
– Recursive Filter
• Kalman Filter
• Fast Fourier Transform
• Curve Fitting
• Walsh Filter
Software Implementation Considerations

Computation Algorithms
 Convergence of a Recursive Filter
Software Implementation Considerations

Computation Algorithms
 Convergence of a Recursive Filter
Software Implementation Considerations

Computation Algorithms
 Magnitude Calculation

|V |2 = vm2 + vm2 −3
|V |2 = ( vm2 + vm2 −1 − 2vm vm−1 cos ∆T ) / sin 2 ∆T
Software Implementation Considerations

Computation Algorithms
 Phase Calculation

|V |*| I |*cos θ = v m * im + vm−3 * im−3

|V |*| I |*sin θ = vm * im−3 − v m−3 * im
Software Implementation Considerations

Moving Windows for Magnitude Estimation

W4
W3
Moving Data Window

W2

W1
Software Implementation Considerations

Computation Algorithms
 Calculation Algorithms
– Fault Detection Algorithm
– Fault Classification Algorithms
– Calculate Between Samples or Calculate After Several
Samples
Software Implementation Considerations

Computation Algorithms
 Decision Making Process
– Trip After One Violation
– Trip After Several Consecutive Violations
– Trip After Majority Violation of N Consecutive
Samples
– Similar Conditions Also Apply to Reset Procedure
Software Implementation Considerations

Computation Algorithms
 Auto Execution, Watch Dog Timer, and Self
Diagnostic
– Auto Execution After Power Failure
– Watch Dog Timer to Protect Against Software Failure
Software Implementation Considerations

Computation Algorithms
 Auto Execution, Watch Dog Timer, and Self
Diagnostic
– Self Diagnostic to Protect Against Hardware Failure.
• Frequency of Self Diagnostic Function
• Completeness of the Diagnostic Function
• Failure Isolation and Indication
Software Implementation Considerations

Data Communication Algorithm

 Communication Protocol
– Compatibility and Security
– EPRI’s UCA
Software Implementation Considerations
 Error Checking
– General properties of error detection and correction
• If the distance between any two code words of a code C is
>dmin, the code is said to have minimum distance of dmin
• In general, a code provides t error correction plus detection of
s additional errors if and only if the following inequality is
satisfied:
2t + s + 1 < dmin
Software Implementation Considerations
 Error Checking
– Definition of the distance
• The distance between I and J, d(I, J), is equal to the number of
bit position in which I and J differ.
• For example: I = 01101100 and J = 11000100

I=01101100
J=11000100

d(I, J) = 3
Software Implementation Considerations
 Error Checking
– Distance and error detection/correction

valid code word

dmin=2 dmin=4
Software Implementation Considerations
 ErrorDetection Algorithms
– Parity Check
• Even parity
• Odd parity
– Check Sum
• CRC
• LRC
• CX-ORC
Software Implementation Considerations
 Error Correction Algorithm
– Hamming code
i3 i2 i1 i0 c2c1c0
1000111 1110100
G= 0 1 0 0 1 1 0 H= 1 1 0 1 0 1 0
0010101 101100 1
0001011
Software Implementation Considerations
 Error Correction Algorithm
– Hamming code
• c2: even parity check of i3, i2, i1
• c1: even parity check of i3, i2, i0
• c0: even parity check of i3, i1, i0
• Transmit code word, c = iG
• HcT = 0
• If the receiving code, d, with error
d=c+e
• Syndrome, s = HdT = HeT
Software Implementation Considerations
 Error Correction Algorithm
– Syndrome table
Syndrome Meaning
000 No error
001 Error in c0
010 Error in c1
100 Error in c2
011 Error in i0
101 Error in 11
110 Error in i2
111 Error in i3
Software Implementation Considerations
 Error Correction Algorithm
– H matrix for (15, 11) hamming code
111101110001000
H= 111011001100100
110110100110010
101110011010001
• Code length: n = 2m - l -1
• Number of information bits: k = 2 m - m - l -1
• Number of check bits m = n - k
Software Implementation Considerations
 Example: Design a Hamming code for encoding
five (k =5) information bits
• Four check bit, m = 4, is required
• Delete six (6) columns from previous H matrix
111101000 100001111
H= 111010100 010001110
110110010 G= 001001101
101110001 000101011
000010111
Software Implementation Considerations
Unauthorized Access Prevention and Security
Operation
 Levels of Password
 Master Password
 Operation Reconfirmation
 Background Operation
 Settings Update Algorithm
Future Development of Microcomputer
Based Relay Systems

 ArtificialIntelligence
 Multiple Function Relays
 Common Hardware Configuration
 Software (Firmware) Driven Protective
Function(s)
 Stronger Communication Capability
 Serve as Pre-/Post-Fault Recorder