INSTRUCTIONS SET OF 8085 MICROPROCESSOR

INSTRUCTIONS SET OF 8085

An Instruction is a command given to the microprocessor to perform a specified operation on given data. The instruction set of a microprocessor is the collection of the instructions that the microprocessor is designed to execute. The programmer can write a program in assembly language using these instructions. These instructions have been classified into the following groups: Data Transfer Group Arithmetic Group Logical Group Branch Control Group I/O and Machine Control Group

DATA TRANSFER GROUP

Instructions, which are used to transfer data from one register to another register, from memory to register or register to memory, come under this group. When an instruction of data transfer group is executed, data is transferred from the source to the destination without altering the contents of the source.

DATA TRANSFER GROUP

1) MOV r1, r2
(Move Data; Move the content of the one register to another).

[r1]
Example:

[r2].

MOV C,B. Move the content of register B to C.

Initially
After execution
Flags Affected Addressing mode Memory require Machine Cycle require T- States

B=10H.
B=10H.
Register.

C=20H.
C=10H.

No flags affected. 1Byte Instruction 1 4

DATA TRANSFER GROUP

2) MOV R, M (Move the content of memory to register). r [M] Move the content of memory location, whose adders is in H-l pair to register r
Flags Affected Addressing mode Memory require No flags affected. Indirect. 1Byte Instruction

Machine Cycle require

T- States

2
7

EXAMPLE:
MOV C, M Move the content of memory location (M) , whose adders is in H-l pair {2000H} to register C

Initially content of memory location (M) 32H After execution content of memory location (M) 32H

C=00 H. C=32H.

Register C H- L

20 00 H

32H

32 00 H H

DATA TRANSFER GROUP

3) MOV M, R (Move the content of register to memory). [M] R Move the content of register R to memory location(M),

whose adders is in H-l pair

Flags Affected Addressing mode No flags affected. Indirect.

Memory require Machine Cycle require

T- States

1Byte Instruction 2
7

EXAMPLE:
MOV M,C Move the content of register C to memory location (M) whose adders is in H-l pair {2000H}

Initially content of memory location (M) 00 H After execution content of memory location (M) 32H

C=32 H. C=32H.

Register C H- L

20 00 H

00H 32H

32 H

DATA TRANSFER GROUP

4) MVI r, data. (Move immediate data to register). [r] data.(8 bit)
Example: MVI B, 30H. (Move the data 30 H to Register B) Initially After execution
Flags Affected Addressing mode Memory require Machine Cycle require T- States

B=40H B=30H
No flags affected. Immediate. 2Byte Instruction 2 7

DATA TRANSFER GROUP

5) MVI M, data. (Move immediate data to memory whose adders is in H-l pair {2000H}. [M]
Flags Affected Addressing mode

data.(8 bit)
No flags affected. Immediate.

Memory require
Machine Cycle require T- States

2Byte Instruction
2 7

DATA TRANSFER GROUP

Example:
MVI M, 32H. (Move the data 30 H to memory whose adders is in H-l pair {2000H}. Initially content of memory location (M) After execution content of memory location (M)
Data

=40H =32H

H- L

20 00 H

40H 32H

32 H

DATA TRANSFER GROUP

6) LXI rp, data 16. (Load register pair immediate 16 bits data). [rp] data 16 bits
We have 3 register pair 1) B-C 2) D-E 3) H-L Example: LXI B, C200H. (Load register pair B-C with C200H). Initially B=C800H After execution B=C200H.
Flags Affected
Addressing mode Memory require Machine Cycle require

No flags affected.
Immediate. 3Byte Instruction 3

T- States

10

DATA TRANSFER GROUP

7) LDA adders. (Load Accumulator direct) (load accumulator direct by the content of memory
location (M) whose adders is directly given in instruction its self).

[A]
Flags Affected

[adders].
No flags affected.

Addressing mode
Memory require Machine Cycle require T- States

Direct
3Byte Instruction 4 13

DATA TRANSFER GROUP

Example:
LDA 2000H (load accumulator direct by the content of memory location (2000H) whose adders is directly given in instruction its self.) Initially A = 40H After execution A = 32H

Accumulator

2000 H

32H

40 32 H H

DATA TRANSFER GROUP

8) STA adders. (Store accumulator direct) (Store the content of accumulator direct to the memory
location (M) whose adders is directly given in instruction its self).

[A]
Flags Affected

[adders].
No flags affected.

Addressing mode
Memory require Machine Cycle require T- States

Direct
3Byte Instruction 4 13

DATA TRANSFER GROUP

Example:
STA 2000H (Store the content of accumulator direct to the memory location (2000H) whose adders is directly given in instruction its self) Initially content of memory location (M) After execution content of memory location (M) =40H =32H

Accumulator

2000 H

40H 32H

32 H

DATA TRANSFER GROUP

9) LHLD adders (Load H-L pair direct) (load register L by the content of memory location
whose adders is directly given in instruction its self. Load register H by the content of next memory location).

[L] [H]
Flags Affected Addressing mode Memory require Machine Cycle require

[addr], [addr+1].
No flags affected. Direct 3Byte Instruction 5

T- States

16

DATA TRANSFER GROUP

Example:
LHLD 2000H (load register L by the content of memory location(2000) whose adders is directly given in instruction its self. Load register H by the content of next memory location(2001)) Initially L = 00H After execution L = 32H H = 23H H = 00H

2000 H 2001 H

32H 23H

00 32 HH 23 00 HH

L H

DATA TRANSFER GROUP

9) SHLD adders (Store H-L pair direct) (Store the content register L to the memory location
whose adders is directly given in instruction its self. Store the content register H to the of next memory location).

[L] [H]
Flags Affected Addressing mode Memory require Machine Cycle require

[addr], [addr+1].
No flags affected. Direct 3Byte Instruction 5

T- States

16

DATA TRANSFER GROUP

Example:
SHLD 2000H (Store the content register L to the memory location(2000) whose adders is directly given in instruction its self. Store the content register H to the of next memory location(2001)) Initially content of memory location (M) 2000 = 40H, 2001 = 41 After execution content of memory location (M)2000 = 32H, 2001 = 23H

2000 H 2001 H

32H 40H 41H 23H

32 H 23 H

L H

DATA TRANSFER GROUP

10) LDAX Rp. (LOAD accumulator indirect) (Load accumulator by the content of memory location
(M) whose adders is given in register pair).

[A]

[Rp].

Flags Affected

No flags affected.

Addressing mode
Memory require Machine Cycle require T- States

Indirect
1Byte Instruction 2 7

DATA TRANSFER GROUP

Example:
LDAX B (Load accumulator by the content of memory location (2000H) whose adders is given in register pair.) Initially A = 40H After execution A = 32H

B- C

Accumulator

20 00 H

32H

40 32 H H

DATA TRANSFER GROUP

11) STAX Rp. (Store accumulator indirect) (Store the content of accumulator to the memory
location (M) whose adders is given in register pair).

[A]

[adders].

Flags Affected

No flags affected.

Addressing mode
Memory require Machine Cycle require T- States

Register indirect
1Byte Instruction 2 7

DATA TRANSFER GROUP

Example:
STAX B (Store the content of accumulator to the memory location (2000H) whose adders is given in register pair) Initially content of memory location (M) After execution content of memory location (M) =40H =32H

Accumulator

20 00 H

32H 00H

32 H

DATA TRANSFER GROUP

12) XCHG.
(Exchange the contents of H-L with D-E pair) [H-L] [D-E].
Example: XCHG Initially L = 15H H = 16H D = 32H E = 23H L = 32H H = 23H D = 15H E = 16H
No flags affected.
Regiser 1Byte Instruction 1 4

After execution
Flags Affected

Addressing mode Memory require Machine Cycle require T- States

ARITHMETIC GROUP

The instructions of this group perform arithmetic operations such as addition, subtraction; increment or decrement of the content of a register or memory.

ARITHMETIC GROUP
ADD R
(ADD register content with Acc and result in A ).

[A]

[A] + [r].

Example: ADD C. (ADD the content of C with A). Suppose the Data at C register is 10H. Initially C= 10H , After execution A=20H,
Flags Affected Addressing mode Memory require Machine Cycle require T- States All flags affected. Register 1Byte Instruction 1 4

A=10H C=10H.

ARITHMETIC GROUP
ADD M
(ADD memory content with Acc and result in A ).

[A]

[A] + [M].

Example: ADD M. (ADD the content of memory with A). Suppose the Data at memory is 10H. Initially M= 10H , A=10H After execution A=20H, M=10H.
Flags Affected Addressing mode Memory require Machine Cycle require T- States All flags affected. Register indirect 1Byte Instruction 2 7

ARITHMETIC GROUP
ADI Data
(ADD immediate data with Acc and result in A ).

[A]
Example:

[A] + data.

ADI 30H. (ADD 30H with A).

Suppose the Data at Accumulator is 20H.

Initially After execution
Flags Affected Addressing mode Memory require Machine Cycle require T- States

A=20H A=50H.
All flags affected. Immediate 2Byte Instruction 2 7

ARITHMETIC GROUP
ADC R
(ADD register with carry to accumulator and result in A ).

[A]

[A] + [r] + [CS].

Example: ADC C. (ADD the content of C with A considering carry). Suppose the Data at C register is 10H. Initially C= 10H , A=10H CS = 1 After execution A=21H, C=10H.
Flags Affected Addressing mode Memory require Machine Cycle require T- States All flags affected. Register 1Byte Instruction 1 4

ARITHMETIC GROUP
ADC M (ADD memory content with carry to accumulator and result in A ). [A] [A] + [M] + [CS]. Example: ADD M. (ADD the content of memory with A considering carry). Suppose the Data at memory is 10H. Initially M= 10H , A=10H CS = 1 After execution A=21H, M=10H.
Flags Affected
Addressing mode Memory require Machine Cycle require

All flags affected.

Register indirect 1Byte Instruction 2

T- States

ARITHMETIC GROUP
ACI Data
(ADD immediate data with carry to accumulator and result in A ). [A] Example: ADI 30H. (ADD 30H with A considering carry). [A] + data + [CS]

Suppose the Data at Accumulator is 20H.

Initially After execution
Flags Affected Addressing mode Memory require Machine Cycle require T- States

A=20H CS = 1 A=51H.
All flags affected. Immediate 2Byte Instruction 2 7

ARITHMETIC GROUP
SUB R
(Subtract register content from Acc and result in A ).

[A]

[A] - [r].

Example: SUB C. (Subtract the content of C from A). Suppose the Data at C register is 10H. Initially C= 10H , A=20H After execution A=10H, C=10H.
Flags Affected Addressing mode Memory require Machine Cycle require T- States All flags affected. Register 1Byte Instruction 1 4

ARITHMETIC GROUP
SUB M
(Subtract memory content from Acc and result in A ).

[A]

[A] - [M].

Example: SUB M. (Subtract the content of memory from A). Suppose the Data at memory is 10H. Initially M= 10H , A=20H After execution A=10H, M=10H.
Flags Affected Addressing mode Memory require Machine Cycle require T- States All flags affected. Register indirect 1Byte Instruction 2 7

ARITHMETIC GROUP
SUI Data
(Subtract immediate data from Acc and result in A ).

[A]
Example:

[A] - data.

SUI 30H. (Subtract 30H from A).

Suppose the Data at Accumulator is 50H.

Initially After execution
Flags Affected Addressing mode Memory require Machine Cycle require T- States

A=50H A=20H.
All flags affected. Immediate 2Byte Instruction 2 7

ARITHMETIC GROUP
SBB R
(Subtract register with borrow from accumulator and result in A ).

[A]

[A] - [r] - [CS].

Example: SBB C. (Subtract the content of C from A with borrow). Suppose the Data at C register is 10H. Initially C= 10H , A=20H CS = 1 After execution A=9H, C=10H.
Flags Affected Addressing mode Memory require Machine Cycle require T- States All flags affected. Register 1Byte Instruction 1 4

ARITHMETIC GROUP
SBB M
(Subtract memory content with borrow from accumulator and result in A ). [A] [A] - [M] - [CS]. Example: SBB M. (ADD the content of memory from A with borrow). Suppose the Data at memory is 10H. Initially M= 10H , A=20H CS = 1 After execution A=09H, M=10H.

ARITHMETIC GROUP
SBI Data
(Subtract immediate data with borrow from accumulator and result in A ). [A] Example: SBI 30H. (Subtract 30H from A with borrow). [A] data-[CS]

Suppose the Data at Accumulator is 20H.

Initially After execution
Flags Affected Addressing mode Memory require Machine Cycle require T- States

A=50H CS = 1 A=19H.
All flags affected. Immediate 2Byte Instruction 2 7

ARITHMETIC GROUP
INR R
(Increment register content by 1 ).

[R]
Example:

[R] +1.

INR C. (Increment the content of C by 1). Suppose the Data at C register is 10H. Initially C= 10H C=11H.

After execution

ARITHMETIC GROUP
DCR R
(Decrement register content by 1 ).

[R]
Example:

[R] -1.

DCR C. (Decrement the content of C by 1). Suppose the Data at C register is 10H. Initially C= 10H C= 09H.

After execution

ARITHMETIC GROUP
INR M
(Increment content of memory by 1 ).

[M]
Example:

[M] +1.

INR M. (Increment the content of M by 1). Suppose the Data at M is 10H. Initially M= 10H M=11H.

After execution

ARITHMETIC GROUP
DCR M
(Decrement content of memory by 1 ).

[M]
Example:

[M] -1.

DCR M. (Decrement the content of M by 1). Suppose the Data at M is 10H. Initially M= 10H M= 0FH.

After execution

ARITHMETIC GROUP
INX Rp
(Increment register pair content by 1 ).

[Rp]
Example:

[Rp] +1.

INX B. (Increment the content of BC pair by 1). Suppose the Data at B-C register pair is 1110H. Initially B= 1110H B= 1111H.

After execution

ARITHMETIC GROUP
DCX Rp
(Decrement register pair content by 1 ).

[Rp]
Example:

[Rp] -1.

DCX B. (Decrement the content of B by 1). Suppose the Data at B-C register pair is 1110H. Initially B= 1110H B= 110FH.

After execution

ARITHMETIC GROUP
DAD Rp (Add specified register pair with HL pair)
(Add the content of E with L and that of D with H register and result in HL pair) [H-L] [H-L] + [rp]. Example: DAD D.(Add the content of E with L and that of D with H register and result in HL pair) Initially H=20H ,L=40H D=30H, E=10H After execution H=50H ,L=50H D=30H, E=10H

ARITHMETIC GROUP

LOGICAL GROUP
The Instructions under this group perform logical operation such as AND, OR, compare, rotate etc.

Examples are: ANA, XRA, ORA, CMP, and RAL etc.

LOGICAL GROUP
ANA R
(Logically AND content of register with Acc and result in A )

[A] [A] ^ [r]

Example: ANA C (AND the content of C with A). Suppose the Data at C register is 10H. Initially C= 10H, A=10H After execution A= 10H, C=10H.

LOGICAL GROUP
ANI Data
(Logically AND immediate data with Acc and result in A )

[A] [A] ^ [data]

Example: ANI 10 (AND the data with A). Suppose the Data is 10H. Initially Data = 10H, A=10H After execution Data = 10H, A=10H.

LOGICAL GROUP
ANA M
(Logically AND content of memory with Acc and result in A )

[A] [A] ^ [M]

Example: ANA M (AND the content of memory with A). Suppose the content of memory is 10H. Initially M=10H, A = 10H After execution M=10H, A = 10H .

LOGICAL GROUP
ORA R
(Logically OR register content with Acc and result in A)

[A] [A] v [r]

Example: ORA C (OR the content of C with A).

Suppose the Data at C register is 17H.

Initially After execution C= 17H, C= 17H, A=10H A=17H

LOGICAL GROUP
ORI Data
(Logically OR immediate Data with Acc and result in A ).

[A] [A] v [Data]

Example: ORI 17 (OR the Data with A).

Suppose the Data is 17H.

Initially After execution Data= 17H, Data= 17H, A=10H A=17H

LOGICAL GROUP
ORA M
(Logically OR memory content with Acc and result in A).

[A] [A] v [M]

Example: ORA M (OR the content of memory with A).

Suppose the Data at memory is 17H.

Initially After execution M= 17H, M= 17H, A=10H A=17H

LOGICAL GROUP
XRA R
(Logically XOR register content with Acc and result in A)

[A] [A]
Example:

[r]

XRA C (XOR the content of C with A). Suppose the Data at C register is 17H. Initially After execution A=10H,C= 17H A=07H,C=17H.

LOGICAL GROUP
XRI Data
(Logically XOR immediate Data with Acc and result in A)

[A] [A]
Example:

[Data]

XRI 17 (XOR the Data with A). Suppose the Data is 17H. Initially After execution A=10H,Data=17H A=07H,Data=17H.

LOGICAL GROUP
XRA M
(Logically XOR memory content with Acc and result in A)

[A] [A]
Example:

[M]

XRA M (XOR the content of memory with A). Suppose the memory content is 17H. Initially After execution A=10H,M= 17H A=07H,M=17H.

LOGICAL GROUP
CMA. (Complement the accumulator) [A] [A]
Example: CMA (Complement the accumulator0

Suppose the Data at accumulator is FFH.

Initially After execution A=FFH A=00H

LOGICAL GROUP
CMC (Complement the carry status) [CS] [CS] STC (Set carry status) [CS] 1.

LOGICAL GROUP
CMP r. (Compare register with accumulator) [A] [r] The content of the register r is subtracted from the content of the accumulator and status flags are set according to the result of subtraction . But the result is discarded. The content of the accumulator remain unchanged.

LOGICAL GROUP
CMP M. (Compare memory content with accumulator) [A] [M] The content of the memory is subtracted from the content of the accumulator and status flags are set according to the result of subtraction . But the result is discarded. The content of the accumulator remain unchanged.

LOGICAL GROUP
CMP Data. (Compare immediate Data with accumulator) [A] [Data] The immediate Data is subtracted from the content of the accumulator and status flags are set according to the result of subtraction . But the result is discarded. The content of the accumulator remain unchanged.

LOGICAL GROUP
RLC (Rotate accumulator left) The content of the accumulator is rotated left by one bit. The seventh bit of the accumulator is moved to carry bit as well as to the zero bit of the accumulator. Only CS flag is affected. [An+1] [An], [A0] [A7], [CS] [A7]

CS

A7

A6

A5

A4

A3

A2

A1

A0

LOGICAL GROUP
RRC. (Rotate accumulator right) The content of the accumulator is rotated right by one bit. The zero bit of the accumulator is moved to the seventh bit as well as to carry bit. Only CS flag is affected. [An] [An+1] , [CS] [A0] , [A7][A0]

CS

A7

A6

A5

A4

A3

A2

A1

A0

LOGICAL GROUP
RAL (Rotate accumulator left through carry) The content of the accumulator is rotated left by one bit. The seventh bit of the accumulator is moved to carry bit & carry bit to the zero bit of the accumulator. Only CS flag is affected. [An+1] [An], [A0] [CS], [CS] [A7]

CS

A7

A6

A5

A4

A3

A2

A1

A0

LOGICAL GROUP
RAR. (Rotate accumulator right through carry) The content of the accumulator is rotated right by one bit. The zero bit of the accumulator is moved to the to carry bit & carry bit to the seventh bit. Only CS flag is affected. [An] [An+1] , [CS] [A0], [A7][CS]

CS

A7

A6

A5

A4

A3

A2

A1

A0

BRANCH GROUP
Conditional Jump addr (label): After the execution of the conditional jump instruction the program jumps to the instruction specified by the address (label) if the specified condition is fulfilled. The program proceeds further in the normal sequence if the specified condition is not fulfilled. If the condition is true and program jumps to the specified label, the execution of a conditional jump takes 3 machine cycles: 10 states. If condition is not true, only 2 machine cycles; 7 states are required for the execution of the instruction.

BRANCH GROUP
JZ addr (label). (Jump if the result is zero) JNZ addr (label) (Jump if the result is not zero) JC addr (label). (Jump if there is a carry) JNC addr (label). (Jump if there is no carry) JP addr (label). (Jump if the result is plus) JM addr (label). (Jump if the result is minus)

JPE addr (label) (Jump if even parity)

JPO addr (label) (Jump if odd parity)

BRANCH GROUP
JZ adders (label). (Jump if the result is zero)
ARITHMETIC OR LOGICAL OPERATION

ALL FLAGS WILL BE AFECTED

IF ZERO FLAG

=1
SATE OF ZERO FLAG

IF ZERO FLAG

=0

GO TO ADDERS (LABEL)

GO FOR NEXT INSTRUCTION

BRANCH GROUP
JNZ adders (label). (Jump if the result is not zero)
ARITHMETIC OR LOGICAL OPERATION

ALL FLAGS WILL BE AFECTED

IF ZERO FLAG

=0
SATE OF ZERO FLAG

IF ZERO FLAG

=1

GO TO ADDERS (LABEL)

GO FOR NEXT INSTRUCTION

BRANCH GROUP
JC addr (label). (Jump if there is a carry)
ARITHMETIC OR LOGICAL OPERATION

ALL FLAGS WILL BE AFECTED

IF

carry FLAG = 1
SATE OF

IF

carry FLAG = 0

carry
FLAG

GO TO ADDERS (LABEL)

GO FOR NEXT INSTRUCTION

BRANCH GROUP
JNC addr (label). (Jump if there is a carry)
ARITHMETIC OR LOGICAL OPERATION

ALL FLAGS WILL BE AFECTED

IF

carry FLAG = 0
SATE OF

IF

carry FLAG = 1

carry
FLAG

GO TO ADDERS (LABEL)

GO FOR NEXT INSTRUCTION

BRANCH GROUP
JP addr (label). (Jump if there is a plus) (Jump if sign flag reset )
ARITHMETIC OR LOGICAL OPERATION

ALL FLAGS WILL BE AFECTED

IF

sign FLAG = 0
SATE OF

IF

sign FLAG = 1

sign FLAG

GO TO ADDERS (LABEL)

GO FOR NEXT INSTRUCTION

BRANCH GROUP
JM addr (label). (Jump if there is a minus) (Jump if sign flag is set or minus)
ARITHMETIC OR LOGICAL OPERATION

ALL FLAGS WILL BE AFECTED

IF

sign FLAG = 1
SATE OF

IF

sign FLAG = 0

sign FLAG

GO TO ADDERS (LABEL)

GO FOR NEXT INSTRUCTION

BRANCH GROUP
JPE addr (label). (Jump if parity flag is set)
ARITHMETIC OR LOGICAL OPERATION

ALL FLAGS WILL BE AFECTED

IF

parity FLAG = 1
SATE OF

IF

parity FLAG = 0

parity
FLAG

GO TO ADDERS (LABEL)

GO FOR NEXT INSTRUCTION

BRANCH GROUP
JPO addr (label). (Jump if parity odd or P flag is reset )
ARITHMETIC OR LOGICAL OPERATION

ALL FLAGS WILL BE AFECTED

IF

parity FLAG = 0
SATE OF

IF

parity FLAG = 1

parity
FLAG

GO TO ADDERS (LABEL)

GO FOR NEXT INSTRUCTION