Chapter 5 : Processing Unit
Chapter objectives
In this chapter you will learn about: Execution of instructions by a processor The functional units of a processor and how they are interconnected Hardware for generating control signals Microprogrammed control
Main hardware components of a processor
Recap: Organisation
Bus
Processor
Control
Memory
Devices
Input
Cache Datapath
Output Registers
Fundamental Concepts
Processor (CPU): the active part of the computer,
which does all the work (data manipulation and decision-making). Datapath: portion of the processor which contains hardware necessary to perform all operations required by the computer (the brawn). Control: portion of the processor (also in hardware) which tells the datapath what needs to be done (the brain).
Fetch and execute phase
Fetching an instruction and loading it into the IR is usually referred to as the instruction fetch phase. Performing the operation specified in the instruction constitutes the instruction execution phase. With few exceptions, the operation specified by an instruction can be carried out by performing one or more of the following actions: Read the contents of a given memory location and load them into a processor register. Read data from one or more processor registers. Perform an arithmetic or logic operation and place the result into a processor register. Store data from a processor register into a given memory location.
Fetch and execute phase cont..
Instruction execution
cycle: fetch, decode, execute. Fetch: fetch next instruction
(using PC) from memory into IR. Decode: decode the instruction. Execute: execute instruction.
Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction
Single-bus Organization
Internal processor bus
Register Y, Z and TEMP are use ONLY by the processor unit for temporary storage during the execution of some instructions. Programmer cannot access these registers The IR and the Instruction decoder are integral parts of the control circuitry in the processing unit.
PC Address line Memory bus Data line MAR MDR
Control signals ...
Instruction decoder and control logic
IR Constant 4 Select ALU control lines
Add Sub
Y RO
MUX
A B
: : R(n1)
Carry-in
:
XOR
ALU
TEMP Z
Processor: Datapath and Control
Single-bus Organization
The data registers, ALU and the interconnecting bus is referred to as data path Register R0 through R(n1) are the processor register These register include General Purpose Register and Special Purpose Register (stack pointer, index register and pointers) The Register and ALU are used for storing and manipulating data These are 2 option provides for A & B input of the ALU. Select by MUX
Internal processor bus PC Address line Memory bus Data line MAR MDR IR Constant 4 Select ALU control lines
Add Sub
Control signals ...
Instruction decoder and control logic
Y RO
MUX
A B
: : R(n1)
Carry-in
:
XOR
ALU
TEMP Z
Processor: Datapath and Control
Single-bus Organization
Internal processor bus PC
Control signals ...
Instruction decoder and control logic
The Multiplexer (MUX) is used to select one of the two inputs If select (1) select output of Y If select (0)- select Constant as input A for ALU The constant number is used to increment the contents of program counter
Address line Memory bus Data line
MAR MDR
IR Constant 4 Select ALU control lines
Add Sub
Y RO
MUX
A B
: : R(n1)
Carry-in
:
XOR
ALU
TEMP Z
Processor: Datapath and Control
The execution of various instructions processor:
Register Transfer
Register to register transfer: For each register Ri, two control signals: Riin used to load the data
on the bus into the register. Riout to place the registers Select contents on the bus.
Constant 4 MUX
A B
Internal processor bus Yin X Y X Ri Riin
X
Riout
Example: To transfer contents of R1 to R4: Set R1out to 1. This places
contents of R1 on the bus. Set R4in to 1. This loads data from the processor bus into R4.
ALU
Zin
Z X Zout
Arithmetic/Logic Operation
Internal processor bus
ALU: Performs
arithmetic and logic operations on its A and B inputs. Select To perform R3 [R1] + [R2]:
1. R1out, Yin 2. R2out, SelectY, Add, Zin 3. Zout, R3in
Constant 4 MUX
A
Yin X Y X X Ri
Riin
Riout
B
ALU Zin X
Z X Zout
External Memory Bus
MDR has four control signals: MDRin, MDRout, MDRinE and MDRoutE.
Memory-bus data lines
Internal processor bus
MDRinE
MDRin
MDR
MDRoutE
MDRout
External Memory Bus Datapath
Memory-bus data lines
MDRinE X MDR X MDRoutE X MDRout Internal processor bus MDRin Address line X Memory bus Data line PC MAR MDR Internal processor bus Control signals ...
Instruction decoder and control logic
IR Constant 4 Select ALU control lines
Add Sub
RO
MUX
A B
: : R(n1)
Carry-in
:
XOR
ALU TEMP Z
Regiter to/ from Memory Transfer
Memory-bus data lines
MDRinE X MDR X MDRoutE X MDRout Internal processor bus MDRin Address line X Memory bus Data line PC MAR MDR Internal processor bus Control signals ...
Instruction decoder and control logic
IR Constant 4 Select ALU control lines
Add Sub
RO
MUX
A B
: : R(n1)
Carry-in
:
XOR
ALU TEMP Z
Reading a Word from Memory
Move (R1), R2/* R2 [[R1]] Instruction Sequence
1. MAR [R1] 2. Start a Read operation on the memory bus 3. Wait for the MFC response from the memory MFC MemoryFunction-Completed Signal 4. Load MDR from the memory bus 5. R2 [MDR]
PC Address line Memory bus Data line MAR MDR Internal processor bus Control signals ...
Instruction decoder and control logic
IR Y Constant 4 RO Select MUX
Add Sub A B
Sequence of control steps:
1. 2. 3. 4. 5. R1out, MARin, Read MDRinE, WMFC MDRout, R2in
ALU control lines
: : R(n1)
Carry-in
:
XOR
ALU TEMP Z
WMFC: Wait for arrival of MFC (MemoryFunction-Completed) signal.
Storing a Word in Memory
Move R2, (R1)/* [R1] R2 Sequence of control steps:
R1out, MARin 2. R2out, MDRin, Write 3. MDRoutE, WMFC
1. Address line Memory bus Data line Internal processor bus PC MAR MDR Control signals ...
Instruction decoder and control logic
IR Y Constant 4 RO Select MUX
Add Sub A B
: : R(n1)
Carry-in
ALU control lines
:
XOR
ALU TEMP Z
