Logic Families

Introduction & Overview

CSET 4650 Field Programmable Logic Devices

Dan Solarek

Logic Families
Logic Family : A collection of different ICs that have similar circuit characteristics The circuit design of the basic gate of each logic family is the same The most important parameters for evaluating and comparing logic families include :
Logic Levels Power Dissipation Propagation delay Noise margin Fan-out ( loading )

Example Logic Families

General comparison or three commonly available logic families.

the most important to understand 3

Implementing Logic Circuits

There are several varieties of transistors the building blocks of logic gates the most important are:
BJT (bipolar junction transistors)
one of the first to be invented

FET (field effect transistors)

especially Metal-Oxide Semiconductor types (MOSFETs) MOSFETs are of two types: NMOS and PMOS

Transistor Size Scaling

Performance improves as size is decreased: shorter switching time, lower power consumption.

2 orders of magnitude reduction in transistor size in 30 years.

Moores Law
In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months
i.e., grow exponentially with time

Considered a visionary million transistor/chip barrier was crossed in the 1980s

2300 transistors, 1 MHz clock (Intel 4004/4040) - 1971 42 Million transistors, 2 GHz clock (Intel P4) - 2001 140 Million transistors, (HP PA-8500)

Moores Law and Intel

From Intels 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond

TTL and CMOS

Connecting BJTs together gives rise to a family of logic gates known as TTL Connecting NMOS and PMOS transistors together gives rise to the CMOS family of logic gates
MOSFET (NMOS, PMOS)

BJT

transistor types

TTL

logic gate families

CMOS 8

Electrical Parameters And Interpretation Of Data Sheets

Voltages and Currents Noise Margin Power Dissipation Propagation Delay Speed-Power Product Fan-In, Fan-Out Comparison of Logic Families Interpretation of Data Sheets
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Electrical Characteristics
TTL
faster (some versions) strong drive capability rugged

CMOS
lower power consumption simpler to make greater packing density better noise immunity

Complex ICs contain many millions of transistors If constructed entirely from TTL type gates would melt A combination of technologies (families) may be used CMOS has become most popular and has had greatest development 10

Voltage & Current

For a High-state gate driving a second gate, we define:
VOH (min), high-level output voltage, the minimum voltage level that a logic gate will produce as a logic 1 output. VIH (min), high-level input voltage, the minimum voltage level that a logic gate will recognize as a logic 1 input. Voltage below this level will not be accepted as high. IOH, high-level output current, current that flows from an output in the logic 1 state under specified load conditions. IIH, high-level input current, current that flows into an input when a logic 1 voltage is applied to that input.

Test setup for measuring values

Ground

I OH VOH

I IH VIH

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Voltage & Current

For a Low-state gate driving a second gate, we define:
VOL (max), low-level output voltage, the maximum voltage level that a logic gate will produce as a logic 0 output. VIL (max), low-level input voltage, the maximum voltage level that a logic gate will recognize as a logic 0 input. Voltage above this value will not be accepted as low. IOL , low-level output current, current that flows from an output in the logic 0 state under specified load conditions. IIL , low-level input current, current that flows into an input when a logic 0 voltage is applied to that input.
Inputs are connected to Vcc instead of Ground
Ground

OL

I IL
V IL

V OL

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Electrical Characteristics
logic 1

Important characteristics are:

VOHmin min value of output recognized as a 1 VIHmin min value input recognized as a 1 VILmax max value of input recognized as a 0 VOLmax max value of output recognized as a 0

indeterminate input voltage

logic 0

Values outside the given range are not allowed.

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Logic Level & Voltage Range

Typical acceptable voltage ranges for positive logic 1 and logic 0 are shown below A logic gate with an input at a voltage level within the indeterminate range will produce an unpredictable output level.
5.0V Logic 1 3.5V 2.5V Indeterminate 0.8V Logic 0 0V TTL 0V CMOS 1.5V Logic 0 Indeterminate 5.0V

Logic 1

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Noise Margin
Manufacturers specify voltage limits to represent the logical 0 or 1. These limits are not the same at the input and output sides.
For example, a particular Gate A may output a voltage of 4.8V when it is supposed to output a HIGH but, at its input side, it can take a voltage of 3V as HIGH.

In this way, if any noise should corrupt the signal, there is some margin for error.

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Noise Margin
If noise in the circuit is high enough it can push a logic 0 up or drop a logic 1 down into the indeterminate or illegal region The magnitude of the voltage required to reach this level is the noise margin Noise margin for logic high is:
NMH = VOHmin VIHmin
VOHmin VIHmin

logic 1

indeterminate input voltage

logic 0

VILmax VOLmax

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Noise Margin
Difference between the worst case output voltage of one stage and worst case input voltage of next stage Greater the difference, the more unwanted signal that can be added without causing incorrect gate operation
NMhigh = VOHmin - VIHmin

NMlow = VILmax - VOLmax

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Worked Example
Given the following parameters, calculate the noise margin of 74LS series.
Parameter VIH (min) VIL(max) VOH(min) VOL(max) 74LS 2V 0.8V 2.7V 0.4V

Solution:
High Level Noise Margin, VNH = VOH (min) - VIH (min)=2.7V-2.0V=0.7V Low Level Noise Margin, VNL = VIL (max) - VOL (max)=0.8V-0.4V=0.4V

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Noise Margin & Noise Immunity

Noise immunity of a logic circuit refers to the circuits ability to tolerate noise voltages on its inputs. A quantitative measure of noise immunity is called noise margin High Level Noise Margin, VNH = VOH (min) - VIH (min) Low Level Noise Margin, VNL = VIL (max) - VOL (max)
Logic 1 VOH (min) Logic 1

VNH

VIH (min) VIL (max) Logic 0

Input Voltage Ranges

VOL (max) Logic 0

Output Voltage Ranges

VNL

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Further Important Characteristics

The propagation delay (tpd) which is the time taken for a change at the input to appear at the output The fan-out, which is the maximum number of inputs that can be driven successfully to either logic level before the output becomes invalid

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Speed: Rise & Fall Times

Rise Time
Time from 10% to 90% of signal, Low to High

Fall Time
Time from 90% to 10% of signal, High to Low
rise time fall time

10%

90%

90%

10%

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Speed: Propagation Delay

A logic gate always takes some time to change states tPLH is the delay time before output changes from low to high tPHL is the delay time before output changes from high to low both tPLH & tPHL are measured between the 50% points on the input and output transitions Input 0 Output 0 tPHL tPLH
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50%

Power Dissipation
Static
I2R losses due to passive components, no input signal

Dynamic
I2R losses due to charging and discharging capacitances through resistances, due to input signal

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Speed-Power Product
Speed (propagation delay) and power consumption are the two most important performance parameters of a digital IC. A simple means for measuring and comparing the overall performance of an IC family is the speedpower product (the smaller, the better). For example, an IC has
an average propagation delay of 10 ns an average power dissipation of 5 mW the speed-power product = (10 ns) x (5 mW) = 50 picoJoules (pJ)
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Logic Family Tradeoffs

Looking for the best speed/power product tp and Pd are normally included in the data sheet for each device Older logic families are the worst CMOS is one of the best FPGAs use CMOS
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Comparison of Logic Families

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TTL - Example SN74LS00

Recommended operating conditions
Vcc supply voltage input voltages 5V 0.5 V VIH = 2V VIL = 0.8V
Input Range for 1 2.7 2.0

5 Volt

Electrical Characteristics
output voltage (worst case) max input currents
propagation delay noise margins Fan-out

Output Range for 1

VOH = 2.7V VOL = 0.5V IIH = 20A IIL = -0.4mA tpd = 15 nS

for a logic 0 = 0.3V for a logic 1 = 0.7V 20 TTL loads
Input Range for 0

0.8 0.5 0 Volt

Output Range for 0

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Fan-In
Number of input signals to a gate
Not an electrical property Function of the manufacturing process

NAND gate with a Fan-in of 8

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Fan-Out
A measure of the ability of the output of one gate to drive the input(s) of subsequent gates Usually specified as standard loads within a single family
e.g., an input to an inverter in the same family

May have to compute based on current drive requirements when mixing families
Although mixing families is not usually recommended

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Current Sourcing and Sinking

Current-source : the driving gate produces a outgoing current
VOH

Low
IIH

Current-sinking : the driving gate receives an incoming current

VOL
High IIL
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Fan-Out
An illustration of fan-out and the associated source and sink currents

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Worked Example
How many 74LS00 NAND gate inputs can be driven by a 74LS00 NAND gate outputs ?
Solution: Refer to data sheet of 74LS00, the maximum values of IOH = 0.4mA, IOL = 8mA, IIH = 20uA, and IIL = 0.4mA Hence, fan-out(high) = IOH(max) / IIH (max)=0.4mA/20uA=20 fan-out(low) = IOL(max) / IIL(max)=8mA/0.4mA=20, the overall fan-out = fan-out(high) or fan-out(low) whichever is lower. Hence, overall fan-out = 20 32

Gate Drive Capability: Fan-Out

A logic gate can supply a maximum output current
IOH(max), in the high state or IOL(max), in the low state

A logic gate requires a maximum input current

IIH(max), in the high state or IIL(max), in the low state

Ratio of output and input current decide how many logic gates can be driven by a logic gate
fan-out(high) = IOH(max) / IIH (max) fan-out(low) = IOL(max) / IIL(max) overall fan-out = fan-out(high) or fan-out(low) whichever is lower

A typical figure of fan-out is ten (10)

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Wired-AND
Open collector outputs connected together to a common pullup resistor Any collector can pull the signal line low Logically an AND gate

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Tri-State Logic
Both output transistors of totem-pole output are turned off Usually used to bus multiple signals on the same wire Gates not enabled present high-Z to bus and therefore do not interfere with other gates putting signals on the bus

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Tri-State Logic
Tri-state logic includes a switch at the output In the figure below, the three states are illustrated:
a) Logic High output b) Logic Low output c) High impedance (Hi-Z) output

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Electronic Combinational Logic

Within each of these families there is a large variety of different devices
We can break these into groups based on the number gates per device

Acronym SSI MSI LSI VLSI ULSI

Description Small-scale integration Medium-scale integration Large-scale integration Very large-scale integration

No Gates <12 12 100 100 1000 1000 1M

Example 4 NAND gates Adder 6800 68000 80486/80586

Ultra large scale integration > 1M

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SSI Devices
Each package contains a code identifying the package

N74LS00
Manufacturers Code N = National Semiconductors SN = Signetics Specification

Family L LS H

Member 00 = Quad 2 input NAND 02 = Quad 2 input Nor 04 = Hex Invertors 20 = Dual 4 Input NAND

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7400 Series History

1960s space program drove development of 7400 series
Consumed all available devices for internal flight computer $1000 / device (1960 dollars) 10:1 integration improvement over discrete transistors

1963 Minuteman missile forced 7400 into mass production

Drove pricing down to $25 / circuit (1963 dollars) 39

7400 Series Evolution

BJT storage time reduction by using a BC Schottky diode. Schottky diode has a Vfw=0.25V. When BC junction becomes forward biased Schottky diode will bypass base current.
C B

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Too Much of a Good Thing?

Families Packages Reliability options Speed grades Features Functions

An availability nightmare! >> 500K unique devices 41

Different Families Dont all Speak the Same Language

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Sometimes Things Get Lost or Added in the Translation*

Different families arent always on speaking terms with one another

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The World of TTL

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Success Drives Proliferation

2003

1960

New families introduced based on

Higher performance Lower power New features New signaling threshold

Spawned over 32 unique families!

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Success Drives Proliferation

Products introduced in the 1960 are near the end of their life cycle
Decreasing supplier base Increasing prices Not recommended for new designs

Products considered to be mature are about 2 decades into their life cycle
High-volume production Multiple suppliers Low prices

Newer products are only a few years into their life cycle
High performance High level of vendor and supplier support Newest technologies Higher prices

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Characteristics: TTL and MOS

Remember:
TTL stands for Transistor-Transistor Logic
uses BJTs

MOS stands for Metal Oxide Semiconductor

uses FETs

MOS can be classified into three sub-families:

PMOS (P-channel) NMOS (N-channel) CMOS (Complementary MOS, most common)

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TTL Circuit Operation

+Vcc 4K R1 1.6K R2 Q2 A B D Q 1 D2 I CQ1 1K R4 130 R3 Q 4

A 0 0
Y O/P Q 3

B 0 1 0 1

ICQ1 + + +

Q1 ON ON ON OFF

Q2 OFF OFF OFF ON

Q3 OFF OFF OFF ON

Q4 ON ON ON OFF

Y O/P 1 1 1 0

D3

1 1

Table explaining the operation of the TTL NAND gate circuit

A standard TTL NAND gate circuit

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Transistor-Transistor Logic Families

Transistor-Transistor Logic Families: 74L Low power 74H High speed 74S Schottky 74LS Low power Schottky 74AS Advanced Schottky 74ALS Advance Low power Schottky

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MOS Circuit Operation

+VDD
S

Q1
D D

O/P Q2

I/P 0 1

Q1 ON OFF

Q2 OFF ON

O/P 1 0

I/P

A CMOS inverter circuit

Table explaining the operation of the CMOS inverter circuit

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CMOS Logic Families

CMOS Logic Families
40xx/45xx 74C 74HC 74ACT Metal-gate CMOS TTL-compatible CMOS High speed CMOS Advanced CMOS -TTL compatible

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CMOS Family Evolution

CMOS Logic Trend: Reduction of dynamic losses (cross-conduction, capacitive charge/discharge cycles) by decreasing supply voltages:
12V5V 3.3V 2.5V 1.8V 1.5V

Reduction of IC power dissipation is the key to:

lower cost (packaging) higher integration improved reliability

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Comparison of Logic Families

vo

vi

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Comparison Logic Families

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Comparison of Logic Families

speed power product = a constant

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