Additional examples Verilog
Verilog: 2x1 MUX
Uses the conditional ?: operator
Software designers detest this operator Hardware designers revel in its beauty
Verilog: 4x1 MUX (Data Flow Style)
This is getting complicated! Need a way to specify a group of bits like w[0:3] Need a way to replace ?: with if then else
Vectored Signals in Verilog
Format is [MSB:LSB]
Signals can be grouped as bit vectors
The order of the bits is user determined W has 4 lines with the MSB = W[0] and the LSB = W[3] S has two lines with the MSB = S[1] and the LSB = S[0]
Hierarchical Design of a 16x1 MUX
s0 s1 w0 w3
Structural style Verilog
w4 w7
s2 s3
f w8 w11
w12 w15
The Verilog code for mux4x1 must be either in the same file as mux16x1, or in a separate file (called mux4x1.v) in the same directory as mux16x1
Hierarchical Design of a 4 to 16 Decoder
w0 w1 En w0 w1 y0 y1 y2 y3 y0 y1 y2 y3 y0 y1 y2 y3 y0 y1 y2 y3
w0 w1
y0 y1 y2 y3
y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15
Structural style Verilog
w2 w3 En
w0 w1 En
y0 y1 y2 y3
En w0 w1 En w0 w1 En
dec2to4 to be presented soon .
Behavioral Style in Verilog
Must be reg type when used as LHS in an always block
Sensitivity list: statements inside the always block are only executed when one or more signals in the list changes value
Always Blocks
All LHS signals must be variables type reg
The simulator registers the value and maintains it until the statements in the always block are executed again Statements are re-executed only when a signal in the sensitivity list changes value
The sensitivity list must include all signals on which the LHS variables depend in the always block
Order counts inside the always block!!!!
If else is called a procedural statement
All procedural statements must be inside an always block
Single vs Multiple Statements
In Verilog, all constructs permit only a single statement If you need > 1 statement inside a construct, use
begin end
You wont find much use for begin end most constructs really do include just a single statement
This is similar to Pascal syntax
Verilog is generally more like C though
Representation of Numbers
Numbers can be given as constants in
Binary (b) Octal (o) Hex (h) Decimal (d)
For numbers of a specified size:
TFAE:
12d2217 12h8A9 12o4251 12b100010101001
Numbers are 0-extended to the left, if necessary, to fill out the number of bits If the value exceeds the # of bits allocated, the extra bits are ignored!
#bits given in decimal
4x1 MUX: Behavioral Styles
Case Statement
Comparisons in a case statement are made bit by bit. No break statement needed first match executes and then case is exited. Use begin end if > 1 statement required in a case.
If not all cases are enumerated, make sure to use default case.
2 to 4 Decoder: Behavioral Style
4 to 2 Binary Encoder
Left extended by x to fill 2 bits
4 to 2 Priority Encoder
casex vs case
Case, Casez, Casex
Case treats each value 0, 1, x, and z literally
4b01xz only matches 4b01xz Example: 4b0110 does not match 4b01xx in a case
Casez treats 0, 1, and x literally
Casez treats z as a dont care Example: 4b0110 matches 4b01zz, but not 4b01xz
No match here
Casex treats 0 and 1 literally
Casex treats both x and z as dont cares Example: 4b0110 matches 4b01xx and also 4b01xz
