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EE 560 INTRODUCTION
Kenneth R. Laker, University of Pennsylvania
ORDERING OF TOPICS
Course Progress
System-Related Issues Reliability Manufacturability Testability Ps, Custom Logic VLSI Sub-systems Regular Structures ROMs, RAMs, PLAs Logic Circuits, Gates, Latches Two Transistor Locic Circuits (Inverters) static behavior dynamic behavior
Design
Implement
MOS Transistor, Capacitor and Interconnect Models
CMOS Fabrication
Kenneth R. Laker, University of Pennsylvania
INFORMATION SERVICE INDUSTRY TRENDS Video on Demand Speech Processing/Recognition Wireless/Cellular Data Communication Data Communication Consumer Electronics Mainframe Computers 1970 Personal Computers 1980 1990 Multimedia Applications Portable Computers Network Computers 2000
WHY MONOLITHIC INTEGRATION OF A LARGE NUMBER OF FUNCTIONS ON A SINGLE CHIP?
Less die area, compactness Less power consumption Less testing requirements at the system level Higher reliability, due to high quality on chip interconnect Higher speed, due to reduced interconnect length Significant cost savings
MIMIMUM FEATURE SIZE (m) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1975 1980 1985 1990 1995 0.1 m 2000 YEAR Complexity - #transistors double every two years. 400M traistors and 64 Gbit memories by 2005. Operating speed- double every two years. 5Gbits/sec 2002/03 and 10Gbits/sec 2003/04. Design - each transistor hand crafted to design automation and reuse of cells.
CLASSIFICATION OF DIGITAL CIRCUIT TYPES
DIGITAL CIRCUITS
STATIC CIRCUITS
DYNAMIC CIRCUITS
CLASSICAL CMOS
TRANSMISSION GATE CMOS
CVSL CIRCUITS
DOMINO LOGIC CIRCUITS
Kenneth R. Laker, University of Pennsylvania
NORA LOGIC CIRCUITS
TSPC LOGIC CIRCUITS
MOS TRANSISTORS
G G
S B G S B
B S p+ n-well p -substrate G D p+
S B G
S B
G
D n+
S n+
Kenneth R. Laker, University of Pennsylvania
S B G S B D
S B G S B
S p+
D p+
D n+
S n+
p-well n -substrate
Kenneth R. Laker, University of Pennsylvania
nMOS and pMOS SWITCH SYMBOLS AND IDEAL CHARACTERISTICS
SYMBOLS a N- SWITCH s N b s a b s=1 b 1 a
s=1
SWITCH CHARACTERISTICS Input Output
s=1
a s=0
0 a
b Srong 0
b Weak 1
"Strong 0" is 0 volts and "Strong 1" is VDD volts
a P- SWITCH s P b
Kenneth R. Laker, University of Pennsylvania
a s
Input a s=0 b 0 a
s=0
Output b Weak 0
a b s=1
1 a
b Strong 1
s=0
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OUTPUT LOGIC LEVELS OF N- AND P- SWITCHES
LEVEL Strong 1 Weak 1 Strong 0 Weak 0 High Impedance SYMBOL 1 1 0 0 Z SWITCH CONDITION P-SWITCH gate = 0, input = VDD N-SWITCH gate = 1, input = VDD N-SWITCH gate = 1, input = VSS P-SWITCH gate = 0, input = VSS N-SWITCH gate = 0 or P-SWITCH gate = 1
Kenneth R. Laker, University of Pennsylvania
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COMPLEMENTARY CMOS SWITCH
SYMBOLS -s a C s -s a s b a s b a s -s b b Input 0 a 1 a Output b Srong 0 b Strong 1 SWITCH CHARACTERISTICS
Kenneth R. Laker, University of Pennsylvania
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INVERTER TRUTH TABLE INPUT 0 1
1 (VDD)
G S
OUTPUT 1 0
input VDD output
G S
output
input
G
P
D D
N
S
input
G
D D
output
0 (VSS )
Kenneth R. Laker, University of Pennsylvania
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1 (VDD) P input N 0 (VSS ) output
RESOLUTION OF GATE OUTPUT LEVELS
Pull-Down Output 0 Z Z 0 Pull-Up Output Z 1 Z 1 Combined Output Desired 0 Operation 1 States Z CROSSBARRED
Kenneth R. Laker, University of Pennsylvania
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CONNECTION & BEHAVIOR OF SERIES N- AND P- SWITCHES
a s1 s2 N N b b s1 = 0 s2 = 0 a b s1 = 0 s2 = 1 a b s1 = 1 s2 = 0 a b s1 = 1 s2 = 1 a s1 = 0 s2 = 0 a s1 = 0 s2 = 1 a s1 = 1 s2 = 0 a s1 = 1 s2 = 1 a
F 0 s2 1 off 0 off
s1 1 off on
a s1 s2 P P b
F 0 s2 1 off 0 on
s1 1 off off
b
Kenneth R. Laker, University of Pennsylvania
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CONNECTION & BEHAVIOR OF PARALLEL N- AND P- SWITCHES
a
s1 = 0 s2 = 0 a s1 = 0 s2 = 1 a s1 = 1 s2 = 0 a s1 = 1 s2 = 1 a
F 0 s2 1 on 0 off
s1 1 on on
s1
s2
b
a
b s1 = 0 s2 = 0 a
P s2
b s1 = 0 s2 = 1 a
b s1 = 1 s2 = 0 a
b s1 = 1 s2 = 1 a
F 0 s2 1 on 0 on
s1 1 on off
s1
Kenneth R. Laker, University of Pennsylvania
2-INPUT CMOS NAND GATE
1 P P
(A.B) = (A+B) (A + B)
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A out 0 B 1 1 0 0 1 1 1 OR
output A N B N 0
(A.B) (AB) (A.B)
2-INPUT CMOS NAND GATE TRUTH TABLE OUTPUT 0 output B-INPUT B
Kenneth R. Laker, University of Pennsylvania
A-INPUT 1 0
U 1U
ZDZD
1U1U
Z ZD
U ZZU
D
1 1U
ZD ZD
0D 0D
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2-INPUT CMOS NOR GATE
NAND
P
1
P
OUT
1 P B A P output
(A+B) (A+B) = (A.B) (AB)
N
0
A out 0 B 1 (A + B) (A+B) 0 0 0 1 1 0 OR
Kenneth R. Laker, University of Pennsylvania
COMPOUND GATES
F = ((AB) + (CD))
N - Half
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F = ((AB) + (CD))
A B N N N N C D A B N N N N C D
P - Half
F = ((A+B) (C+D))
A P P B C P P D A P P B
Kenneth R. Laker, University of Pennsylvania
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F = ((AB) + (CD))
1 A P P B
D F
A B
N N 0
N N
C D
Kenneth R. Laker, University of Pennsylvania
2-INPUT MULTIPLEXER
-s s
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C s output
A s B -s s
A x x 0 1 B 0 1 x x s 0 0 1 1 -s s 1 1 0 0 output 0 (B) 1 (B) 0 (A) 1 (A) output = A.s + B .s
B
output
0 1s
C -s s
output
Key components in CMOS memory elements and data manipulation structures.
Kenneth R. Laker, University of Pennsylvania
CIRCUIT AND SYSTEM REPRESENTATIONS
COMPLEX DIGITAL SYSTEM can be SUCCESSIVELY SUB-DIVIDED in a HIERARCHIAL manner. Highly automated techniques exist for converting HIGH LEVEL DESCRIPTIONS OF SYSTEM BEHVIOR to a detailed implementation prescription to fabricate a CHIP. To do this, a set of ABSTRACTIONS have been developed to describe integrated electronic systems. Designs are represented in THREE distinct DOMAINS:
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1. Behavioral: what does the system do? 2. Structural: how are the elements connected together? 3. Physical: how is the structure to be built?
Each DESIGN DOMAIN can be specified at a variety of LEVELS of ABSTRACTION - Architectural - Algorithmic - Module or Functional Block - Logical - Switch - Circuit
Kenneth R. Laker, University of Pennsylvania
Higher Level
Lower Level
TYPICAL DESIGN ABSTRACTIONS IN DIGITAL VLSI DESIGN
21 22
SYSTEM
B A
0 1s
output
MODULE
VDD
S
CIRCUIT DEVICE
G D D
Vin
G S
Vout
1 m
G S n+
VSS
0.5 m
D n+
0.2 m
Kenneth R. Laker, University of Pennsylvania
CONSISTANT ABSTRACTIONS IN THREE DOMAINS
Behavioral Domain
Applications Operating Systems Programs Subroutines Instructions Transistors Transistors
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Structural Domain
PC RISC Procesor Adder, gates, registers
Circuit Abstraction Level
Logic Abstraction Level
Cells
Arcitectural Level
Modules Chips, Boards, Boxes
Kenneth R. Laker, University of Pennsylvania
Physical Domain
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BEHAVIORAL REPRESNTATION
Behavior may be specified by: 1. Boolean expressions 2. Tables of input/output values 3. Algoritythms written in high level computer languages 4. Algoritythms written in Harware Description Languages (HDLs) e.g. VHDL, Verilog highest level Algorithym -> lowest level Registers and communications -> ..... -> Boolean expressions
GOAL OF MODERN DESIGN SYSTEMS: Convert spec at HIGHEST LEVEL possible into a system design in MINIMUM TIME and with MAXIMUM LIKLIHOOD that the design will PERFORM AS DESIRED.
Kenneth R. Laker, University of Pennsylvania
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Example 1-1: pp 10, 2nd Ed
Design a one-bit binary adder circuit using 1 m n-well CMOS technology. The specificaions are: 1. Propogation Delay Times of SUM & CARRY_OUT signals: 1.2 ns 2. Transition Delay Times of SUM & CARRY_OUT signals: 1.2 ns 3. Circuit Die Area: 1500 m2 4. Dynamic Power Dissipation (@ VDD = 5 V and fmax = 20 MHz): 1 mW
Kenneth R. Laker, University of Pennsylvania
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COST OF AN INTEGRATED CIRCUIT
FIXED COST: engineering cost, research and development, indirect costs. VARIABLE COST: die cost, test cost, package cost
TYPICAL VLSI DESIGN FLOW System Requirements
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Architecture Definition and Logic Design Logic Diagram/Description FAIL Design Verification VLSI Design and Layout Verilog Technology Design Rules Device Models Design Rule Check Circuit Sim (SPICE)
FAIL
Design Verification PASS Mask Generation Silicon Processing
Wafer Testing, Packaging, Reliability Qualification
Kenneth R. Laker, University of Pennsylvania
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START: Boolean description of binary adder circuit: A B C FULL ADDER sum_out carry_out A B C sum_out carry_out 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1
DEFINE: Input Variables: addends: A, B carry-in: C Output Variables: sum_out, carry_out BOOLEAN FUNCTION:
sum_out = A + B + C = ABC + ABC + ABC + ACB carry_out = AB + AC + BC
Kenneth R. Laker, University of Pennsylvania
BOOLEAN FUNCTION: SUM_OUT = A + B + C = ABC + ABC + ABC + ACB CARRY_OUT = AB + AC + BC
A B C carry_out
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LOGIC DIAGRAM
A B C sum_out
SUM_OUT= ABC + (A + B + C) CARRY_OUT (use of carry_out to realize sum_out reduces circuit complexity and chip area)
Kenneth R. Laker, University of Pennsylvania
GATE LEVEL SCHEMATIC OF ONE-BIT FULL ADDER CIRCUIT
A B C A B C
carry_out
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sum_out A A B C A C B C VDD
A carry_out
A B C VDD
A A B B
A
sum _out
B C
Kenneth R. Laker, University of Pennsylvania
TRANSISTOR LEVEL SCHEMATIC
A A B C A B
A carry_out
VDD A B C A VDD
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C A B
A
sum_out
B C
COLOR LEGEND n-Well p-Well n+ Poly p+ S_O VDD VDD
C_O A B C
Gate Oxide Field Oxide Metal 1 Metal 2 Metal 3 Contact/via
Kenneth R. Laker, University of Pennsylvania
GND
GND
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COLOR LEGEND n-Well p-Well n+ Poly p+ S_O VDD VDD
C_O A B C
Gate Oxide Field Oxide Metal 1 Metal 2 Metal 3 Contact/via
GND
GND
Layout with W/L = 2 m/0.8 m Area 21 m x 54 m = 1134 m2
Kenneth R. Laker, University of Pennsylvania
SPECIFICATIONS: 1. Propogation Delay Times of SUM & CARRY_OUT signals: 1.2 ns 2. Transition Delay Times of SUM & CARRY_OUT signals: 1.2 ns 3. Circuit Die Area: 1500 m2 4. Dynamic Power Dissipation (@ VDD = 5 V and fmax = 20 MHz): 1 mW
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Layout with W/L = 2 m/0.8 m
Voltage (V) A = 0, B = 1 5.0 3.0 1.0 -1.0 20 22 24 SUM C (carry_in) tPLH tPLH < 1.2 ns tPLH = 2 ns > 1.2 ns tPHL 26 28 30 Time (ns)
Modified Layout Required
1. Increase W/L's of transistors 2. Consider more compact placement of transistors and reduce interconnect in critcal paths
Kenneth R. Laker, University of Pennsylvania
System Requirements Architecture Definition and Logic Design Design Verification VLSI Design and Layout Verilog Technology Design Rules Device Models Design Rule Check Circuit Sim (SPICE)
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FAIL
FAIL
Design Verification PASS Mask Generation Silicon Processing
Wafer Testing, Packaging, Reliability Qualification
Kenneth R. Laker, University of Pennsylvania
