UNIT V

MEMORY AND PROGRAMMABLE LOGIC

• RAM
• Memory Decoding
• Error Detection and Correction
• ROM
• Programmable Logic Array
• Programmable Array Logic
• Sequential Programmable Devices

2
 Introduction
• A memory unit is a collection of storage cells
with associated circuits needed to transfer
information in and out of the device.
• The binary information is transferred for storage
and from which information is available when
needed for processing.
• When data processing takes place, information
from the memory is transferred to selected
registers in the processing unit.
• Intermediate and final results obtained in the
processing unit are transferred back to be stored
in memory.

3
• The smallest unit of binary data is the bit.
• An 8- bit unit called a byte or in multiples of 8-bit
units.
• The byte can be split into two 4-bit units that are
called nibbles.
• A complete unit of information is called a word
and generally consists of one or more bytes.
• Some memories store data in 9-bit groups; a 9-bit
group consists of a byte plus a parity bit.

4
 Basic Semiconductor Memory Array
• Each storage element in a memory can retain either a 1 or
a 0 and is called a cell.
• Memories are made up of arrays of cells,
• Each block in the memory array represents one storage cell,
and its location can be identified by specifying a row and a
column.

5
 Memory Address and Capacity
• The location of a unit of data in a memory array is called its
address.
• The capacity of a memory is the total number of data units
that can be stored.

6
 Basic Memory Operations
• Since a memory stores binary data, data must be put
into the memory and data must be copied from the
memory when needed.
• The write operation puts data into a specified address
in the memory, and the read operation copies data out
of a specified address in the memory.
• The addressing operation, which is part of both the
write and the read operations, selects the specified
memory address.
• Data units go into the memory during a write operation
and come out of the memory during a read operation
on a set of lines called the data bus.
• For a write or a read operation, an address is selected
by placing a binary code representing the desired
address on a set of lines called the address bus.
7
• A 15- bit address code can select 32,768 locations (215)
in the memory; a 16-bit address code can select 65,536
locations (216) in the memory and so on.
• In personal computers a 32-bit address bus can select
4,294,967,296 locations (232), expressed as 4GB

Block diagram of memory operation

8
Write Operation

9
Read Operation

10
 Classification of Memories
• Random-Access Memory (RAM)
• RAM (random-access memory) is a type of memory in
which all addresses are accessible in an equal amount
of time and can be selected in any order for a read or
write operation. All RAMs have both read and write
capability. Because RAMs lose stored data when the
power is turned off, they are volatile memories.
• Read-Only Memory (ROM)
• ROM (read-only memory) is a type of memory in which
data are stored permanently or semi permanently.
Data can be read from a ROM, but there is no write
operation as in the RAM. The ROM, like the RAM, is a
random-access memory but the term RAM traditionally
means a random-access read/write memory. Because
ROMs retain stored data even if power is turned off,
they are nonvolatile memories.
11
12
 RAM
• RAMs are read/write memories
• When a data unit is written into a given address,
previously stored data is replaced by the new data unit.
• When a data unit is read from a given address in the
RAM, the data unit remains stored and is not erased by
the read operation.
• This nondestructive read operation can be viewed as
copying the content of an address while leaving the
content intact.
• A RAM is typically used for short-term data storage
because it cannot retain stored data when power is
turned off.

13
• Static RAM (SRAM)
Flip-flops as storage elements and can therefore store
data indefinitely as long as dc power is applied.
• Dynamic RAM (DRAM).
Capacitors as storage elements and cannot retain data
very long without the capacitors being recharged by a
process called refreshing.
• Both SRAMs and DRAMs will lose stored data when dc
power is removed and, therefore, are classified as
volatile memories.
• Data can be read much faster from SRAMs than from
DRAMs.
• However, DRAMs can store much more data than
SRAMs for a given physical size and cost because the
DRAM cell is much simpler, and more cells can be
crammed into a given chip area than in the SRAM.
14
 Static RAM (SRAM)
• All static RAMs are characterized by flip-flop
memory cells.
• As long as dc power is applied to a static memory
cell, it can retain a 1 or 0 state indefinitely.
• If power is removed, the stored data bit is lost.
• The cell is selected by an active level on the
Select line and a data bit (1 or 0) is written into
the cell by placing it on the Data in line.
• A data bit is read by taking it off the Data out line.

15
 Basic Static Memory Cell Array
• The memory cells in a SRAM are organized in rows and
columns.
• All the cells in a row share the same Row Select line.
• Each set of Data in and Data out lines go to each cell in a
given column and are connected to a single data line that
serves as both an input and output (Data I/O) through the
data input and data output buffers.
• SRAM chips can be organized in single bits, nibbles (4 bits),
bytes (8 bits), or multiple bytes (16, 24, 32 bits, etc.).
• 256 rows and 128 columns, each with
8 bits.
• There are actually 215 = 32,768
addresses and each address contains
8 bits.
• The capacity is 32,768 bytes (typically
expressed as 32 Kbytes).
16
Operation

Memory block diagram

17
Read
• In the READ mode, the write enable input, WE‘ is HIGH
and the output enable, OE‗ is LOW.
• The input tri state buffers are disabled by gate G1, and
the column output tri state buffers are enabled by gate
G2.
• Therefore, the eight data bits from the selected
address are routed through the column I/O to the data
lines (I/O1 through I/O7), which are acting as data
output lines.
Write
• In the WRITE mode, WE‘ is LOW and OE‘ is HIGH.
• The input buffers are enabled by gate G1, and the
output buffers are disabled by gate G2.
• Therefore the eight input data bits on the data lines are
routed through the input data control and the column
I/O to the selected address and stored.
18
• Read cycle time, tRC.
• Address access time, tAQ
• Chip enable access time, tEQ
• Output enable access time, tGQ
19
• Write cycle time, tWC.
• Address setup time, t s(A).
• Valid data time, tWD
• Data hold time, t h(D)
20
 Memory Decoding
• Decoding circuits are needed to select the
memory word specified by the input address.
Internal Construction
• A RAM of m words and n bits per word consists of
m * n binary storage cells and associated
decoding circuits for selecting individual words

21
Diagram of a 4 * 4 RAM

22
• A memory with 2k words of n bits per word requires k
address lines that go into a k * 2k decoder.
• Each one of the decoder outputs selects one word of n bits
for reading or writing.
Coincident Decoding
• A decoder with k inputs and 2k outputs requires 2k AND
gates with k inputs per gate.
• The total number of gates and the number of inputs per
gate can be reduced by employing two decoders in a
two‐dimensional selection scheme.
• The basic idea in two‐dimensional decoding is to arrange
the memory cells in an array that is close as possible to
square.
• In this configuration, two k /2‐input decoders are used
instead of one k ‐input decoder.
• One decoder performs the row selection and the other the
column selection in a two‐dimensional matrix
configuration.
23
Two‐dimensional decoding structure for a 1K‐word memory
24
Address Multiplexing
• DRAMs typically have four times the density of SRAMs.
• This allows four times as much memory capacity to be
placed on a given size of chip.
• Because of their large capacity, the address decoding of
DRAMs is arranged in a two‐dimensional array, and
larger memories often have multiple arrays.
• To reduce the number of pins in the IC package,
designers utilize address multiplexing whereby one set
of address input pins accommodates the address
components.
• In a two‐dimensional array, the address is applied in
two parts at different times, with the row address first
and the column address second.
• Since the same set of pins is used for both parts of the
address, the size of the package is decreased
significantly.
25
Address multiplexing for a 64K DRAM

26
 Error Detection and Correction
• The most common error detection scheme is the parity bit.
• A parity bit is generated and stored along with the data word
in memory.
• The parity of the word is checked after reading it from
memory.
• The data word is accepted if the parity of the bits read out is
correct.
• If not, an error is detected, but it cannot be corrected.
• An error‐correcting code generates multiple parity check bits
that are stored with the data word in memory.
• When the word is read back from memory, the associated
parity bits are also read from memory and compared with a
new set of check bits generated from the data that have been
read.
• If the check bits are correct, no error has occurred.
• If the check bits do not match the stored parity, they generate
a unique pattern, called a syndrome, that can be used to
identify the bit that is in error. 27
Hamming Code
• k parity bits are added to an n‐bit data word,
forming a new word of n + k bits.
• The bit positions are numbered in sequence
from 1 to n + k.
• Those positions numbered as a power of 2 are
reserved for the parity bits.
• The remaining bits are the data bits.
• The code can be used with words of any
length

28
 Consider, for example, the 8‐bit data word
11000100. We include 4 parity bits with the
8‐bit word and arrange the 12 bits as follows
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0
Each parity bit is calculated as follows
241  0010
0100
0001
8 1000
35  0011
0101
9  1001
65  0110
0101
10  1010
7  0111
11  1011
109
12 1001
1010
1100
12  1100
11  1011
111011 29
 • Substituting the 4 P bits in their proper
positions, we obtain the 12‐bitcomposite
word stored in memory

• The 4 check bits are evaluated as follows

4218 
1000
0100
0010
0001
953  1001
0101
0011
1065  0110
1010
0101
117  0111
1011
12129 1100
10 1100
1001
1010
11  1011
111011 30
• IF result, C = C8C4C2C1 = 0000, indicates that
no error has occurred.
• However, if C ≠ 0, then the 4‐bit binary
number formed by the check bits gives the
position of the erroneous bit.
• For example, consider the following three
cases:

31
C1 = XOR of bits (1, 3, 5, 7, 9, 11) =0=1=1
C2 = XOR of bits (2, 3, 6, 7, 10, 11) =0=0=0
C4 = XOR of bits (4, 5, 6, 7, 12) =0=0=1
C8 = XOR of bits (8, 9, 10, 11, 12) =0=0=0

32
• The Hamming code is received as 101101101. Correct it if any
errors. There are four parity bits and odd parity is used.
Received data is 101101101
1 2 3 4 5 6 7 8 9
1 0 1 1 0 1 1 0 1
P1 P2 P4 P8
Odd parity is used
C1= XOR of bits (1, 3, 5, 7, 9) = 1, 1, 0, 1, 1 error since even 1s 1
C2= XOR of bits (2, 3, 6, 7) = 0, 1, 1, 1  odd No of 1s  0
C4= XOR of bits (4, 5, 6, 7) = 1, 0, 1, 1  odd No of 1s  0
C8= XOR of bits (8, 9) = 0, 1  odd No of 1s 0

C= C8 C4 C2 C1 = 0001  Bit no 1 has error

Correct code is  0 0 11 0 1 101
33
 ROM
• A ROM contains permanently or semi-permanently
stored data, which can be read from the memory but
either cannot be changed at all or cannot be changed
without specialization equipment.
• A ROM stores data that are used repeatedly in system
applications, such as tables, conversions, or
programmed instructions for system initialization and
operation.
• ROMs retain stored data when the power is OFF and
are therefore nonvolatile memories.
• The ROMs are classified as follows:
i. Masked ROM (ROM)
ii. Programmed ROM (PROM)
iii. Erasable PROM (EPROM)
iv. Electrically Erasable PROM (EEPROM)
34
Masked ROM
• The mask ROM is usually referred to simply as a ROM.
• It is permanently programmed during the manufacturing
process to provide widely used standard functions, such as
popular conversions, or to provide user-specified functions.
• Once the memory is programmed, it cannot be changed.
• Most IC ROMs utilize the presence or absence of a
transistor connection at a row/column junction to
represent a 1 or a 0.

ROM Cells
35
PROM (Programmable Read-Only Memory)
• It comes from the manufacturer unprogrammed and
are custom programmed in the field to meet the user‘s
needs.
• A PROM uses some type of fusing process to store bits,
in which a memory link is burned open or left intact to
represent a 0 or a 1. The fusing process is irreversible;
once a PROM is programmed, it cannot be changed.
• The fusible links are manufactured into the PROM
between the source of each cell's transistor and its
column line. In the programming process, a sufficient
current is injected through the fusible link to bum it
open to create a stored 0. The link is left intact for a
stored 1.
Metal links nichrome
Silicon links polycrystalline silicon
Shorted junction
36
PROM array with fusible links
37
EPROM (Erasable Programmable ROM)
• An EPROM is an erasable PROM. Unlike an
ordinary PROM, an EPROM can be reprogrammed
if an existing program in the memory array is
erased first.
• An EPROM uses an NMOSFET array with an
isolated-gate structure. The isolated transistor
gate has no electrical connections and can store
an electrical charge for indefinite periods of time.
• Two basic types of erasable PROMs are the
ultraviolet erasable PROM (UV EPROM) and the
electrically erasable PROM (EEPROM).
38
S.No RAM ROM
RAMs have both read
ROMs have only read
1 and write
operation.
capability.
RAMs are volatile ROMs are non-volatile
2
memories. memories.
They lose stored data They retain stored data
3 when the even if power is
power is turned OFF. turned off.
RAMs are available in
RAMs are available in both
both
4 bipolar and
bipolar and MOS
MOS technologies.
technologies.
Types: SRAM, DRAM,
5 Types: PROM, EPROM.
EEPROM
39
S.No Static RAM Dynamic RAM
It contains less
It contains more memory cells
1 memory cells per unit
per unit area.
area.
Its access time is less, Its access time is greater than
2
hence faster memories. static RAM
It stores the data as a charge on
It consists of number
the capacitor. It consists of
3 of flip-flops. Each flip-
MOSFET and capacitor for each
flop stores one bit.
cell.
Refreshing circuitry is required
to maintain the charge on the
Refreshing circuitry is capacitors every time after every
4
not required. few milliseconds. Extra hardware
is
required to control refreshing.
5 Cost is more Cost is less.
40
 One-
Memory Non- High In-system
Transistor
type Volatile Density writability
cell
SRAM No No No Yes
DRAM No Yes Yes Yes
ROM Yes Yes Yes No
EPROM Yes Yes Yes No
EEPROM Yes No No Yes

41
 ROM block diagram

32 words
of 8 bits each
32 * 8 = 256
internal connections

Internal logic of a 32 : 8 ROM

42
• The 256 intersections are programmable
• The truth table shows the five inputs under which are
listed all 32 addresses.
• Each address stores a word of 8 bits, which is listed in
the outputs columns.

A7, A6,
A5,A3,
A4,A2,
andand
A1A0are
Fuses to be BLOWN
marked with a X

43
 X X X X X
X X X X
X X X X
X X X X

Programming the ROM according to Table

44
Combinational Circuit Implementation
• A decoder generates the 2k minterms of the k input
variables.
• By inserting OR gates to sum the minterms of Boolean
functions, we were able to generate any desired
combinational circuit.
• The ROM is essentially a device that includes both the
decoder and the OR gates within a single device to form a
minterm generator.
• By choosing connections for those minterms which are
included in the function, the ROM outputs can be
programmed to represent the Boolean functions of the
output variables in a combinational circuit.
• The internal operation of a ROM can be interpreted in two
ways.
• The first interpretation is that of a memory unit that
contains a fixed pattern of stored words.
• The second interpretation is that of a unit which
implements a combinational circuit. 45
• Design a combinational circuit using a ROM,
that accepts a 3-bit number and generates an
output binary number equal to the square of
the given input number B0 is always equal to input A0
B1 is always 0

Truth Table for square of the given input number

46
The minimum size of ROM needed must have
three inputs and four outputs.
Three inputs specify eight words, so the ROM
must be of size 8 * 4.

47
Design a switching circuit that converts a 4bit
binary code into a 4 bit Gray code using ROM array
Decimal Binary Input Gray Output
Equivalent B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0 48
 mo 0000
X 0001
X X 0011
X 0010
X X 0110
B3 X X X 0111
X X
B2 X
4 X 16
B1 X X
Decoder X X X
B0 X X X X
X X
X X
X X X
X X
m15 X
4 bit Binary Code into a
4 bit Gray Code using ROM array
G3 G2 G1 G0
49
Implement the following function with ROM.
F1 (A,B,C)=∑m(0,3,7) and f2 (A,B,C)=∑m(1,5,7)
A2 A1 A0 f1 f2
0 0 0 1 0
0 0 1 0 1
0 1 0 0 0
0 1 1 1 0
1 0 0 0 0
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1
ROM truth table and Block diagram
50
51
 Programmable Logic Devices - PLDs
• PLD is an integrated circuit with programmable gates divided into
an AND array and an OR array to provide an AND-OR sum of
product implementation.
• The PLD‘s can be reprogrammed in few seconds and hence gives
more flexibility to experiment with designs.
• Reprogramming feature of PLDs also makes it possible to accept
changes/modifications in the previously design circuits.
• The advantages of using programmable logic devices are:
1. Reduced space requirements.
2. Reduced power requirements.
3. Design security.
4. Compact circuitry.
5. Short design cycle.
6. Low development cost.
7. Higher switching speed.
8. Low production cost for large-quantity production.

52
• According to architecture, complexity and
flexibility in programming in PLD‘s are
classified as

• PROM : Programmable Read Only memories,

• PLA : Programmable Logic Arrays,
• PAL : Programmable Logic Array,
• FPGA : Field Programmable Gate Arrays,
• CPLD : Complex Programmable Logic Devices.

53
Programmable Read-Only Memory (PROM)

Programmable Logic Array (PLA)

Programmable Array Logic (PAL)

54
Programmable Arrays
• All PLDs consists of programmable arrays.
• A programmable array is essentially a grid of
conductors that form rows and columns with a
fusible link at each cross point.
• Arrays can be either fixed or programmable.
The OR Array
It consists of an array of OR gates connected to a
programmable matrix with fusible links at each
cross point of a row and column
The AND Array
This type of array consists of AND gates
connected to a programmable matrix with fusible
links at each cross points
55
An example
of a basic
programmable
OR array

An example
of a basic
programmable
AND array

56
 Programmable Logic Array
• The PLA is similar to the PROM in concept except that
the PLA does not provide full coding of the variables
and does not generate all the minterms.
• The decoder is replaced by an array of AND gates that
can be programmed to generate any product term of
the input variables.
• The product term are then connected to OR gates to
provide the sum of products for the required Boolean
functions.
• The AND gates and OR gates inside the PLA are initially
fabricated with fuses among them.
• The specific boolean functions are implemented in sum
of products form by blowing the appropriate fuses and
leaving the desired connections.
57
PLA block diagram

58
 Implement the combinational circuit with a PLA
having 3 inputs, 4 product terms and 2 outputs
for the functions.
F1 (A, B, C) = Σm (0, 1, 2, 4)
F2 (A, B, C) = Σm (0, 5, 6, 7)
Truth table for the given functions
A B C F1 F2
0 0 0 1 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 0 1 59
K-map Simplification

With this simplification, total number of product

term is 6. But we require only 4 product terms.
Therefore find out F1‘ and F2‘.

Now select, F1‘ and F2, the product terms are AC,
AB, BC and A‘B‘C‘ 60
PLA Program table

61
PLA Diagram

62
Implement the combinational circuit with a PLA
having 3 inputs, 4 product terms and 2 outputs
for the functions.
F1 (A, B, C) = Σm (3, 5, 6, 7)
F2 (A, B, C) = Σm (0, 2, 4, 7)
Truth table for the given functions
A B C F1 F2
0 0 0 0 1
0 0 1 0 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 63
K-map Simplification

With this simplification, total number of product term is

6. But we require only 4 product terms. Therefore find
out F1‘ and F2‘.

Now select, F1‘ and F2, the product terms are B’C’,
A’C’, A’B’ and ABC.
64
 PLA Program table

Inputs Outputs
Product
term A B C F1(C) F2 (T)

B'C' 1 - 0 0 1 1

A'C' 2 0 - 0 1 1

A'B' 3 0 0 - 1 -

ABC 4 1 1 1 - 1

65
PLA Diagram

66
 Design a BCD to Excess-3 code converter and
implement using suitable PLA.
BCD code Excess-3 code
Decimal
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
67
 K-map Simplification

The product terms are

B3, B2B0, B2B1, B2B1’B0’, B2’B0, B2’B1, B1’B0’, B1B0, B0’
68
 PLA Program table
Inputs Outputs
Product
E3( E2 E1 E0
Terms B3 B2 B1 B0
T) (T) (T) (T)
B3 1 1 - - - 1 - - -
B2B0 2 - 1 - 1 1 - - -
B2B1 3 - 1 1 - 1 - - -
B2B1’B0’ 4 - 1 0 0 - 1 - -
B2’B0 5 - 0 - 1 - 1 - -
B2’B1 6 - 0 1 - - 1 - -
B1’B0’ 7 - - 0 0 - - 1 -
B1B0 8 - - 1 1 - - 1 -
B0’ 9 - - - 0 - - - 1

69
PLA Diagram

70
 Programmable Array Logic
• The PAL is a programmable logic device with a
fixed OR array and a programmable AND array.
• Because only the AND gates are programmable,
the PAL is easier to program than, but is not as
flexible as, the PLA.
• A typical PAL with four inputs and four outputs.
• Each input has a buffer–inverter gate, and each
output is generated by a fixed OR gate.
• There are four sections in the unit, each
composed of an AND–OR array that is three
wide, the term used to indicate that there are
three programmable AND gates in each section
and one fixed OR gate.
71
72
• In designing with a PAL, the Boolean functions
must be simplified to fit into each section.
• Unlike the situation with a PLA, a product term
cannot be shared among two or more OR gates.
• Therefore, each function can be simplified by
itself, without regard to common product terms.
• The number of product terms in each section is
fixed, and if the number of terms in the function
is too large, it may be necessary to use two
sections to implement one Boolean function.

73
 Implement the following function with PAL.
w (A,B,C,D)= ∑m(2,12,13)
x(A,B,C,D)=∑m(7,8,9,10,11,12,13,14,15)
y(A,B,C,D)= ∑m(0,2,3,4,5,6,7,8,10,11,15)
z(A,B,C,D)=∑m(1,2,8,12,13)
Simplification of the given functions using K-map will gives the reduced expression.

74
75
76
Comparison between PROM, PLA, and PAL
S.No PROM PLA PAL
AND array is fixed Both AND and OR array is fixed and
1 and OR array is OR n arrays are AND array is
programmable programmable programmable
Cheaper and simpler Costliest and
2 Cheaper and simpler
to use complex
AND array can be
AND array can be
All minterms are programmed to
3 programmed to get
decoded get desired
desired minterms
minterms
Only Boolean Any Boolean Any Boolean
functions in functions in SOP functions in SOP
4 standard SOP form form can be form can be
can be implemented implemented implemented using
using PROM using PLA PLA
77
 Sequential Programmable Devices
• Digital systems are designed with flip‐flops and gates.
Since the combinational PLD consists of only gates, it is
necessary to include external flip‐flops when they are
used in the design.
• Sequential programmable devices include both gates
and flip‐flops.
• In this way, the device can be programmed to perform
a variety of sequential‐circuit functions.
• There are three major types of sequential
programming devices namely
1. Sequential (or simple) programmable logic device
(SPLD)
2. Complex programmable logic device (CPLD)
3. Field‐programmable gate array (FPGA)

78
Sequential (or simple) programmable logic device
(SPLD)
• Field‐programmable logic sequencer (FPLS)

• Each section of an SPLD is called a macrocell

• It is a circuit that contains a sum‐of‐products
combinational logic function and an optional
flip‐flop

79
Basic Macrocell logic

80
Complex programmable logic device (CPLD)

81
Field‐programmable gate array (FPGA)

82
End of Unit V

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