CMOS ANALOG IC DESIGN

(22PE0EC08)
IV Year I Sem
Course Objectives:
1. To understand most important building blocks of all CMOS Analog ICs.
2. To study the basic principle of operation, the circuit choices and the trade-offs involved in the MOS
transistor level design common to all Analog CMOS ICs.
3. To understand specific design issues related to single and multistage voltage, current and differential
amplifiers, their output and impedance issues, bandwidth, feedback and stability.
4. To understand the design of differential amplifiers, current amplifiers and OPAMPs.

Course Outcomes:
1. Design basic building blocks of CMOS Analog ICs.
2. Carry out the design of single and two stage operational amplifiers and voltage references.
3. Determine the device dimensions of each MOSFETs involved.
4. Design various amplifiers like differential, current and operational amplifiers.

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Syllabus:

UNIT-I
MOS Devices and Modeling
The MOS Transistor, Passive Components- Capacitor & Resistor, Integrated circuit Layout, CMOS Device
Modeling-Simple MOS Large – Signal Model, Other Model Parameters, Small Signal Model for the MOS
Transistor.

UNIT-II
Analog CMOS Sub-Circuits
MOS Switch, MOS Diode, MOS Active Resistor, Current Sinks and Sources, Current Mirrors Current
mirror with Beta Helper, Degeneration, Current and Voltage References, Band gap Reference.

UNIT-III
CMOS Amplifiers
Inverters, Differential Amplifiers, Cascade Amplifiers, Current Amplifiers, Output Amplifiers, High Gain
Amplifiers Architectures.

UNIT-IV
CMOS Operational Amplifiers
Design of CMOS Op-Amps, Compensation of Op-Amps, Design of Two-Stage Op-Amps, Power-Supply,
Rejection Ratio of Two – Stage Op-Amps, Cascade Op-Amps, Measurement Techniques of OP-Amp.

UNIT-V
Comparators
Characterization of Comparator, Two-Stage, Open – Loop Comparators, Other Open – Loop Comparators,
Improving the Performance of Open – Loop Comparators, Discrete – Time Comparators.

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Text Books:

1. Philip E. Allenand Douglas, R. Holberg – CMOS Analog Circuit Design, Oxford University Press,
International Second Edition/Indian Edition,2010.
2. Paul R. Gray, Paul J.Hurst, S.Lewis and R.G.Meyer–Analysis and Design of Analog Integrated
Circuits, 5th edition, Wiley India,2010.

Reference Books:
1. David A.Johns, Ken Martin – Analog Integrated Circuit Design, Wiley Student Edn, 2013.
2. Behzad Razavi– Design of Analog CMOS Integrated Circuits, TMH.
3. Baker, Liand Boyce-CMOS: Circuit Design, Layout and Simulation, PHI.

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 UNIT - I

MOS Devices and Modeling

The MOS Transistor, Passive Components- Capacitor & Resistor, Integrated circuit Layout, CMOS Device
Modeling-Simple MOS Large – Signal Model, Other Model Parameters, Small Signal Model for the MOS
Transistor.

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Introduction
➢ CMOS Analog IC Design is the discipline focused on creating analog integrated circuits using
CMOS (complementary metal-oxide-semiconductor) technology.
➢ It is the dominant process for fabricating modern electronic systems such as computers, smartphones,
and embedded devices.
➢ CMOS technology utilizes both p-channel (PMOS) and n-channel (NMOS) field-effect transistors,
allowing for efficient, high-density integration of analog and digital functions on a single chip.

Why CMOS for Analog IC Design?

➢ CMOS technology offers low power consumption, high noise immunity, and scalability, making it
ideal for both digital and analog circuits.

➢ The ongoing scaling of CMOS device geometries (as described by Moore’s law) enables increasingly
complex and compact circuits, supporting the integration of analog functions with digital processing
on the same chip.

Importance of Analog Design

➢ Analog circuits process signals that vary continuously with time (like voltages or currents), which is
essential for interfacing with the physical world (e.g., audio, sensors, radio signals).

➢ While digital circuits dominate computation, analog circuits remain crucial for signal amplification,
filtering, and conversion between analog and digital domains.

Basic CMOS Analog IC Design Flow

1. Specification: Define the required performance and functions.
2. Hand Calculations & Analytical Models: Initial design using simplified equations.
3. Simulation: Use tools like SPICE to model and refine circuit behavior.
4. Layout: Physically design the circuit for fabrication.
5. Fabrication: Manufacture the chip using CMOS processes.
6. Testing & Verification: Measure performance and iterate if necessary

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Challenges and Trends

➢ As supply voltages decrease and device dimensions shrink, analog design techniques must adapt to
maintain performance and reliability.
➢ Accurate modeling and simulation are increasingly important due to the complexity and sensitivity
of modern analog circuits.

Moore’s Law

➢ Moore’s Law is an observation made by Gordon E. Moore, co-founder of Intel, in 1965, stating that
the number of transistors on a microchip doubles approximately every two years while the cost
increases minimally.

➢ This implies that computing power grows exponentially, making computers faster, smaller, and
cheaper over time.

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PN Junction Diode:
A PN junction diode is a fundamental semiconductor device formed by joining a p-type and an n-type
semiconductor material, creating a junction with unique electrical properties.
Structure and Formation:

• The p-type semiconductor is doped with acceptor impurities, resulting in an excess of holes (positive
charge carriers).
• The n-type semiconductor is doped with donor impurities, resulting in an excess of electrons
(negative charge carriers).
• When these two materials are fused, electrons from the n-side diffuse into the p-side and recombine
with holes, and holes from the p-side diffuse into the n-side.
• This diffusion leads to a region near the junction called the depletion region, which is depleted of
free charge carriers but contains immobile, charged ions (positive ions on the n-side and negative
ions on the p-side).
• The depletion region creates an electric field and a potential barrier (built-in potential) that opposes
further diffusion of charge carriers.

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Working Principle:
The diode allows current to flow primarily in one direction due to the behavior of the depletion region under
different biasing conditions:

➢ Zero Bias (No External Voltage):

• The diode is in equilibrium.
• The potential barrier prevents the flow of current.
• No net movement of charge carriers occurs across the junction
➢ Forward Bias:
• The p-type is connected to the positive terminal of the external voltage, and the n-type to the
negative terminal.
• This reduces the width of the depletion region and lowers the potential barrier.
• When the applied voltage exceeds a threshold (about 0.7 V for silicon and 0.3 V for
germanium diodes), electrons can cross the junction, resulting in current flow.
• The current increases exponentially with voltage, producing a nonlinear I-V characteristic.
• Beyond the threshold, the diode behaves almost like a closed switch, allowing significant
current flow.
➢ Reverse Bias:
• The p-type is connected to the negative terminal, and the n-type to the positive terminal.
• This increases the width of the depletion region and raises the potential barrier.
• Only a tiny reverse saturation current flows due to minority carriers.
• If the reverse voltage exceeds a critical breakdown voltage, the diode may conduct heavily
and possibly be damaged unless it is a special diode designed for this (like a Zener diode).

Characteristics:

• The diode exhibits asymmetric conduction: it conducts current easily in forward bias and blocks
current in reverse bias.
• The I-V characteristic curve is nonlinear and exponential in forward bias.
• The depletion region acts as a barrier controlling charge carrier flow.

Applications:

• Rectification: converting AC to DC.

• Switching: controlling current flow in circuits.
• Voltage Regulation: in special diodes like Zener diodes.
• Photodiodes: reverse-biased PN junctions sensitive to light.

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 • LEDs: forward-biased PN junctions that emit light.

The MOS Transistor

The MOS transistor (Metal Oxide Semiconductor transistor), commonly known as a MOSFET (Metal Oxide
Semiconductor Field Effect Transistor), is a fundamental type of field-effect transistor widely used in
modern electronics, including microprocessors, memory chips, digital logic circuits, and power devices.

Structure and Operation:

• A MOS transistor consists of:

• A semiconductor substrate (usually silicon), lightly doped.
• Two heavily doped regions called source and drain.
• A thin insulating layer of silicon dioxide (SiO2).
• A metal gate terminal placed on top of the oxide layer.
• The gate terminal is electrically insulated from the semiconductor by the oxide layer, allowing the
gate voltage to create an electric field that controls the conductivity of a channel.

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Types of MOS Transistors:
MOS transistors are classified based on the type of semiconductor channel:
NMOS (N-Channel MOSFET): Uses a p-type substrate with heavily doped n-type source and drain.
Applying a positive gate voltage induces an n-type channel, allowing current flow.
PMOS (P-Channel MOSFET): Uses an n-type substrate with heavily doped p-type source and drain.
Applying a negative gate voltage induces a p-type channel for current flow.

Modes of Operation:
➢ Enhancement mode:

Enhancement mode in a MOSFET refers to a mode of operation where the transistor is normally off at zero
gate-to-source voltage (VGS = 0), meaning there is no conductive channel between the source and drain
initially. The device requires a gate voltage exceeding a certain threshold voltage (VTH) to induce or
"enhance" a conductive channel, allowing current to flow from drain to source.

➢ Depletion mode:

Depletion mode in a MOSFET refers to a mode where the transistor is normally on at zero gate-to-source
voltage (VGS = 0), meaning there is already a conductive channel between the source and drain without
applying any gate voltage. This contrasts with enhancement-mode MOSFETs, which are normally off at zero
gate voltage.

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Key Characteristics:
➢ Voltage-controlled device: The current flow between source and drain is controlled by the gate
voltage.
➢ High input impedance: The insulated gate leads to negligible input current, making MOSFETs
efficient switches and amplifiers.
➢ Low power consumption: Ideal for integrated circuits, enabling dense, low-power digital and
analog designs.

MOS Structure:
➢ Figure shows a simplified structure of an n-type MOS(NMOS) device. Fabricated on a p-type
substrate (also called the “bulk” or the “body”), the device consists of two heavily-doped n regions
forming the source and drain terminals, a heavily-doped (conductive) piece of polysilicon1 (simply
called “poly”) operating as the gate, and a thin layer of silicon dioxide (SiO2) (simply called
“oxide”) insulating the gate from the substrate.

Fig: Structure of a MOS device

➢ The dimension of the gate along the source-drain path is called the length, L, and that perpendicular
to the length is called the width, W. Since the S/D junctions “side-diffuse” during fabrication, the
actual distance between the source and the drain is slightly less than L.
𝐿𝑒𝑓𝑓 = 𝐿𝑑𝑟𝑎𝑤𝑛 − 2𝐿𝐷
• where 𝐿𝑒𝑓𝑓 is the “effective” length
• 𝐿𝑑𝑟𝑎𝑤𝑛 is the total length
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 • 𝐿𝐷 is the amount of side diffusion
• 𝐿𝑒𝑓𝑓 and the gate oxide thickness, tox, play an important role in the performance of MOS circuits.
In complementary MOS(CMOS) technologies, both NMOS and PMOS transistors are available.

MOS Symbols:
The circuit symbols used to represent NMOS and PMOS transistors are shown in Fig.
The source of the PMOS device is positioned on top since it has a higher potential than its gate. Since in
most circuits the bulk terminals of NMOS and PMOS devices are tied to ground and VDD, respectively, we
usually omit these connections as in fig(b) and switch symbols in fig(c) are used generally in digital circuits.

Fig: MOS Symbols

The symbols in fig(b) are generally preferred because the visual distinction between S and D proves helpful
in understanding the operation of circuits.

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The MOS System Under External Bias:

➢ Depending on the polarity and the magnitude of VG, three different operating regions can be
observed for the MOS system: accumulation, depletion, and inversion.
➢ If a negative voltage VG is applied to the gate electrode, the holes in the p-type substrate are
attracted to the semiconductor-oxide interface. The majority carrier concentration near the surface
becomes larger than the equilibrium hole concentration in the substrate; hence, this condition is
called carrier accumulation on the surface as shown in Fig.

Fig: The cross-sectional view of the MOS structure operating in accumulation region

➢ Now consider the case in which a small positive gate bias VG is applied to the gate electrode. Since
the substrate bias is zero, the oxide electric field will be directed towards the substrate in this case.
➢ The majority carriers, i.e., the holes in the substrate, will be repelled back into the substrate as a
result of the positive gate bias, and these holes will leave negatively charged fixed acceptor ions
behind. Thus, a depletion region is created near the surface as shown in figure.

Fig: The cross-sectional view of the MOS structure operating in depletion mode, under small gate bias.

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 ➢ If the positive gate bias is further increased i.e. VG>0(Large). As a result of the increasing surface
potential, the electron density is larger than the majority hole density, since the positive gate potential
attracts additional minority carriers (electrons) from the bulk substrate to the surface as shown in
figure.
➢ The n-type region created near the surface by the positive gate bias is called the inversion layer, and
this condition is called surface inversion.
➢ It will be seen that the thin inversion layer on the surface with a large mobile electron concentration
can be utilized for conducting current between two terminals of the MOS transistor.

Fig: The cross-sectional view of the MOS structure in surface inversion, under larger gate bias voltage.

Derivation of I/V Characteristics:

➢ Consider a semiconductor bar carrying a current I [Fig.1]. If the mobile charge density along the

direction of current is 𝑄𝑑 coulombs per meter and the velocity of the charge is v meters per second,

then

𝐼 = 𝑄𝑑 . 𝑣 (1)

With a velocity v, all of the charge enclosed in v meters of the bar must flow through the cross section
in one second.

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 (a) (b)

Fig 1: (a) A semiconductor bar carrying a current I; (b) snapshots of the carriers one second apart.

➢ For, 𝑉𝐺𝑆 ≥ 𝑉𝑇𝐻 any charge placed on the gate must be mirrored by the charge in the channel,
generating a uniform channel charge density (charge per unit length along the source-drain path)
equal to
where is 𝐶𝑜𝑥 multiplied by W to represent the total capacitance per unit length.
➢ The charge density at a point x along the channel can be written as
𝑄𝑑 (𝑥) = 𝑊𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉(𝑥) − 𝑉𝑇𝐻 ) (3)
where V(x) is the channel potential at x. From (1), the current is given by
𝐼𝐷 = −𝑊𝐶𝑜𝑥 [𝑉𝐺𝑆 − 𝑉(𝑥) − 𝑉𝑇𝐻 ]𝑉 (4)
where the negative sign is introduced because the charge carriers are negative.
➢ Note that v denotes the velocity of the electrons in the channel. For semiconductors, v = µE, where μ
is the mobility of charge carriers and E is the electric field.
𝑑𝑉
➢ Noting that E(x)=− 𝑑𝑥 and representing the mobility of electrons by 𝜇 𝑛 , we have
𝑑𝑉
𝐼𝐷 = −𝑊𝐶𝑜𝑥 [𝑉𝐺𝑆 − 𝑉(𝑥) − 𝑉𝑇𝐻 ]𝑉𝜇 𝑛 𝑑𝑥 (5)

Using boundary conditions V(0)=0 and V(L)= 𝑉𝐷𝑆 . Multiplying both sides by dx and performing
integration, we obtain
𝐿 𝐷𝑆 𝑉
∫𝑥=0 𝐼𝐷 𝑑𝑥 = ∫𝑉=0 𝑊𝐶𝑜𝑥 𝜇 𝑛 [(𝑉𝐺𝑆 − 𝑉𝑇𝐻 ) − 𝑉(𝑥)] 𝑑𝑉 (6)
➢ Since ID is constant along the channel,
𝑉2 𝑉𝐷𝑆
𝐼𝐷 𝐿 = 𝑊𝐶𝑜𝑥 𝜇 𝑛 [(𝑉𝐺𝑆 − 𝑉𝑇𝐻 )𝑉 − ]
2 0
𝑊 𝑉𝐷𝑆 2
𝐼𝐷 = 𝜇𝐶𝑜𝑥 [(𝑉𝐺𝑆 − 𝑉𝑇𝐻 )𝑉𝐷𝑆 − ] (7)
𝐿 2

Here L is the effective channel length.

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 Figure (2) plots the parabolas for the equation (7) for different values of 𝑉𝐺𝑆 , indicating that the
“current capability” of the device increases with 𝑉𝐺𝑆 .
𝜕𝐼
➢ Calculating 𝜕 𝑉𝐷 , shows that the peak of each parabola occurs at 𝑉𝐷𝑆 =𝑉𝐺𝑆 − 𝑉𝑇𝐻 and the peak current
𝐷𝑆

is

1 𝑊
𝐼𝐷,𝑚𝑎𝑥 = 2 𝜇𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 (8)
𝐿

𝑊
Here 𝑉𝐺𝑆 − 𝑉𝑇𝐻 is called the “overdrive voltage” and is the “aspect ratio.” If 𝑉𝐷𝑆 ≤𝑉𝐺𝑆 − 𝑉𝑇𝐻 , we say
𝐿

that the device operates in the “triode region.”

Fig 2: Drain current versus drain-source voltage in the triode region.

If in equation (7), 𝑉𝐷𝑆 ≪2(𝑉𝐺𝑆 − 𝑉𝑇𝐻 ), we have

𝑊
𝐼𝐷 ≈ 𝜇𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 ) 𝑉𝐷𝑆 (9)
𝐿

that is, the drain current is a linear function of 𝑉𝐷𝑆 . For small 𝑉𝐷𝑆 as shown in figure (3) each parabola can
be approximated by a straight line. The linear relationship implies that the path from the source to the drain
can be represented by a linear resistor equal to

1
𝑅𝑜𝑛 = 𝑊 (10)
𝜇 𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )
𝐿

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 Fig(3): Linear operation in deep triode region.

➢ A MOSFET can therefore operate as a resistor whose value is controlled by the overdrive voltage as
𝑉𝐷𝑆 ≪2(𝑉𝐺𝑆 − 𝑉𝑇𝐻 ) and the device operates in the deep triode region.

Fig (4): MOSFET as a controlled linear resistor

Saturation Region:
If 𝑉𝐷𝑆 > 𝑉𝐺𝑆 −𝑉𝑇𝐻 , 𝐼𝐷 becomes relatively constant, and the device operates in the “saturation” region.

Fig (5): Saturation of drain current.

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Pinch-Off Voltage in MOSFET:
➢ Pinch-off voltage in a MOSFET refers to the drain-to-source voltage at which the MOSFET channel
becomes partially depleted near the drain, and the device enters the saturation region.
➢ When the applied voltage 𝑉𝐺𝑆 (gate-to-source) greater than the threshold voltage 𝑉𝑇𝐻 , a conducting
channel forms between the source and drain.
➢ As you increase the drain-to-source voltage 𝑉𝐷𝑆 , electrons start flowing from source to drain.
➢ At a certain point when:
𝑉𝐷𝑆 = 𝑉𝐺𝑆 - 𝑉𝑇𝐻
the voltage difference between the gate and the drain end of the channel becomes equal to the
threshold voltage. This causes the channel to narrow near the drain — this is the pinch-off point.
➢ Beyond this point, increasing 𝑉𝐷𝑆 does not significantly increase the drain current 𝐼𝐷 . The MOSFET
is now in the saturation region, where it behaves like a current source.

Fig (6): Pinch-off behavior.

Second-Order Effects:
1. Body Effect:
➢ Suppose 𝑉𝑆 = 𝑉𝐷 = 0, and 𝑉𝐺 is less than 𝑉𝑇𝐻 , so that a depletion region is formed under the
gate but no inversion layer exists.
➢ As 𝑉𝐵 becomes more negative, more holes are attracted to the substrate connection, leaving a
larger negative charge behind, i.e. the depletion region becomes wider.
➢ The threshold voltage is a function of the total charge in the depletion region because the gate
charge must mirror 𝑄𝑑 before an inversion layer is formed.
➢ Thus, as 𝑉𝐵 drops and 𝑄𝑑 increases, 𝑉𝑇𝐻 also increases. This phenomenon is called the “body
effect” or the “back-gate effect.”
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 𝑉𝑇𝐻 = 𝑉𝑇𝐻0 + 𝛾(√2∅𝐹 + 𝑉𝑆𝐵 − √|2∅𝐹 |

Where 𝑉𝑇𝐻0 is the threshold voltage without body effect,

𝛾 = √2𝑞𝜖𝑠𝑖 𝑁𝑠𝑢𝑏 /𝐶𝑜𝑥
denotes the body-effect coefficient and 𝑉𝑆𝐵 is the source – bulk potential difference.

Channel Length Modulation:

➢ In the analysis of channel pinch-off, the actual length of the channel gradually decreases as the
potential difference between the gate and the drain decreases.
➢ The actual length 𝐿′ of the channel gradually decreases from total length L as 𝑉𝐷𝑆 increase. This
effect is called channel length modulation.

Mathematically,

𝐿′ = 𝐿 − ∆𝐿

1 1
= 𝐿−∆𝐿
𝐿′
𝐿+∆𝐿
= (𝐿−∆𝐿)(𝐿+∆𝐿)
𝐿+∆𝐿
≈ 𝐿2−∆𝐿2

∆𝐿
𝐿+ 𝐿
≈
𝐿
1 1 ∆𝐿
= 𝐿 (1 + )
𝐿′ 𝐿

In the saturation region,

1 𝑊
𝐼𝐷 = 𝜇 𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
2 𝐿

1 𝑊
𝐼𝐷 ≈ 𝜇 𝑛 𝐶𝑜𝑥 ′ (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
2 𝐿
1 𝑊 ∆𝐿
≈ 2 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 (1 + )
𝐿 𝐿

∆𝐿 ∆𝐿
Assuming a first-order relationship between and 𝑉𝐷𝑆 such as = λ𝑉𝐷𝑆 , then
𝐿 𝐿

1 𝑊
𝐼𝐷 ≈ 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 (1 + λ𝑉𝐷𝑆 )
2 𝐿
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 Where λ is the “channel-length modulation coefficient.”

MOS Device Layout:

Fig (7): Bird’s-eye and vertical views of a MOS device.

Passive Components:
➢ The passive components that are compatible with fabrication steps used to build the MOS device.
These passive components include the capacitor and the resistor.

Capacitors:

➢ A good capacitor is often required when designing analog integrated circuits.

➢ They are used as compensation capacitors in amplifier designs, as bandwidth-determining
components in gm/C filters, as charge storage devices in switched-capacitor filters and digital-to-
analog converters, and in other places as well.
➢ The desired characteristics for capacitors used in these applications are given below:
• Good matching accuracy.
• Low voltage coefficient.
• High ratio of desired capacitance to parasitic capacitance.
• High capacitance per unit area.
• Low temperature dependence.
➢ For analog processes, there are basically two types of capacitors made available, capacitors utilizing
polysilicon for plates and capacitors utilizing metal for plates.
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 ➢ Modern submicron processes (0.18 mm and below) use MiM (metal-insulator-metal) capacitors
because they are economical to build (minimal masks, steps, and process complexity) and meet the
criteria set forth above.
➢ Figure (8) shows an example of a MiM capacitor. It is formed by providing an additional metal layer
prior to the last metal interconnect layer that lies above a thin oxide region on top of the next to last
metal layer (i.e., a capacitor metal on top of M4, separated by a thin oxide region fabricated in a five-
metal process).

Fig (8): MiM Capacitor

Resistors:

➢ The other passive component compatible with MOS technology is the resistor. Some applications,
such as digital-to-analog conversion, use resistors. Resistors compatible with the MOS technology, it
includes diffused, polysilicon, and n-well resistors.
For a conductive bar of material as shown in Fig.9, the resistance, R, is given as
𝜌𝐿
𝑅= (𝛺) (1)
𝐴

where ρ is resistivity in 𝛺 -cm and A is a plane perpendicular to the direction of current flow. The
equation (1) can be rewritten as
𝜌𝐿
𝑅 = 𝑊𝑇 (𝛺) (2)
𝜌 𝐿 𝐿
𝑅 = (𝑇 ) 𝑊 = 𝜌𝑠 𝑊 (𝛺) (3)
𝛺
The units of 𝜌𝑠 is ⎕ (read ohms per square). From the layout point of view, a resistor has the value

determined by the number of squares of resistance multiplied by 𝜌𝑠 .

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 Fig (9): Current flow in a conductive bar.

• Figure (10) illustrates a P^+ diffusion resistor. It is formed using source/drain diffusion in an n-well.
The sheet resistance of such resistors in a non-silicide process is usually in the range of 50–150 Ω∕⎕.
• For a silicide process, these resistors are in the range of 5–15 Ω∕⎕. The fact that the source/drain
diffusion is needed as a good conductor (i.e., as interconnect) in integrated circuits conflicts with its
use as a resistor.

Figure (10): Diffusion Resistor

Integrated Circuit Layout:

➢ A circuit defined and functioning properly at the schematic level can fail if it is not correctly
designed physically. Physical design, in the context of integrated circuits, is referred to as layout.
➢ An integrated circuit is made up of multiple layers, each defined by a photomask using a
photolithographic process, on a thin substrate of semiconductor material. Each photomask is built
from a computer database that describes it geometrically. This database is derived from the physical
layout drawn by a mask designer or by computer.

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 ➢ The layout consists of topological descriptions of all electrical components that will ultimately be
fabricated on the integrated circuit. The most common components that have been discussed are
transistors, resistors, and capacitors.

Matching Concepts:
➢ Matching performance of two or more components is very important to overall circuit operation.
Since matching is dependent on layout topology.
➢ The rule for making two components electrically equivalent is simply to draw them as identical units.
This is the unit-matching principle. The two components are identical means that both they and their
surroundings must be identical.
➢ Consider the two square components, A and B, illustrated in Fig. (11a). In this example, these objects
could be pieces of metal that are desired after deposition and etching. They have identical shape in
area and perimeter as drawn. However, the surroundings seen by A and B are different due to the
presence of object C.
➢ The presence of object C nearer to object B may cause that object to change in some way different
than A. The solution to this is to somehow force the surroundings of both geometries A and B to be
the same.
➢ However, matching performance can normally be improved by at least making the immediate
surroundings identical as illustrated in Fig.(11b). Frequently, dummy devices are placed around the
perimeter of a set of geometries being matched.
➢ These dummy devices have no electrical function but rather serve to meet the objective of
minimizing effects due to asymmetric surroundings. This general principle will be applied repeatedly
to components of various types.

Fig: 11a Fig: 11b

23
MOS Transistor Layout:
➢ Figure (12) shows the layout of a single MOS transistor. Transistors that are used for analog
applications are drawn as linear stripes as opposed to a transistor drawn with a bend or corner in the
gate. The dimensions that will be important later on are the width and length of the transistor as well
as the area and periphery of the drain and source.
➢ It is the W/L ratio that is the dominant dimensional component governing transistor conduction, and
the area and periphery of the drain and source that determine drain and source capacitance on a per-
device basis.

Resistor Layout:
➢ Figure (13) shows the layout of a polysilicon resistor (top view and side view at the cut line).
Generally, polysilicon resistors used in analog circuits require a silicide block to achieve a reasonable
sheet resistance. Because the silicided polysilicon is somewhat low resistance, the primary resistance
is specified by the non-silicided region.

24
Capacitor Layout:

➢ Capacitors can be constructed in a variety of ways depending upon the process as well as the
particular application. Only two detailed capacitor structures will be discussed.
➢ The MiM capacitor layout is illustrated in Fig.14(a). Notice that the cap layer boundary falls
completely within the boundaries of the Metal 4 layer and the top-plate contact is made at the center
of the cap-layer geometry.
➢ The cap layer should always reside inside the boundaries of the bottom-plate Metal 4 in order to
achieve the most precise capacitance.

➢ Precision capacitors are generally made using multiple layers of metal—MOM capacitors. An
example of a two-metal MOM finger-capacitor is illustrated in Fig. 14(b).
➢ In this layout, the two capacitor plates are interleaved between the two metal layers; thus, there is no
clear distinction between top and bottom plates. The concept illustrated is easily extended to more
metal layers.

25
Fig: 14(a)

Fig: 14(b)

26
CMOS Device Modeling:
There are 2 main analysis methods used:
(1) Large signal analysis.
(2) Small signal analysis.

➢ Large signal analysis is used when the voltage/current values changes are large such that the non-
linear behavior of the transistor must be accounted for. Large signal analysis is mainly used for
finding the bias conditions of a circuit.
➢ The bias condition of a circuit is the set of voltage/current values that occur in a circuit when all
input signals are set to a fixed dc value.
➢ Small signal analysis is used when one wants to ignore the non-linear behavior of the transistor and
instead look at variations in the voltage/current values from their bias conditions.

Simple MOS Large-Signal Model (SPICE LEVEL 1):

All large-signal models will be developed for the n-channel MOS device with the positive polarities of
voltages and currents shown in Fig. 15(a). The same models can be used for the p-channel MOS device if all
voltages and currents are multiplied by -1 and the absolute value of the p-channel threshold is used. This is
equivalent to using the voltages and currents defined by Fig. 15(b), which are all positive quantities.

Figure: 15 Positive sign convention for (a) n-channel and (b) p-channel MOS transistor.

When the length and width of the MOS device is greater than about 10 μm, the substrate doping is low, and
when a simple model is desired, the model suggested by Sah and used in SPICE by Shichman and Hodges is
appropriate. This model was developed in 𝐸𝑞 𝐼𝐷 and is given below.

𝜇0 𝐶𝑜𝑥 𝑊 𝑉𝐷𝑆
𝐼𝐷 = [(𝑉𝐺𝑆 − 𝑉𝑇 ) − ( )]𝑉𝐷𝑆 (1)
𝐿 2

27
The various parameters of Eq.(1) are defined as,
𝜇0 =surface mobility of the channel for the n−channel or p−channel device (𝑐𝑚2 ∕V−s).
𝜀
𝐶𝑜𝑥 =𝑡𝑜𝑥=capacitance per unit area of the gate oxide (F/cm^2).
𝑜𝑥

W=effective channel width.

L=effective channel length.

The threshold voltage 𝑉𝑇 for an n-channel transistor:

𝑉𝑇 =𝑉𝑇0+ γ (√2|𝜙𝐹 | + 𝑉𝑆𝐵 −√2|𝜙𝐹 |) (2)

√2𝑞𝜀𝑠𝑖 𝑁𝑆𝑈𝐵 2|𝜙𝐹 |
𝑉𝑇0=𝑉𝑇 (𝑉𝑆𝐵 = 0) = 𝑉𝐹𝐵 +2|𝜙𝐹 |+ (3)
𝐶𝑜𝑥

√2𝜀𝑠𝑖 𝑞𝑁𝑆𝑈𝐵
γ = bulk threshold parameter (𝑉 1⁄2 )= (4)
𝐶𝑜𝑥

𝜙𝐹 = strong inversion surface potential(V)=kT/qln(N_SUB/n_i) (5)

𝑄
𝑉𝐹𝐵 = flatband voltage(V)= 𝜙𝑀𝑆 − 𝐶 𝑠𝑠 (6)
𝑜𝑥

𝜙𝑀𝑆 = 𝜙𝐹 (substrate)− 𝜙𝐹 (gate) (7)

𝑘𝑇 𝑁𝑆𝑈𝐵
𝜙𝐹 (substrate)= − 𝑞 ln ( ) [n-channel with p-substrate] (8)
𝑛𝑖
𝑘𝑇 𝑁𝐺𝐴𝑇𝐸
𝜙𝐹 (gate)= − 𝑞 ln ( ) [n-channel with 𝑛+ polysilicon gate] (9)
𝑛𝑖

𝑄𝑆𝑆 = oxide-charge = q𝑁𝑆𝑆 (10)

k= Boltzmann’s constant
T= temperature (k)
𝑛𝑖 = intrinsic carrier concentration
The drain current is often expressed as
𝑉𝐷𝑆
𝑖𝐷 =β[(𝑉𝐺𝑆 − 𝑉𝑇 )− ] 𝑉𝐷𝑆 (11)
2

or
𝑊 𝑉𝐷𝑆
𝑖𝐷 =𝐾 ′ 𝐿 [(𝑉𝐺𝑆 − 𝑉𝑇 )− ] 𝑉𝐷𝑆 (12)
2

where the transconductance parameter β is given in terms of physical parameters as

28
 𝑊 𝑊
𝛽 = 𝐾′ ≅ 𝜇0 𝐶𝑜𝑥 (𝐴⁄𝑉 2 ) (13)
𝐿 𝐿

When devices are characterized in the non-saturation region with low gate and drain voltages, the value for
K is approximately equal to 𝜇0 𝐶𝑜𝑥 in the simple model.
There are various regions of operation of the MOS transistor based on the model of Eq.(1). These regions of
operation depend on the value of 𝑉𝐺𝑆 − 𝑉𝑇 . If 𝑉𝐺𝑆 − 𝑉𝑇 is zero or negative, then the MOS device is in the
cutoff region and Eq. (1) becomes
𝑖𝐷 = 0, 𝑉𝐺𝑆 − 𝑉𝑇 ≤ 0 (14)
In this region, the channel acts like an open circuit.

Fig 16: Graphical illustration of the modified Sah equation.

A plot of Eq. (1) with λ=0 as a function of 𝑉𝐷𝑆 is shown in Fig.16 for various values of 𝑉𝐺𝑠 − 𝑉𝑇 . At the
maximum of these curves the MOS transistor is said to saturate. The value of 𝑉𝐷𝑆 at which this occurs is
called the saturation voltage and is given as

𝑉𝐷𝑆 (𝑆𝑎𝑡) = 𝑉𝐺𝑆 − 𝑉𝑇 (15)

Thus, 𝑉𝐷𝑆 (𝑆𝑎𝑡) defines the boundary between the remaining two regions of operation. If 𝑉𝐷𝑆 is less than
𝑉𝐷𝑆 (𝑆𝑎𝑡), then the MOS transistor is in the non-saturated region and Eq.(1) becomes
𝑊 𝑉𝐷𝑆
𝑖𝐷 = 𝐾 ′ [(𝑉𝐺𝑆 − 𝑉𝑇 ) − ] 𝑉𝐷𝑆 , 0 < 𝑉𝐷𝑆 ≤ (𝑉𝐺𝑆 − 𝑉𝑇 ) (16)
𝐿 2

In Fig.17, the nonsaturated region lies between the vertical axis (𝑉𝐷𝑆 =0) and the 𝑉𝐷𝑆 =𝑉𝐺𝑆 −𝑉𝑇 curve.
The third region occurs when𝑉𝐷𝑆 is greater than 𝑉𝐷𝑆 (𝑆𝑎𝑡) or 𝑉𝐺𝑆 − 𝑉𝑇 . At this point the current i_D becomes
29
independent of 𝑉𝐷𝑆 . Therefore, 𝑉𝐷𝑆 in Eq.(1) is replaced by 𝑉𝐷𝑆 (Sat) of Eq.(15) to get
𝑊
𝑖𝐷 =𝐾 ′ 2𝐿 (𝑉𝐺𝑆 − 𝑉𝑇 )2, 0< (𝑉𝐺𝑆 − 𝑉𝑇 ) ≤ 𝑉𝐷𝑆 (17)

Equation (17) indicates that drain current remains constant once𝑉𝐷𝑆 is greater than 𝑉𝐺𝑆 − 𝑉𝑇 ). In reality, this
is not true. As drain voltage increases, the channel length is reduced, resulting in increased current. This
phenomenon is called channel length modulation and in the saturation model with the addition of the factor
(1+λ𝑉𝐷𝑆 ), where 𝑉𝐷𝑆 is the actual drain–source voltage and not 𝑉𝐷𝑆 (Sat).

The saturation region model modified to include channel length modulation is given in Eq.(18):
𝑊
𝑖𝐷 =𝐾 ′ 2𝐿 (𝑉𝐺𝑆 − 𝑉𝑇 )2 (1 + λ𝑉𝐷𝑆 ), 0< (𝑉𝐺𝑆 − 𝑉𝑇 ) ≤ 𝑉𝐷𝑆 (18)

Here the various regions of the MOS transistor as cutoff when (𝑉𝐺𝑆 − 𝑉𝑇 ) ≤ 0 ; as active, ohmic, triode, or
non-saturation when 0≤ 𝑉𝐷𝑆 ≤(𝑉𝐺𝑆 − 𝑉𝑇 ) ; and as saturation when (𝑉𝐺𝑆 − 𝑉𝑇 ) ≤ 𝑉𝐷𝑆 .

Fig 17: Output characteristics of the MOS device.

Other MOS Large-Signal Model Parameters:

➢ The large-signal model also includes several other characteristics such as the source/drain bulk
junctions, source/drain ohmic resistances, various capacitors, noise, and temperature dependence.
The complete version of the large-signal model is given in Fig.18.
➢ The diodes of Fig.18. represent the pn junctions between the source and substrate and the drain and
substrate. For proper transistor operation, these diodes must always be reverse biased. Their purpose
in the dc model is primarily to model leakage currents.

30
 These currents are expressed as
𝑞𝑣𝐵𝐷
𝑖𝐵𝐷 = 𝐼𝑆 [exp ( ) − 1] (1)
𝑘𝑇

and

𝑞𝑣𝐵𝑆
𝑖𝐵𝑆 = 𝐼𝑆 [exp ( ) − 1] (2)
𝑘𝑇

where 𝐼𝑆 is the reverse saturation current of a pn junction, q is the charge of an electron, k is Boltzmann’s
constant, and T is temperature in kelvin units.

➢ The resistors 𝑟𝐷 and 𝑟𝑆 represent the ohmic resistance of the drain and source, respectively.
The capacitors of Fig.18 can be separated into three types. The first type includes capacitors 𝐶𝐵𝐷
and 𝐶𝐵𝑆 , which are associated with the back biased depletion region between the drain and
substrate and the source and substrate.
➢ The second type includes capacitors 𝐶𝐺𝐷 , 𝐶𝐺𝑆 , and 𝐶𝐺𝐵 , which are all common to the gate and are
dependent on the operating condition of the transistor.
➢ The third type includes parasitic capacitors, which are independent of the operating conditions.

Fig 18: Complete large-signal model for the MOS transistor.

31
Small-Signal Model for the MOS Transistor:

• The small-signal model is a linear model that helps to simplify calculations.

Figure .19 shows a linearized small-signal model for the MOS transistor. The para meters of the
small-signal model will be designated by lowercase subscripts.
• The various parameters of this small-signal model are all related to the large-signal model para
meters and dc variables.
• The relationship between these two models assumes that the small-signal parameters are defined in
terms of the ratio of the partial differentiation of one large-signal variable with respect to another.

Fig:19 Small-signal model of the MOS transistor.

The conductance 𝑔𝑏𝑑 and 𝑔𝑏𝑠 are the equivalent conductance of the bulk-to-drain and bulk-to-source
junctions. They are defined as
𝜕𝑖
𝑔𝑏𝑑 =𝜕𝑣𝐵𝐷 (evaluated at the quiescent point) ≅0 (1)
𝐵𝐷

and
𝜕𝑖
𝑔𝑏𝑠 =𝜕𝑣𝐵𝑆 (evaluated at the quiescent point) ≅0 (2)
𝐵𝑆

The channel transconductances 𝑔𝑚 and 𝑔𝑚𝑏𝑠 and the channel conductance 𝑔𝑑𝑠 are defined as
32
 𝜕𝑖
𝑔𝑚 = 𝜕𝑣 𝐷 (evaluated at the quiescent point) (3)
𝐺𝑆

𝜕𝑖𝐷
𝑔𝑚𝑏𝑠 = (evaluated at the quiescent point) (4)
𝜕𝑣𝐵𝑆

and
𝜕𝑖
𝑔𝑑𝑠 =𝜕𝑣 𝐷 (evaluated at the quiescent point) (5)
𝐷𝑆

The values of these small-signal parameters depend on which region the quiescent point occurs in.
The small-signal channel transconductance due to 𝑣𝑆𝐵 can be determined by rewriting
𝜕𝑖 𝜕𝑖 𝜕𝑉
𝑔𝑚𝑏𝑠 =− 𝜕𝑣 𝐷 =−(𝜕𝑉𝐷 )( 𝜕𝑉 𝑇 ) (6)
𝐵𝑆 𝑇 𝑆𝐵

𝜕𝑖𝐷 𝜕𝑖
We know that = −𝜕𝑉𝐷 and 𝑉𝑇 = 𝑉𝑇0 + 𝛾(√2|∅𝐹 | + 𝑉𝑆𝐵 − √|2∅𝐹 |, we get
𝜕𝑉𝑇 𝑇
𝛾
𝑔𝑚𝑏𝑠 = 𝑔𝑚 2(2|𝜙 |+𝑉 1⁄2 = 𝜂𝑔𝑚 (7)
𝐹 𝑆𝐵 )

Short-channel effects in MOSFETs:

Short-channel effects (SCEs) in MOSFETs arise when the channel length becomes comparable to or shorter
than the depletion layer widths of the source and drain regions. This occurs as transistor dimensions are
scaled down to meet demands for higher performance and density. These effects cause deviations from ideal
long-channel MOSFET behavior, impacting threshold voltage, current control, reliability, and overall device
performance.

1. Threshold Voltage Roll-Off:

As the channel length decreases, the control of the gate over the channel weakens due to the
influence of the source and drain junctions. This causes the threshold voltage (the voltage required to
create a conducting channel) to decrease. Lower threshold voltage leads to higher leakage currents
and affects device stability.
This transconductance will become important in small-signal analysis of the MOS transistor when
the ac value of the source–bulk potential 𝑣𝑠𝑏 is not zero.
The small-signal channel conductance, 𝑔𝑑𝑠 (𝑔0 ), is given as
𝐷 𝐼 𝜆
𝑔𝑑𝑠 = 𝑔0 = 1+𝜆𝑉 ≅ 𝐼𝐷 λ
𝐷𝑆

The channel conductance will be dependent on L through λ, which is inversely proportional to L.

2. Drain-Induced Barrier Lowering (DIBL):

The drain voltage lowers the potential barrier at the source-channel junction, which makes it easier
for carriers to be injected into the channel even when the gate voltage is below threshold. This effect

33
 reduces the threshold voltage further and causes increased off-state leakage current, degrading device
performance.

3. Velocity Saturation:
At high electric fields in short channels, carriers (electrons or holes) reach a velocity saturation limit.
Instead of the velocity increasing linearly with the electric field, it saturates, limiting the drive
current and affecting the transistor's transconductance and switching speed.

4. Hot Carrier Injection:

High electric fields near the drain accelerate carriers to high energies ("hot carriers"). These carriers
can penetrate the gate oxide, cause oxide damage and resulting in long-term degradation of device
performance and reliability.

5. Punch-Through:
When the depletion regions of the source and drain extend into the shortened channel region, punch-
through can occur, where the source-to-drain current increases even without proper gate control.

34