U23PEEEC02 Advanced Digital System Design L T P C

(Electronics and Communication

2 0 2 3
Engineering)
COURSE OBJECTIVES:

 To understand and gain the knowledge of sequential circuits and

asynchronous sequential circuits design.
 To understand and gain the knowledge of fault diagnosis and testing procedure
for digital circuits.
 To understand and gain the knowledge of synchronous design using
programmable devices and system design using VERILOG.
UNIT I SEQUENTIAL CIRCUIT DESIGN 6
Analysis of Clocked Synchronous Sequential Circuits and Modelling- State Diagram,
State Table, State Table Assignment and Reduction-Design of Synchronous Sequential
Circuits Design of Iterative Circuits-ASM Chart and Realization using ASM.

UNIT II ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN

6
Analysis of Asynchronous Sequential Circuit – Flow Table Reduction-Races-State
Assignment Transition Table and Problems in Transition Table- Design of
Asynchronous Sequential Circuit - Static, Dynamic and Essential hazards – Mixed
Operating Mode Asynchronous Circuits – Designing Vending Machine Controller.

FAULT DIAGNOSIS AND TESTABILITY

UNIT III 6
ALGORITHMS
Fault Table Method-Path Sensitization Method – Boolean Difference Method - D
Algorithm –– Tolerance Techniques – The Compact Algorithm – Fault in PLA – Test
Generation - DFT Schemes – Built in Self-Test.

SYNCHRONOUS DESIGN USING PROGRAMMABLE

UNIT IV 6
DEVICES
Programming Logic Device Families – Designing a Synchronous Sequential Circuit
using PLA/PAL – Designing ROM with PLA – Realization of Finite State Machine using
PLD – FPGA – Xilinx FPGA - Xilinx 4000.

UNIT V SYSTEM DESIGN USING VERILOG 6

Hardware Modelling with Verilog HDL – Logic System, Data Types And Operators For
Modelling In Verilog HDL - Behavioral Descriptions In Verilog HDL – HDL Based
Synthesis – Synthesis Of Finite State Machines– Structural Modelling – Compilation
And Simulation Of Verilog Code – Test Bench - Realization Of Combinational And
Sequential Circuits Using Verilog – Registers – Counters – Sequential Machine – Serial
Adder – Multiplier- Divider .
30 PERIODS
PRACTICAL EXERCISES:
1. Design of sequential circuits by Verilog HDL.
2. Design of asynchronous sequential circuits by Verilog HDL.
3. Design of fault diagnosis and testing procedure for combinational circuit with
PLA.
4. Design of synchronous sequential circuits by Verilog HDL.
 5. Design of Serial Adders, Multiplier and Divider by Verilog HDL.

List of Equipment’s needed for 30 students in a batch (6 students in bench)

1. Xilinx ISE/Altera Quartus/ equivalent EDA Tools.
2. Xilinx /Altera/equivalent FPGA Boards.
3. Cadence/Synopsis/ Mentor Graphics/Tanner/equivalent EDA Tools.
4. Personal Computer.
30 PERIODS
TOTAL: 60 PERIODS
TEXT BOOKS:
1 Charles [Link]., “Fundamentals of Logic Design” Thomson Learning, 2013.
2 [Link] , Modeling, Synthesis and Rapid Prototyping with the Verilog HDL,
Prentice Hall, 1999.
REFERENCES:
1 [Link] “Fault Tolerant and Fault Testable Hardware Design” B S
Publications, 2002.
2 [Link] “Digital System Design Using PLD” B S Publications, 2003.
3 Palnitkar, Verilog HDL – A Guide to Digital Design and Synthesis, Pearson,
2003.

ONLINE RESOURCES:
1 [Link]
2 [Link]
3 [Link]
4 [Link]

COURSE OUTCOMES:
Upon the completion of the course, the students will be able to
CO1 Analyse and design of sequential circuits.
CO2 Analyse hazards and design of asynchronous sequential circuits.
CO3 Analyse and design of fault diagnosis and testing procedure for
combinational circuit with PLA.
CO4 Design of Synchronous Sequential Circuit using programmable devices.
CO5 Design and use programming tools for implementing digital circuits.
CO – PO – PSO MAPPING:
P P P P P P P
PO PO PO PO PO PSO
O O O O O O O PSO1
1 2 8 10 11 2
3 4 5 6 7 9 12
CO1 3 3 2 2 2 2 2 2
CO2 3 3 2 2 2 2
CO3 3 3 2 2 1 2 2
CO4 3 3 3 2 1 2 2 2
CO5 3 3 3 2 2 2 2 2 2