8085 Microprocessor Architecture
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8085 Microprocessor Architecture
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Memory map
It is a pictorial representation in which memory chips are located in the entire range of
addresses
Memory addresses: provide the location of various memory devices in the system.
The interfacing logic defines the range of memory addresses of each memory device.
Memory interfacing:
Typical memory chip
Basic concept in memory interfacing:
1. Select the chip (higher order address to activate cs)
2. Identify the memory location (low order address to enable the F/F)
3. Enable the I/P buffer (using WR) OR O/P buffer (using RD)
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8085 Microprocessor Architecture
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To interface the memory with MP:
1. Connect the low order of AB to the address pins of memory chip.
2. Decode the higher AB to generate unique address to the memory chip which
activate the CS
3. Generate the control signals MEMR & MEMW by combining RD , WR with
IO/M
Ex(1) :Design a cct. to connect 1/4 k byte of RAM chip to a µP with AB= 10 bits , DB=8
bits. Draw the memory map.
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8085 Microprocessor Architecture
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SOL.
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8085 Microprocessor Architecture
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Memory Map
SOL 4 300H-3FFH
11 1111 11112
11 0000 00002
SOL 3 200H-2FFH
10 1111 11112
10 0000 00002
SOL 2 100H-1FFH
01 1111 11112
01 0000 00002
SOL 1 000H-0FFH
00 1111 11112
00 0000 00002
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8085 Microprocessor Architecture
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Ex(2) :Design a cct. to connect 1/2 k byte of RAM chip to a µP with AB= 10 bits ,
DB=8 bits. Draw the memory map.
A9 A9
A8
A8
A0
A0
High Low order
order
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Sol1 000H = 0 0 0 0 0 0 0 0 0 0 1st
1FFH = 0 1 1 1 1 1 1 1 1 1 Last
location
200H = 1 0 0 0 0 0 0 0 0 0 1st
Sol2
3FFH = 1 1 1 1 1 1 1 1 1 1 Last
location
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8085 Microprocessor Architecture
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Memory Map
SOL 2 11 1111 11112
200H -
3FFH
10 0000 00002
01 1111 11112
SOL 1
000H-1FFH
00 0000 00002
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8085 Microprocessor Architecture
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Ex: For the circuit shown below:
1) Find the range of addresses for each memory chip & draw the memory map.
Ans: 2x = 4K x=12 A11 A0
Higher order Low Order
ROM A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1st location 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Last location 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Range of ROM addresses 1000H ------- 1FFFH
RAM A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1st location 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
last location 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Range of RAM addresses 7000 H--------------- 7FFFH
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8085 Microprocessor Architecture
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Memory map
2) H.W. Find the range of addresses and draw the memory map if we connect
the CS of the ROM to O/P 4 (2) if we connect CS of the RAM to O/P 5.
3) Repeat step 1 if we:
a) Exchange A14 with A15.
b) Exchange A12 with A15.
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8085 Microprocessor Architecture
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Ans: a)
A14
A15
For ROM , the range will not change 1000H ------ 1FFFH because both E1, E2 and I/P of the decoder
must be 0
RAM A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1st location 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Last location 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Hence, the RAM range of addresses will be changed to: B000H ------- BFFFH
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8085 Microprocessor Architecture
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b)
A12
A15
ROM A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
8000 ---- 8FFF 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E000 ------EFFF 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
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