ECE 441 TCAD Project 2 on MOS Cap and MOSFET

Shaloo Rakheja ([email protected])

TCAD solutions provided by Yicong Dong ([email protected])

Part I: MOS Capacitor

The meshed MOS cap structure is shown in Figure 1.

2
Y

5
-2 0 2 4
X

Fig 1 Meshed MOS capacitor.

1. Equilibrium solution

The band bending in the MOS capacitor at VG = 0 V is shown in Figure 2 below for different

substrate doping concentrations. The band bending magnitude in the semiconductor can be theo-

1
Fig 2 Band bending in equilibrium at different substrate doping levels. The yellow highlighted region is the metal and
the gray highlighted region is the oxide.

retically estimated from potential balance equation as

Qs (ϕs )
VG = VFB − + ϕs . (1)
Cox

From the values provided in the problem, VFB = (φM − φS ), where φS = χ/q + EG /2q +

kT /q ln(NA /ni ) = 4.05 + 0.55 + 0.4 = 5 V. Since φM = 4.54 V, we get VFB = 4.54 − 5 = −0.46

V. Likewise, for ND = 5 × 1017 cm−3 , we can find VFB = −0.5174 V. The value of Cox =

ϵox /xox = 3.9 × 8.85 × 10−14 /(10 × 10−7 ) = 3.45 × 10−7 F/cm2 .

Moreover in equilibrium we know that the charge in the semiconductor is due to depletion, we can
√
write Qs = −qNA xd = − 2qϵs NA ϕs . Thus, in equilibrium Eq. (1) can be simplified as

√
Qs (ϕs ) 2qϵs NA ϕs
VFB = − ϕs ⇒ 0.09 − ϕs = (2)
Cox Cox

This is a quadratic equation which can be solved for different NA values. We find the following:

• NA = 5 × 1016 cm−3 , ϕs = 0.2672 V, ϕox = 0.1928 V.

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 • NA = 5 × 1017 cm−3 , ϕs = 0.1159 V, ϕox = 0.3645 V.

Note that with higher doping, there is less band bending in silicon and more potential is dropped

across the oxide. From TCAD solutions, we can read the band bending and we find that ϕs =

0.2965 V for NA = 5 × 1016 cm−3 and ϕs = 0.1442 V for NA = 5 × 1017 cm−3 . These values are

quite close to those theoretically predicted.

2. Charge in the semiconductor in equilibrium

The charge in the semiconductor along the depth is plotted in Figure 3. We need to integrate it to

get the total charge, which we find from TCAD to be

• NA = 5 × 1016 cm−3 , Qs = −6.69 × 10−8 C/cm2 (TCAD).

• NA = 5 × 1017 cm−3 , Qs = −1.40 × 10−7 C/cm2 (TCAD).

This charge is consistent with theoretical calculations which show

p
Qs = − 2qϵs NA ϕs . (3)

From Part 1, we calculated ϕs for each doping and the charge comes out to be

• NA = 5 × 1016 cm−3 , Qs = −6.65 × 10−8 C/cm2 . (Theory).

• NA = 5 × 1017 cm−3 , Qs = −1.38 × 10−7 C/cm2 (Theory).

3. C-V analysis of the MOS capacitor

a. The Q − Vg profile of the MOS capacitor is shown in Figure 4.

3
 Fig 3 Charge density in the semiconductor at equilibrium.

Fig 4 Semiconductor charge versus applied gate voltage.

b. The C − Vg profile is obtained by differentiating the results of Q − Vg profile obtained in part

a. above. Results are plotted in Figure 5. We can see that in accumulation and inversion, for

both doping densities, the total gate capacitance is very nearly the same as oxide capacitance.

This means that in these regimes, Cs ≫ Cox . The minimum value of capacitance occurs at

the point where depletion width is maximized.

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 Fig 5 Gate capacitance versus gate voltage.

c. Once we have the gate capacitance, the semiconductor capacitance is obtained as

1 1 1
= − . (4)
Cs CG Cox

On the other hand, a better way of obtaining Cs is given as Cs = −dQs /dϕs , where ϕs is the

potential drop across the semiconductor and can be obtained as a function of gate voltage,

V . Results are shown in Fig. 6.

Fig 6 Semiconductor capacitance versus gate voltage.

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 d. To find the threshold voltage, we look at the graph of Cs − V and we know that at V = VT ,

Cs = 2Cdep,min . This gives us the following results:

– NA = 5 × 1016 cm−3 , VT = 0.65 V (TCAD).

– NA = 5 × 1017 cm−3 , VT = 1.5 V (TCAD).

From theory, we know

p
VT = VFB + γ 2ϕF + 2ϕF . (5)

Using this equation and substituting the values of doping and other parameters we get

– NA = 5 × 1016 cm−3 , γ = 0.3729 V0.5 , VT = 0.6735 V (Theory).

– NA = 5 × 1017 cm−3 , γ = 1.1793 V0.5 , VT = 1.5253 V (Theory).

e. The band bending at the onset of inversion is obtained for V = VT for each doping profile

and is graphed in Figure 7.

Fig 7 Band bending at the onset of inversion. The gate voltage applied for NA = 5 × 1016 cm−3 is 0.65 V, while that
for NA = 5 × 1017 cm−3 is 1.5 V.

f. The electric field in the MOS structure at the onset of inversion is plotted in Figure 8.

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 – For NA = 5 × 1016 cm−3 , the electric field in the oxide is 3.37 × 105 V/cm, while that

at the surface of the semiconductor is 1.2 × 105 V/cm.

– For NA = 5 × 1017 cm−3 , the electric field in the oxide is 1.13 × 106 V/cm, while that

at the surface of the semiconductor is 3.71 × 105 V/cm.

Fig 8 Electric field in the MOS structure at the onset of inversion.

Part II: N-MOSFET

The meshed MOSFET structure is shown in Figure 9.

1. Band bending in equilibrium

The band bending of the MOSFET in equilibrium for both gate lengths is shown in Figure 10. As

expected when VG = 0 V, there are very few inversion charge carriers and thus the MOSFET is in

off-state. Also because VDS = 0 V, there is no band difference in the Fermi level across the length

of the device.

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 0

0.5
Y

DopingConcentration [cm^-3]
1.000e+20

4.135e+17

1.710e+15
1.5
7.036e+12

-8.521e+12

-2.068e+15

-5.000e+17

-1 -0.5 0 0.5 1
X

Fig 9 Meshed MOSFET structure for the simulation results reported in this project.

Fig 10 Band bending in MOSFET of different lengths in equilibrium.

2. Transfer curves of the device

The transfer curves of the devices are shown in Figure 11. It can be seen from the figure that the

500-nm gate length device behaves better with a better on-off ratio for all VDS values, while the

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100-nm gate length device shows degraded behavior. Moreover, the degradation in the electrical

transport characteristics of the 100-nm gate length device increases at higher VDS values.

Fig 11 Transfer curves of the device at different VDS values.

3. Subthreshold swing extraction

The subthreshold swing tells us the amount of gate voltage change needed to change the drain

current by a factor of 10× in the sub-threshold regime. The results from TCAD simulations are

given below.
LG VD = 0.05 V VD = 1 V VD = 2 V
500 nm 110 mV/decade 110 mV/decade 110 mV/decade
100 nm 114 mV/decade 127 mV/decade 274 mV/decade
Table 1 Subthreshold swing for different gate length devices as a function of drain bias.

4. Threshold voltage extraction

The threshold voltage is extracted as the gate bias for which the drain current is 100 nA/µm. The

results from TCAD simulations are presented in the table below. In the case of short-channel

device, at high VDS the device does not turn off due to substrate leakage. This means that the

depletion region at the drain end widens and overlaps with the depletion region at the source end

causing punch through.

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 LG VD = 0.05 V VD = 1 V VD = 2 V
500 nm 1.46 V 1.46 V 1.46 V
100 nm 0.94 V 0.6 V N/A
Table 2 Threshold voltage extracted from transfer curves.

5. Drain-induced barrier lowering (DIBL)

The DIBL manifests as a negative shift along the gate voltage axis of the transfer curves as VDS

increases. This happens when the voltage applied at the drain end influences the potential barrier

between the source contact and the gated region of the channel. In the ideal case, the potential

barrier at the source-channel side should be fully controlled by the gate. But as the transistor

length reduces, the drain starts to reduce this source-side potential barrier. This effectively reduces

the threshold voltage of the device at higher drain bias.

In the case of LG = 500 nm, there is virtually no DIBL and hence the VT remains unaffected

by VDS , while in the case of short-channel device, VT reduces drastically with VDS and eventually

for large VDS , the device suffers from punchthrough.

6. Peak transconductance

The transconductance versus VGS at VDS = 2 V is plotted in Figure 12.

Fig 12 Transconductance versus gate voltage at 2 V drain bias.

From the figure we can read the peak value of the transconductance of both devices

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 peak
• LG = 500 nm, gm = 1586 S/m at VGS = 2 V and VDS = 2 V.

peak
• LG = 100 nm, gm = 92.1 S/m at VG = 2 V.

7. Output curves of the device

The output curves of the long channel device are shown in Figure 13, while the output curves of

the short channel device are shown in Figure 14. The main difference between the two curves is

that for the short channel device, the MOSFET action is completely lost due to punch through and

the device tends to act like a double-sided diode. This is shown in Figure 15.

Fig 13 Output curves of the long-channel (LG = 500 nm) device.

Fig 14 Output curves of the short-channel (LG = 100 nm) device.

8. Saturation current density

We define the saturation current at VDS = 2 V for each VGS value for the 500-nm gate-length device.

• VGS = 0.1 V, IDSAT = 1.92 × 10−10 A/m (device is still in subthreshold regime).

11
 1e+19

Charge Density (cm^-3)

1e+13

1e+7

10 Electron
Space Charge

-0.2 0 0.2
X (um)

Fig 15 Space charge at the S/D overlapping for 100 nm device at VGS = 0 V and VDS = 2 V.

• VGS = 1 V, IDSAT = 4.74 × 10−6 A/m (device is still in subthreshold regime).

• VGS = 2 V, IDSAT = 23 A/m

Since the 100-nm gate length device is dominated by depletion-related effects and does not show

saturation characteristics, we choose not to report its saturation current density.

9. Output conductance

The output conductance curves of the long channel device are shown in Figure 16, while the output

curves of the short channel device are shown in Figure 17.

The output conductance in the linear regime is quite low for VGS = 0.5 V and VGS = 1 V for

500-nm gate-length device. This is because the device is still turned off. The transconductance

increases in magnitude in the linear regime when VGS = 2 V as the device is on. For all gate

voltages, the transconductance goes to nearly zero when the 500-nm gate-length device enters

saturation.

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 Fig 16 Output conductance curves of the long-channel (LG = 500 nm) device.

The behavior of the 100-nm gate-length device is quite different. As the transistor action is lost

in this case, we do not get the expected transconductance curves. Because the device behaves like

a double-sided diode, we see that like output conductance increases as VDS increases.

Fig 17 Output conductance curves of the short-channel (LG = 100 nm) device.

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