Ex. No.
: 6 Design, Simulation and Implementation of 4-bit Ripple Carry Adder
Date: 24|10|2025 and 4-bit Array Multiplier using Verilog HDL
AIM:
To design, simulate and implement 4-bit Ripple Carry Adder (RCA) and 4-bit Array Multiplier
on Xilinx FPGA hardware using Verilog Hardware Description Language (HDL).
SOFTWARE/HARDWARE REQUIRED:
Simulation tool: Xilinx Vivado 2015.3
Hardware: Zedboard Zynq 7000 Development Board
a) 4-bit Ripple Carry Adder
I. Truth Table
a[3:0] Decimal b[3:0] Decimal Sum [4:0] Decimal
a3 a2 a1 a0 Equi. b3 b2 b1 b0 Equi. Cout S3 S2 S1 S0 Equi.
0 1 1 1 7 1 0 0 0 8 0 1 1 1 1 15
1 0 1 0 10 1 1 0 0 12 1 0 1 1 0 22
1 0 1 1 11 0 0 1 1 3 0 1 1 1 0 14
1 1 1 0 14 1 1 0 1 13 1 1 0 1 1 27
II. Logic Diagram
Simulation
RTL Schematic
Verilog HDL
Full Adder
`timescale 1ns/1ps
module full_adder (input A, B, Cin,output Sum, Cout);
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (B & Cin) | (A & Cin);
endmodule
Ripple Carry Adder
`timescale 1ns/1ps
module ripple_carry_adder_4bit (input [3:0] A, B, input Cin, output [3:0] Sum, output Cout, output [4:0]
total);
wire C1, C2, C3;
full_adder FA0 (.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(C1));
full_adder FA1 (.A(A[1]), .B(B[1]), .Cin(C1), .Sum(Sum[1]), .Cout(C2));
full_adder FA2 (.A(A[2]), .B(B[2]), .Cin(C2), .Sum(Sum[2]), .Cout(C3));
full_adder FA3 (.A(A[3]), .B(B[3]), .Cin(C3), .Sum(Sum[3]), .Cout(Cout));
assign total = {Cout, Sum};
endmodule
Testbench
`timescale 1ns/1ps
module tb_ripple_carry_adder_4bit;
reg [3:0] A;
reg [3:0] B;
reg Cin;
wire [3:0] Sum;
wire Cout;
wire [4:0] total;
ripple_carry_adder_4bit uut (.A(A),.B(B),.Cin(Cin),.Sum(Sum),.Cout(Cout),.total(total));
initial begin
Cin = 0;
A = 4'b0111; B = 4'b1000; #10;
A = 4'b1010; B = 4'b1100; #10;
A = 4'b1011; B = 4'b0011; #10;
A = 4'b1110; B = 4'b1101; #10;
$finish;
end
endmodule
RTL Schematic
Constraints File
‘Implemented Device
b) 4-bit Array Multiplier
I. Truth Table
Multiplicand Multiplier b[3:0] Product [7:0]
Decima Decimal Decimal
a[3:0]
l Equi. Equi. Equi.
a3 a2 a1 a0 b3 b2 b1 b0 p7 p6 p5 p4 p3 p2 p1 p0
0 1 0 1 5 1 1 0 0 12 0 0 1 1 1 1 0 0 60
0 1 1 1 7 1 1 1 0 14 0 1 1 0 0 0 1 0 98
1 1 1 1 15 1 1 1 0 14 1 1 0 1 0 0 1 0 210
1 1 1 1 15 1 1 1 1 15 1 1 1 0 0 0 0 1 225
II. Logic Diagram
Simulation
RTL Schematic
Verilog HDL
Half Adder
module half_adder (input A, B,output Sum, Carry);
assign Sum = A ^ B;
assign Carry = A & B;
endmodule
Array Multiplier
`timescale 1ns / 1ps
module array_multiplier_4bit (input [3:0] A, [3:0] B,output [7:0] P);
wire [15:0] PP;
assign PP[0] = A[0] & B[0];
assign PP[1] = A[1] & B[0];
assign PP[2] = A[2] & B[0];
assign PP[3] = A[3] & B[0];
assign PP[4] = A[0] & B[1];
assign PP[5] = A[1] & B[1];
assign PP[6] = A[2] & B[1];
assign PP[7] = A[3] & B[1];
assign PP[8] = A[0] & B[2];
assign PP[9] = A[1] & B[2];
assign PP[10] = A[2] & B[2];
assign PP[11] = A[3] & B[2];
assign PP[12] = A[0] & B[3];
assign PP[13] = A[1] & B[3];
assign PP[14] = A[2] & B[3];
assign PP[15] = A[3] & B[3];
wire S1, S2, S3, S4, S5, S6, S7, S8, S9, S10;
wire C1, C2, C3, C4, C5, C6, C7, C8, C9, C10;
assign P[0] = PP[0];
half_adder HA1 (PP[1], PP[4], P[1], C1);
full_adder FA1 (PP[2], PP[5], PP[8], S1, C2);
half_adder HA2 (S1, C1, P[2], C3);
full_adder FA2 (PP[3], PP[6], PP[9], S2, C4);
full_adder FA3 (S2, C3, PP[12], S3, C5);
half_adder HA3 (S3, C2, P[3], C6);
Synthesis Schematic
Utilisation Table
full_adder FA4 (PP[7], PP[10], PP[13], S4, C7);
full_adder FA5 (S4, C4, C5, S5, C8);
half_adder HA4 (S5, C6, P[4], C9);
full_adder FA6 (PP[11], PP[14], C7, S6, C10);
full_adder FA7 (S6, C8, C9, P[5], P[6]);
full_adder FA8 (PP[15], C10, P[6], P[7], );
endmodule
Testbench
`timescale 1ns / 1ps
module tb_array_multiplier_4bit;
reg [3:0] A;
reg [3:0] B;
wire [7:0] P;
array_multiplier_4bit uut (.A(A),.B(B),.P(P));
initial begin
A = 4'b0101; B = 4'b1100; #10;
A = 4'b0111; B = 4'b1110; #10;
A = 4'b1111; B = 4'b1110; #10;
A = 4'b1111; B = 4'b1111; #10;
$finish;
end
endmodule
Result
Thus the design, simulation and implementation of 4-bit Ripple Carry Adder (RCA) and 4-bit Array
Multiplier on Xilinx FPGA hardware using Verilog Hardware Description Language (HDL) and its output was
verified successfully.
