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Static and Dynamic Checks

The document outlines the usage of Spectre APS/XPS for static and dynamic design checks to identify common design issues such as high-impedance nodes and DC leakage paths. It details the prerequisites for using these checks, the differences between static and dynamic checks, and provides a comprehensive list of checks available, along with examples of their application. The document also includes instructions for running simulations and interpreting the results in XML format.

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Static and Dynamic Checks

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Static and Dynamic Checks

Rapid Adoption Kit (RAK)

Product Version: Spectre 23.1.0

June 2023
Copyright Statement

© 2023 Cadence Design Systems, Inc. Cadence and the Cadence logo are registered trademarks of
Cadence Design Systems, Inc. All others are the property of their respective holders.

This content is Cadence Confidential and for Cadence customers only. DO NOT DISTRIBUTE.

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Contents
Purpose.......................................................................................................................... 5
Prerequisites .................................................................................................................. 5
Introduction .................................................................................................................... 5
Use Model ...................................................................................................................... 8
Workshop Exercise for Static Checks ........................................................................... 9
1. Static High-Impedance Node Check: Filtering by xsubckt .................................... 9
2. Static DC Leakage Path Check ........................................................................... 14
3. Static NMOS Forward-Bias Voltage Check ......................................................... 15
4. Static Voltage Domain Check .............................................................................. 17
5. Static Transmission Gate Check ......................................................................... 19
6. Static Always-Conducting NMOSFET Check ...................................................... 20
7. Static MOSFET Voltage Check ........................................................................... 21
8. Static Resistor/Capacitor Voltage Check ............................................................. 23
9. Static Diode Voltage Check ................................................................................. 24
10. Static Capacitor and Resistor Check ................................................................. 25
11. Static ERC Check: floatgate .............................................................................. 28
12. Static ERC Check: floatbulk ............................................................................... 29
13. Static ERC Check: hotwell ................................................................................. 30
14. Static ERC Check: dangle ................................................................................. 31
15. Static ERC Check: gate2power ......................................................................... 32
16. Static ERC Check: rmax .................................................................................... 34
17. Static RC Delay Check ...................................................................................... 36
18. Static RC Delay Check – Backannotation ......................................................... 39
19. Static Stack Check ............................................................................................. 40
20. Static Coupling Impact Check ............................................................................ 43
Workshop Exercise for Dynamic Checks .................................................................... 47
1. Dynamic High-Impedance Node Check: Region Based ...................................... 47
2. Dynamic High-Impedance Node Check: Filtering by Subckt............................... 51
3. Dynamic High-Impedance Node Check: Debugging Utility ................................. 54
4. Dynamic DC Leakage Current Path Check: Transient Based............................. 58
5. Dynamic DC Leakage Current Path Check: Common Mistake ........................... 63
6. Dynamic Floating-Node-Induced DC Leakage Path Check: Transient Based .... 65
7. Dynamic MOSFET Voltage Check ...................................................................... 70
8. Dynamic MOSFET Voltage Check: extreme ....................................................... 73
9. Dynamic Resistor/Capacitor Voltage Check ........................................................ 76
10. Dynamic Diode Voltage Check .......................................................................... 78
11. Dynamic Excessive Element Current Check ..................................................... 79
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Static and Dynamic Checks: RAK

12. Dynamic Excessive Rise and Fall Time Check ................................................. 80

13. Dynamic Glitch Check........................................................................................ 87
14. Dynamic Setup and Hold Check ........................................................................ 89
15. Dynamic Setup and Hold Check: Scoping ......................................................... 94
16. Dynamic Noisy Node Check .............................................................................. 96
17. Dynamic Node Capacitance Check ................................................................... 97
18. Dynamic Subckt Port Power Check ................................................................... 98
19. Dynamic Subckt Port Power Check: Tree Based ............................................ 100
20. Dynamic Pulse Width Check ........................................................................... 101
21. Dynamic Power Density Check ....................................................................... 104
22. Dynamic Active Node Check ........................................................................... 105
23. Dynamic Subckt Instance Activity Check ........................................................ 108
24. Dynamic Subckt Port Voltage/Current Check.................................................. 109
25. Dynamic Delay Check...................................................................................... 109
26. Stop Simulation with the First Violation ........................................................... 113
Workshop Exercise for Dynamic Check Based on Leakage Analysis ...................... 114
1. Dynamic DC Leakage Current Path Check: leaki Based .................................. 117
2. Dynamic Floating-Gate-Induced Leakage Check: Possible-Case Current ....... 120
3. Dynamic Floating-Gate-Induced Leakage Check: Worst-Case Current ........... 123
4. Dynamic Floating-Gate-Induced Leakage Check: Worst-Case Current:
sweep=single: distribute......................................................................................... 126
5. Dynamic Floating-Gate-Induced Leakage Check: Filtering Path Per Floating
MOSFET ................................................................................................................ 129
6. Dynamic Floating-Gate-Induced Leakage Check: Filtering Path Per Floating
Node ....................................................................................................................... 131
7. Dynamic Floating-Gate-Induced Leakage Check: Filtering Diode-Connected
Nodes ..................................................................................................................... 133
8. Dynamic Floating-Gate-Induced Leakage Check: Debugging Utility ................ 134
Workshop Exercise for Dynamic Floating Node Statistical Check ............................ 137
1. Dynamic Floating Node Statistical Check: Worst-Case Current ....................... 139
Appendix: Floating Node Detection ........................................................................... 144
Appendix: Ground Node in Virtuoso .......................................................................... 145
Support ...................................................................................................................... 147
Feedback ................................................................................................................... 147

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Purpose
This RAK describes the usage of Spectre APS/XPS static and dynamic design checks.
These checks may be used to identify typical design problems including high-
impedance nodes, DC leakage paths, extreme rise and fall times, excessive device
currents, setup and hold timing errors, voltage domain issues, and connectivity
problems. While static checks are basic topology checks, dynamic checks are
performed during a Spectre APS/XPS transient simulation.

Prerequisites
Basic working knowledge of running simulations with Spectre using command line.

Introduction
Circuit checks enable you to analyze design problems, such as high-impedance nodes,
leakage paths between power supplies, timing errors, power issues, connectivity
problems, and extreme rise and fall times. These checks can be separated into dynamic
and static checks. Dynamic checks are performed during transient simulation. Static
checks are topology checks, which do not require any simulation.

This workshop introduces all dynamic and static checks available in Spectre.

Static checks are performed after the voltage-propagation technique is applied on the
topology of a circuit. It is important to note that the voltage-propagation technique does
not require a transient simulation. Therefore, a static check is faster than a dynamic
check. A static check gives the worst case possible for a given scenario. Static checks
use the static_ keyword prefix, and write the results into a file with the.static.xml
extension. The xml file can be viewed with any web browser.

Dynamic checks are performed during the transient simulation. Therefore, their result
depends on the stimuli applied to the design. Dynamic checks use the dyn_ keyword
prefix, and write the result into a file with the .dynamic.xml extension. The xml file
can be viewed with any web browser.

The default output format of all circuit checks is xml. Therefore, the output files have a
.xml extension and are located in the raw directory. You can use the check_format
parameter with the options statement to output in text format, as shown below:

opt options check_format=text (Spectre format)

.option check_format=text (SPICE format)

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Then text format have the .rpt extension and are located in the raw directory. The
prefix of these files is the same as the prefix of xml files.

All design checks can be applied either globally to the entire design or locally to specific
blocks of a design. The scoping options are available to define the scope of each design
check. The design checks can be applied to a specific subcircuit instance (inst), or to
all instances of a subcircuit definition (subckt). Exclusion of a specific subcircuit
instance (xinst) or all instances of a subcircuit (xsubckt) is supported. All scoping
options support wildcards, and the hierarchy level of the scope can be defined by the
depth option. For further details on scoping, check the Spectre User Manual or use the
“% spectre -h” command.

For full list of static and dynamic checks supported by Spectre, see Spectre User
Manual.

There are two approaches to run dyn_dcpath and dyn_floatdcpath. The first
approach is transient-analysis-based, which is enabled by the
duration/time_window parameters. The second approach is leakage-analysis-
based, which is enabled by the leaki_times parameter. Only one approach can be
enabled per check statement. If both approaches are mentioned (for example,
dyn_dcpath duration=5n time_window=[1u 6u] leaki_times=[3u] …), the
leakage-analysis approach will be enabled and the transient-analysis approach will be
ignored. If none is mentioned (for example, dyn_dcpath …), the transient-analysis
approach will be enabled and the leakage-analysis approach will be ignored.
Table 1: Transient and leakage analysis-based approaches

Spectre, Spectre Spectre Spectre

Spectre XPS XPS XPS MS
APS, SPICE FASTSPICE
Spectre X (SRAM,
DRAM,
Flash)
Dynamic DC Leakage Current Path Check
(dyn_dcpath) – Transient-analysis-based Yes Yes Yes Yes
Dynamic DC Leakage Current Path Check
(dyn_dcpath) – Leakage-analysis-based
Yes Yes Yes No
Dynamic Floating-Gate-Induced Leakage Check
(dyn_floatdcpath) – Transient-analysis-based Yes Yes No No
Dynamic Floating-Gate-Induced Leakage Check
(dyn_floatdcpath) – Leakage-analysis-based Yes Yes Yes Yes

The first approach is shown in section Workshop Exercise for Dynamic Checks. The
second approach is shown in section Workshop Exercise for Dynamic Check Based on
Leakage Analysis.

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The commands for running different modes in Spectre are shown below. In this
workshop, you may try different modes for different checks.

1. Spectre®

% spectre netlist.scs

2. Spectre® APS

% spectre +aps netlist.scs

3. Spectre® X

% spectre +preset=ax netlist.scs

4. Spectre® XPS SPICE

% spectre +xps=s netlist.scs

5. Spectre® XPS FASTSPICE: SRAM

% spectre +xps +cktpreset=sram netlist.scs

6. Spectre® XPS FASTSPICE: FLASH

% spectre +xps +cktpreset=flash netlist.scs

7. Spectre® XPS MIXED SIGNAL

% spectre +ms netlist.scs

If the netlist is in Spice format, add +spice in the command line.

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Use Model
The syntax used by static and dynamic checks can be characterized by the following
Spectre syntax. The Spice syntax is not supported.

Syntax:

Name check_keyword <parameter=value>

Examples:

static_hz1 static_highz node=[*]

static_dc1 static_dcpath net=[vdd gnd]
sta_nmosb1 static_nmosb model=[nmos]
dyn_hz1 dyn_highz node=[*] duration=2n time_window=[1n 20n]

The key parameters are:

1. net: Defines the net to which a check is applied. Net is the full hierarchical name
from the top level.
2. node: Defines nodes to which a check is applied. Node does NOT need to be a
full hierarchical name from the top level. The check will try to match the node
name in all subcircuits.
3. model: Defines device model definitions to which a check is applied.
4. time_window: Defines a time window in which a check needs to be performed.
5. duration: Defines a time limit over which a violation is reported.

The default value for each parameter is dependent on the individual design check used
in the netlist. Run spectre –h followed by the checker keyword to get detailed
information on each design check.

Example:

% spectre –h static_dcpath

% spectre –h dyn_highz

The next sections demonstrate static and dynamic checks. Notice that for each check,
its corresponding netlist <netlistName> is located in the subdirectory named by
<netlistName>.

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Workshop Exercise for Static Checks

In this section, different static checks are introduced and applied to simple circuits with
their outputs shown.

1. Static High-Impedance Node Check: Filtering by xsubckt

The purpose of this section is to get familiar with the xsubckt parameter. Some
nodes are known to be always in highz. Therefore, a mechanism is needed to
exclude such nodes from the check.

Action 1: Open the static_highz.sp netlist, and review the circuit and the
design check statement.

static_hz1 static_highz node=[*]

The above statement checks for all nodes.

static_hz2 static_highz node=[*] xsubckt=[buff1]

The above statement checks for all nodes except nodes in the “buff1” subckt.
All instances of the “buff1” subckt will be skipped.

static_hz3 static_highz node=[*] xsubckt=[inverter]

The above statement checks for all nodes except nodes in the “inverter”
subckt. All instances of the “inverter” subckt will be skipped.

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Figure 1

The top-level circuit is shown in Figure 1. Notice that X1 and X3.X1 are
instances of the “buff1” subckt. Further, X4 is an instance of the “inverter”
subckt.

Figure 2

The “buff1” and “buff2” subckts are shown above with the highz node in red.

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Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_highz.sp

Action 3: Open the static_highz.static.xml result file with a web browser.

The first statement will check all nodes and will report those nodes with highz.

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The second statement will check all nodes except the nodes inside X1 and
X3.X1.

The third statement will check all nodes except the nodes inside X4. It is
important to note that port “out” of subckt X4 is connected to “out4” in the top
level. Therefore, “out4” does not contain X4 in its hierarchical name. Hence,
“out4” is not excluded. In general, ports of any subckt cannot be excluded with
the xsubckt parameter.

Since there are no internal nodes in X4, there is nothing to exclude. Hence, the
reports between static_hz1 and static_hz3 will match.

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Action 4: Open the static_highz.static.rpt text report file.

All statements in the .rpt file are shown below:

Notice that the first column shows an Id for each violation.

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2. Static DC Leakage Path Check

Action 1: Open the static_dcpath.sp netlist, and review the circuit and the
design check statement.

dc1 static_dcpath net=[vdd 0]

The above statement checks for any leakage path between vdd and 0.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_dcpath.sp

Action 3: Open the static_dcpath.static.xml result file with a web browser.

The result file reports a DC leakage path between vdd and 0 through the
elements x3.mp1 and x3.mn2. Check the connectivity of this path. Fix the
connectivity to resolve the problem.

The net parameter should contain at least two nets.

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Static and Dynamic Checks: RAK

3. Static NMOS Forward-Bias Voltage Check

Action 1: Open the static_nmosb.sp netlist, and review the circuit and the
design check statement.

nmosb1 static_nmosb model=nmos

The above statement checks for any NMOS device defined by model nmos with
a forward-biased bulk condition. A violation is generated when the bulk-bias
voltage meets the following conditions:

• When 'mode' = 'definite':

min( Vb ) >= min( Vd, Vs ) + abs( vt )

• When 'mode' = 'possible':

max( Vb ) >= min( Vd, Vs ) + abs( vt )

Here, Vt is the threshold for the p-n junction being checked. If the user does not
specify either mode or Vt, the default values will be used, which are “definite”
and 0.3V, respectively.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_nmosb.sp

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Action 3: Open the static_nmosb.static.xml result file with a web browser.

The result file reports that NMOS device x1.mn1 has a forward-biased bulk. This
is because the following condition is true:

min( Vb ) >= min( Vd, Vs ) + abs( vt )

3 >= 0 + 0.3 is true.

Check the bulk connection of this NMOS device and fix it. You may create a
similar test case to test the static_pmosb check, which is for PMOS devices.

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4. Static Voltage Domain Check

Action 1: Open the static_voltdomain.sp netlist, and review the circuit and the
design check statement.

chk1 static_voltdomain model=[*]

This voltage domain check analyzes if a device is connected to the wrong

voltage domain. This check can be used to analyze if a low-voltage device has a
conducting path to a high-voltage power supply, or if a high-voltage device has a
conducting path to a low-voltage power supply.

In this netlist, the “nmos_thin” and “pmos_thin” device models are low-voltage
(thin oxide) devices, which should only be connected to low-voltage power
supplies. Moreover, the “nmos_thick” and “pmos_thick” device models are
high-voltage (thick oxide) devices, which should only be connected to high-
voltage power supplies.

Using model=[*], all MOSFET instances are checked.

The check determines the vmin/vmax values for each node using voltage
propagation from the voltage sources, and compares the vmax values at the
MOSFET terminals.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_voltdomain.sp

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Action 3: Open the static_voltdomain.static.xml result file with a web

browser.

The check reports that the X1.MN2 (model=nmoslo) and X1.MP2

(model=pmoslo) devices are connected to a high-voltage node called out_1.
Therefore, it is a “HighV driving LowV” violation.

Notice that the “Subckt Name” is the name of subckt in which the X1.MN2
instance resides. This helps locate level-shifters. If the instance is at the top
level, the “Subckt Name” will be N/A.

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5. Static Transmission Gate Check

Action 1: Open the static_tgate.sp netlist, and review the circuit and the
design check statement.

tgate1 static_tgate node=[*]

Typically, a transmission gate consists of a combination of an NMOS and a

PMOS device. Nevertheless, if one of the devices is missing, it may cause a
leakage current in the driven stage. This feature checks for any such missing
MOSFET in a transmission gate, which may cause a leakage current between
power supplies.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_tgate.sp

Action 3: Open the static_tgate.static.xml result file with a web browser.

The result file reports that both in2 and in4 nodes are driven by only one
device. The stage driven by these nodes may create leakage paths between
power supplies. Check the connectivity of the reported nodes, and analyze the
transmission gate problem. Add the missing devices and run the check again.

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6. Static Always-Conducting NMOSFET Check

Action 1: Open the static_nmosvgs.sp netlist, and review the circuit and the
design check statement.

mos1 static_nmosvgs model=nmos vt=0.5

The above statement checks for any NMOS device, with model nmos, which is
always in “on” state. The NMOS device is considered to be in “on” state if the
following condition is satisfied:

min(Vg) > min (Vs/Vd) + abs(vt)

Here, Vt is the MOSFET threshold voltage set by the user.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_nmosvgs.sp

Action 3: Open the static_nmosvgs.static.xml result file with a web browser.

The result file reports that NMOS device x2.mn2 is fulfilling the “always on”
condition. Check the connectivity of the device to understand this check. You
may create a similar case to test the static_pmosvgs check for PMOS
devices.

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7. Static MOSFET Voltage Check

Action 1: Open the static_mosv.sp netlist, and review the circuit and the design
check statements.

mos1 static_mosv model=["nmos"] cond="v(g,s)>1.9"

The above statement checks for any MOSFET device with the model nmos that
has a voltage difference between gate and source greater than 1.9V.

mos2 static_mosv model=[*] cond="v(d)>1.9"

Similarly, the above statement checks for any MOSFET device that has a voltage
greater than 1.9V at its drain terminal.

mos3 static_mosv model=[*] cond="w<30e-6"

The above statement checks for any MOSFET device that has a width less than
30um.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_mosv.sp

Action 3: Open the static_mosv.static.xml result file with a web browser.

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The first check reports that two devices, x1.mn2 and x2.mn2, have v(g,s)
greater than 1.9V. The second check reports that x1.mn2 and x1.mp1 have a
drain voltage greater than 1.9V. The third check reports that x1.m2 and x2.m2
have a width less than 30um.

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8. Static Resistor/Capacitor Voltage Check

Action 1: Open the static_resv_capv.sp netlist, and review the circuit and the
design check statement.

resv1 static_resv cond="v(1,2)>0"

The above statement checks for any resistor that has a voltage greater than 0V
across its terminals.

capv1 static_capv cond="v(1,2)>0"

Similarly, the above statement checks for any capacitor that has a voltage
greater than 0V across its terminals. Here, “1” stands for the positive terminal
and “2” stands for the negative terminal of an element.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_resv_capv.sp

Action 3: Open the static_resv_capv.static.xml result file with a web

browser.

The result file reports that resistor r1 has a voltage greater than 0V.

Similarly, it reports that capacitor c1 has a voltage greater than 0V.

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9. Static Diode Voltage Check

Action 1: Open the static_diodev.sp netlist, and review the circuit and the
design check statement.

dv1 static_diodev model=["diode1"] cond="v(a,c)>=0.5"

The above statement checks for any diode with the model name “diode1” that
has a voltage greater than 0V across its terminals.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_diodev.sp

Action 3: Open the static_diodev.static.xml result file with a web browser.

The result file reports that the x1.d1 and x1.d2 diodes have a voltage greater
than 0.5V.

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10. Static Capacitor and Resistor Check

Action 1: Open the static_res_cap.sp netlist, and review the circuit and the
design check statements.

chk1 static_resistor type=distr

chk2 static_resistor type=print rmin=1k rmax=1M

chk3 static_capacitor type=distr

chk4 static_capacitor type=print cmin=1p cmax=1u

The static_capacitor check reports capacitors outside or within the range

defined by cmin and cmax. For example, if type is set to range, the check will
report each capacitor outside the range of cmin and cmax (capacitor < cmin
OR capacitor > cmax). If type is set to print, the check will print a report of
each capacitor within the range of cmin and cmax (cmin <= capacitors <=
cmax). If type is set to distr, the check will print a distribution (or statistical)
report.

Similarly, the static_resistor check follows the same behavior for resistors,
but with rmin and rmax.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_res_cap.sp

 Open the static_res_cap.static.xml result file with a web browser.

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 The first statement with type=distr will print a report in the xml file, as
shown below:

The second statement with type=print will print a report in the xml file, as
shown below:

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Similarly, the third and fourth statements will print a report for capacitors in the
xml file, as shown below:

Notice that the device names can be sorted by clicking the cell highlighted in the
red box.

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11. Static ERC Check: floatgate

Action 1: Open the static_erc_floatgate.scs netlist, and review the circuit
and the design check statement.

chk1 static_erc floatgate=all

The above statement checks all MOSFETs and reports if their gates are floating.
A gate is considered floating if a voltage cannot propagate to that gate.

Action 2: Run the netlist with Spectre APS.

% spectre +aps static_erc_floatgate.scs

Action 3: Open the result file, static_erc_floatgate.static.xml, with a web

browser.

In this example, the check reports three ERC floating-gate violations. Check the
circuit to determine the reasons for these violations.

Note that if floatgate=no_top is specified, MP1 will not be reported because

MP1 is a top-level transistor. Read the other checks with different floatgate
parameters given in the netlist and their corresponding reports in
static_erc_floatgate.static.xml.

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12. Static ERC Check: floatbulk

Action 1: Open the static_erc_floatbulk.scs netlist, and review the circuit
and the design check statement.

chk1 static_erc floatbulk=all

The above statement checks all MOSFETs and reports if their bulks are floating.
A bulk is considered floating if a voltage cannot propagate to that bulk.

Action 2: Run the netlist with Spectre APS.

% spectre +aps static_erc_floatbulk.scs

Action 3: Open the result file, static_erc_floatbulk.static.xml, with a web

browser.

In this example, the check reports four ERC float-bulk violations. Check the
circuit to determine the reason for these violations.

Note that if floatbulk=no_top is specified, MN1 and MP1 will not be reported
because both are in a top-level netlist. Check the second check with
floatbulk=no_top given in the netlist and its corresponding reports in
static_erc_floatbulk.static.xml.

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13. Static ERC Check: hotwell

Action 1: Open the static_erc_hotwell.scs netlist, and review the circuit and
the design check statement.

chk1 static_erc hotwell=on

The above statement checks all MOSFETs and reports if their bulks are not
connected to either VDD or GND.

Action 2: Run the netlist with Spectre APS.

% spectre +aps static_erc_hotwell.scs

Action 3: Open the result file, static_erc_hotwell.static.xml, with a web

browser.

In this example, the check reports two ERC hotwell violations. Check the circuit
to determine the reason for these violations.

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14. Static ERC Check: dangle

Action 1: Open the static_erc_dangle.scs netlist, and review the circuit and
the design check statement.

chk1 static_erc dangle=all

The above statement checks all nodes of all MOSFETs and reports dangling
nodes. A node is considered dangling if a voltage cannot propagate to that node.

Action 2: Run the netlist with Spectre APS.

% spectre +aps static_erc_dangle.scs

Action 3: Open the result file, static_erc_dangle.static.xml, with a web

browser.

In this example, the check reports six ERC dangling-node violations. Check the
circuit to determine the reason for these violations. Notice that the voltage cannot
propagate to these six nodes, causing them to dangle.

Note that if dangle=no_top is specified, the dan1, dan2, and dan3 nodes will
not be reported because they are in a top-level netlist. Check the second check
with dangle=no_top given in the netlist and its corresponding reports in
static_erc_dangle.static.xml.

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15. Static ERC Check: gate2power

Action 1: Open the static_erc_gate2power.scs netlist.

Review the circuit and the design check statement.

chk1 static_erc gate2power=on vlth=0.1 vhth=1.0

The above statement checks all gates of all MOSFETs and reports PMOS
connected to GND or NMOS connected to VDD. A voltage source is considered as
VDD if its voltage is above vhth. A voltage source is considered GND if its voltage
is below vlth.

Action 2: Run the netlist with Spectre APS.

% spectre +aps static_erc_gate2power.scs

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Action 3: Open the result file, static_erc_gate2power.static.xml, with a

web browser.

In this example, the check reports that the NMOS, MN2, is connected to gate
voltage of 1.1 and the PMOS, MP1, is connected to gate voltage of 0. Check the
circuit to determine the reason for these violations.

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16. Static ERC Check: rmax

Action 1: Open the static_erc_rmax.scs netlist, and review the circuit and the
design check statements.

chk1 static_erc floatgate=all rmax=1k

chk2 static_erc floatgate=all

The above statements check all nodes of all MOSFETs and report floating gates.
A node is considered floating if a voltage cannot propagate to that node. The
voltage cannot propagate through those resistors whose resistance is more than
rmax. The default value for rmax is 100M ohms.

Action 2: Run the netlist with Spectre APS.

% spectre +aps static_erc_rmax.scs

Action 3: Open the result file, static_erc_rmax.static.xml, with a web

browser.

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The first check reports two ERC floating-gate violations. Check the circuit to
determine the reason for these violations. Notice that the voltage cannot
propagate to the gates of MOSFETs Q1.MN1 and Q1.MP1 because voltage
cannot propagate through resistor Q1.R1, causing them to float. The voltage
cannot propagate through resistor Q1.R1 because its value is larger than
rmax=1k for this first check.

The second check will report no violations because rmax is 100M ohms by
default, and voltage can propagate through all resistors in this circuit. Check the
second check given in the netlist and its corresponding reports in
static_erc_rmax.static.xml.

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17. Static RC Delay Check

The purpose of this section is to get familiar with the check mechanism and the
output report. A trivial example is used to explain the same. The static_rcdelay
check is mostly used in digital designs.

Action 1: Open the static_rcdelay.sp netlist, and review the circuit. The
schematic is shown below:

Figure 3

The design check statement is shown below:

chk_maxnrise1 static_rcdelay node=[*] maxnrise=10

fanoutmargin=[0.2 0.8] cmin=1e-14 detailed_path=yes

chk_maxnfall static_rcdelay node=[*] maxnfall=10

fanoutmargin=[0.2 0.8] cmin=1e-14 detailed_path=no

The above statement reports nodes with extreme rise and fall times. This check
estimates their rise or fall time in terms of charging or discharging. The rise time
is defined as the time taken by the signal from 0.2*VDD to 0.8*VDD. Similarly,
fall time is defined as the time taken by the signal from 0.8*VDD to 0.2*VDD.
Only nodes with ground capacitance more than cmin will be considered.

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maxnrise=10 reports the top ten rise times. maxnfall=10 reports the top ten
fall times. Each check statement shown above will have a separate table and a
separate violation count.

You can also have one check statement with both maxnrise and maxnfall
parameters. In that case, there will be a separate table for each parameter, but
there will be joint violation counts.

At least one parameter is required to run this check.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_rcdelay.sp

Action 3: Open the static_rcdelay.static.xml result file with a web browser.

The first rise-time delay is explained below:

As shown in Figure 3, the rise time of node E is though VDD -> x_r1.mp1 ->
x_r1.mp2 -> E.

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The next two rise-time delays are as follows:

As shown in Figure 3, the rise time of node F is through VDD -> x_d2.mp1 ->
F and VDD -> x_d2.mp2 -> F. In order to see only one path, set
detailed_path to “no”. Setting detailed_path to no will show only the
worst delay for a node, and that is 603p Sec.

The first worst fall time is shown below:

As shown in Figure 3, the fall time of node F is through F -> x_d2.mn1 ->
x_d2.mn2 -> 0.

In all reports, the “Receiver” is the random MOSFET with a gate connection to
the reported “Node”. However, gate capacitance from all receivers are taken in
account. The “Node Cap” is the capacitance of the reported “Node”.
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Static and Dynamic Checks: RAK

18. Static RC Delay Check – Backannotation

The purpose of this section is to get familiar with post-layout support. There are
many post-layout flows, but only the backannotation (stitching) flow is supported with
this check. A decoder example is used to demonstrate this.

The WL decoder circuit has 8 address inputs (AD<7:0>) and 256 outputs
(WL<255:0>). Depending on the input address, only one of the 256 WLs will be
“fired”. In the stimulus setup, AD<7:0> is cycled between 00/h and FF/h. Thus,
WL<0> and WL<255> are fired alternatively.

Action 1: First, run the pre-layout netlist without the stitching flow. Open the
static_rcdelay_post_layout.sp netlist, and review the circuit and the
design check statement.

rc_rise static_rcdelay node=[*] maxnrise=10000

fanoutmargin=[0.2 0.8] cmin=1e-14 detailed_path=no

rc_fall static_rcdelay node=[*] maxnfall=10000

fanoutmargin=[0.2 0.8] cmin=1e-14 detailed_path=no

The above statement reports nodes with extreme rise and fall times.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_rcdelay_post_layout.sp

Action 3: Open the result file, static_rcdelay_post_layout.static.xml,

with a web browser.

The first check reports the following rise-time violations. It will report many
violations. One of the violations is as follows:

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Action 4: Run the stitching flow by enabling the following statement in

static_rcdelay_post_layout.sp:

.option spf='./decoder.spf'

Action 5: Run the netlist with Spectre APS.

% spectre +spice +aps static_rcdelay_post_layout.sp

Action 6: Open the result file, static_rcdelay_post_layout.static.xml,

with a web browser.

It will report more violations than pre-layout because more nodes have spf-cap
stitched to them, which makes the capacitance of the node more than cmin. One
of the violations is as follows:

Notice that the “Node Cap” of Z<19> in the pre-layout and post-layout reports are
0.0761pF and 0.196pF, respectively. This additional capacitance comes from
spf-cap from the spf file.

As a result, the delay has also increased.

19. Static Stack Check

Action 1: Open the static_stack.scs netlist, and review the circuit and the
design check statement.

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Figure 4: Circuit

chk1 static_stack count=2 model=[*]

The above statement counts the MOSFETs (pch and nch) stacked between
power and ground. Any stack having a count of more than 2 will be reported.

Chk2 static_stack count=1 model=[nch]

The above statement counts the nch devices stacked between power and
ground. Any stack having a count of more than 1 will be reported.

Action 2: Run the netlist with Spectre.

% spectre +aps static_stack.scs

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Action 3: Open the result file, static_stack.dynamic.xml, with a web browser.

The above report shows two violations. Each violation shows a stack of
MOSFETs having a count of more than 3.

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The above report shows one violation. It shows a stack of nch devices having a
count of more than 2.

20. Static Coupling Impact Check

The purpose of this section is to get familiar with the static coupling check.

Action 1: Open the static_coupling.sp netlist and review the circuit. The
schematic is shown below:

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Figure 5

The design check statement is shown below:

coup static_coupling node=[*]

The statement reports all victims impacted by aggressors.

Action 2: Run the netlist with Spectre APS.

% spectre +spice +aps static_coupling.sp

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Action 3: Open the result file, static_coupling.static.xml, with a web

browser.

The top violation is as follows:

This report has the following two sections:

a. The first section shows the node name of a victim. Next, the node
capacitance (with respect to ground) of the victim is shown. The min/max
voltage shows the possible voltage range for this node. The coupling
impact is a gauge used to measure the coupling impact of aggressor(s) on
the victim. The coupling impact is a relative term and does not have any
physical meaning.

b. The second section shows the list of aggressors. The min/max voltage
shows the possible voltage range for this node. The coupling instance
name (and its capacitance) is the capacitor connected between this
aggressor and the victim. This section can have multiple rows for multiple
aggressors.

The second violation is as follows:

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The most vulnerable victim is node “victim1” due to the “aggressor” node. It has
the highest coupling impact of 1.666834e+01.

Notice that “victim1” is more impacted as compared to “victim2”. The maximum

voltage values for “victim1” and “victim2” are 0.420096 V and 0.218909 V,
respectively.

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Workshop Exercise for Dynamic Checks

In this section, different dynamic checks are introduced and applied to simple circuits
with their output shown.

1. Dynamic High-Impedance Node Check: Region Based

The definition of Highz node is given in Appendix: Floating Node Detection.

Action 4: Open the dyn_highz_region.scs netlist, and review the circuit and the
design check statement.

Figure 6: Circuit

hz1 dyn_highz node=[*] duration=2n time_window=[0n 20n]

The above statement checks for any high-impedance node in the design with a
duration larger than 2ns, within the time window from 0ns to 20ns.

Action 5: Run the netlist with Spectre.

% spectre dyn_highz_region.scs

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Action 6: Open the result file, dyn_highz_region.dynamic.xml, with a web

browser.

Figure 7: Two PWL sources

Check the connectivity of the devices in the dyn_highz_region.scs netlist.

This simple circuit uses two PWL sources as described in Figure 7. Find out
which node will have high impedance and at what time range. Verify your finding
with the check result.

The result file reports that the out node is a high-impedance node. The violation
happens for the duration of 4.8ns, starting at 5.3ns.

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Figure 8: Region values of MP1 and MN1

The enumerations 0, 1, and 2 correspond to cutoff, triode, and saturation,

respectively.

The conducting rule for NMOS is “Region is triode or saturation”. Therefore, MN1
is in OFF state from 5.3s to 10s and 15.2s to 20s.

The conducting rule for PMOS is “Region is triode or saturation”. Therefore, MP1
is in OFF state from 0s to 10.3s.

Approximate State of MN1 State of MP1 Is node out

Time Window floating?
Region is triode or saturation Region is triode or
saturation

0s to 5s ON OFF No

5s to 10s OFF OFF Yes

10s to 15s ON ON No

15s to 20s OFF ON No

Table 2: State of MN1 and MP1

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Table 2 shows that both MN1 and MP1 are in OFF state from 5s to 10s.
Therefore, the out node is a highz (or floating) node from 5s to 10s.

If you want to know which node has path to VDD or GND, meaning non-highz
node, you can set the inverse parameter to yes.

Table 2 shows that either MN1 or MP1 is in ON state from “0s to 5s” and “10s to
20s” time windows. Therefore, the out node is a non-highz (or not-floating)
node for the duration of 5.2ns, starting from 1.2ns, and for the duration of 9.9ns,
starting from 10.1ns.

The check will report all floating nodes by default, as shown in the hz1 check.
Sometimes, you might be interested only in nodes connected to gates of
MOSFETs. This can be achieved by filtering out such nodes using the fanout
parameter. By setting fanout=gate, only highz nodes connected to gates will
be reported.

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2. Dynamic High-Impedance Node Check: Filtering by Subckt

The purpose of this section is to get familiar with the subckt parameter.
Sometimes, you might be interested in one subcircuit and might want to run (or
scope) the check on one subcircuit.

Action 1: Open the dyn_highz_subckt.scs netlist, and review the circuit and the
design check statement.

hz1 dyn_highz node=[*] duration=2n time_window=[5.2n 9.8n]

The above statement checks for all nodes and ports. Notice the default value of
subckt and inst is *, which means all subcircuits and instances will be
selected.

hz2 dyn_highz node=[*] duration=2n time_window=[5.2n 9.8n]

subckt=[dut]

The above statement checks for all nodes and ports inside all instances of subckt
dut.

hz3 dyn_highz node=[*] duration=2n time_window=[5.2n 9.8n]

inst=[X2]

The above statement checks for all nodes and ports inside instance X2.

Figure 9

The top-level circuit is shown in Figure 8. Notice that X2 is an instance of subckt

dut. All highz nodes are shown in red.
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Static and Dynamic Checks: RAK

Action 2: Run the netlist with Spectre.

% spectre dyn_highz_subckt.scs

Action 3: Open the result file, dyn_highz_subckt.dynamic.xml, with a web

browser.

The first statement will check all nodes and ports.

The second statement will check all nodes and ports of X2. Note that X2 is the
only instance of subckt dut. X2.input1 is a port connected to input at the top
level. The check will report only the top-level node to keep the report short.
Similarly, X2.output3 is a port connected to out3 at the top level.
X2.middle2 is the internal node and will be reported as X2.middle2.

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Since X2 is the only instance of subckt dut, the reports of the second and third
statements are the same.

Note that the specified inst will be matched from the top level. For example,
inst=[X2] will check instance X2 and all its children until depth=8, whereas
inst=[X2.X4] will check instance X2.X4 and all its children until depth=8.

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3. Dynamic High-Impedance Node Check: Debugging Utility

The definition of Highz node is given in Appendix: Floating Node Detection.

Action 1: Open the debugging_utility.scs netlist, and review the circuit and
the design check statement.

Figure 10: Highz debug circuit

hz1 dyn_highz node=[*] duration=2n time_window=[5n 10n]

The above statement checks for any high-impedance node in the design with a
duration larger than 2ns, within the time window from 5ns to 10ns.

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Check the connectivity of the devices in the netlist. This simple circuit uses two
PWL sources as described in Figure 10. Find out which node will have high
impedance and at what time range. Verify your finding with the check result.

Figure 11: Two PWL sources

Action 2: Run the netlist with Spectre.

% spectre +aps debugging_utility.scs

Action 3: Open the result file, debugging_utility.dynamic.xml, with a web

browser.

The result file reports that the net2 node is a high-impedance node. The
violation happens for the duration of 4.7ns, starting at 5.3ns.

Figure 12: Highz debug

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To use the debug utility, a net and time point need to be selected, where the net
is a full hierarchical name. Consider the “net2” net for investigation at the time
point 9n.

Action 4: Add debug_net and debug_time in the check statement.

hz1 dyn_highz node=[*] duration=2n time_window=[5n 10n]

debug_net=[net2] debug_time=[9n]

Action 5: Run the netlist with Spectre.

% spectre +aps debugging_utility.scs

A debug report is written into a file with the format

<netlistName>_<checkName>_<debug_time>.report.log. Notice in the
file name, <debug_time> will be the next step after the time specified in the
debug_time (=9n) parameter. Therefore, the file name may be different in
your run because the check does not force time points. However, a customer can
force the time point by using strobetimes, as follows:

tran tran … strobetimes=[9n]

Action 6: Open the result file, debugging_utility_hz1_9.100000e-

09.report.log.

Highz net: net2 0.110802V

MP2 ON (ids= -1.987623e-09 gds= 3.460855e-03 region= triode)

MP1 OFF (ids= -3.469976e-08 gds= 4.635513e-08 region= off) net1 HIGHZ

MN2 OFF (ids= 2.061835e-09 gds= 1.560221e-09 region= off)

MN0 ON (ids= 5.002095e-09 gds= 3.431084e-03 region= triode) net3 HIGHZ

net3 0.110801V

MN1 OFF (ids= 1.568408e-11 gds= 6.254355e-11 region= off) 0 LOWZ

C1 OFF ()

The report shows the devices that are OFF, causing node net2 to highz. Using
the above report, draw a circle crossing the OFF devices.

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4. Dynamic DC Leakage Current Path Check: Transient Based

The dyn_dcpath has two flavors:

1. The first flavor is based on transient analysis that is enabled by the

time_window and duration parameters. Consider
time_window=[1.1e-07 1.5e-07] duration=1e-10. Here,
dyn_dcpath will check each time step between [1.1e-07 1.5e-07]. It
will be a violation if there is a path for a duration more than 1e-10 sec
between transient time points [1.1e-07 1.5e-07].

2. The second flavor is based on leakage analysis (DC) that is enabled by the
leaki_times parameter. This flavor should be used in standby or power-
down mode. Consider leaki_times=[1.1e-07]. Here, it will do a leakage
analysis at time point 1.1e-07, and the check will use the DC solution at
1.1e-07. It will be a violation if there is a path based on the DC solution.
Therefore, in this flavor, the time_window and duration parameters do not
apply. See the “Workshop Exercise for Dynamic Check Based on Leakage
Analysis” section.

You can run only one flavor with one check statement. You cannot run both flavors
with one check statement. #2 has more priority than #1. For example, if the
statement is “leaki_times=[1.1e-07] time_window=[1.1e-07 1.5e-07]”,
you will see the following message in the log:

Ignoring parameter `time_window' because both `leaki_times'

and `time_window' are specified, and `leaki_times' has more
priority over `time_windows'.

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Action 1: Open the dyn_dcpath.scs netlist, and review the circuit and the design
check statement.

dcpath1 dyn_dcpath ith=200u duration=1n net=[vdd 0]

time_window=[1n 20n]

The above statement checks for any DC paths between the voltage sources,
“vdd” and “0”, with a current larger than 200uA and for a duration longer than
1ns, within the time window from 1ns to 20ns. Note that the net=[] parameter
should contain at least two nets.

Figure 13

Action 2: Run the netlist with Spectre.

% spectre dyn_dcpath.scs

Action 3: Open the result file, dyn_dcpath.dynamic.xml, with a web browser.

This simple circuit uses the same sources as described in Figure 13. Find out
any DC path violation within the given time range. Verify your finding with the
check result.

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The result file reports a DC path through PMOS “MP1” and NMOS “MN1”. The
violation happens for the duration of 4.9ns, starting at 10ns.

This path report has the following three sections:

a. The first section shows a path that is found starting “From Net” vdd “To
Net” 0. Since this is a check based on transient analysis, the name of the
table is "Dynamic dcpath check based on transient analysis".

b. The second section shows the actual instances in the path. The first
column, “Instance”, contains instances in the path. The second column
contains the current through instances. The current is taken at the end of
violation, which is equal to 1.52e-8 second (start + duration = 1.03e-8 +
4.94e-9).

c. The third section shows the state of MOSFETs in the path. It does not
report anything other than MOSFET. The first column, “Instance Name”,
is the MOSFET name. The second column is the model name. The
following columns are the terminal names and voltages. The last two
columns are the drain and source terminal currents. Values are taken at
the end of violation.

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Similar to the xml report, the text report is shown below:

The current through MP1 and MN1 is shown in Figure 14 and Figure 15.

Figure 14: Current through MP1

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Figure 15: Current through MN1

Notice that the path reported by dyn_dcpath is correct.

Also, notice that you CANNOT change the whole time window to one single
point. In other words, this check works inside a time window, and NOT at a
certain transient time point. If you want to run this check on a certain time point,
you shrink the time window. Suppose you want to run this check at a single
transient point of 1.0e-7. To do so, use the following syntax:

time_window=[1.0e-07 1.2e-7] duration=1e-8

time_window=[1.000e-07 1.002e-7] duration=1e-10

The check will strobe the time points given in the time window.

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5. Dynamic DC Leakage Current Path Check: Common Mistake

Action 1: Open the dyn_dcpath_common_mistake.scs netlist, and review the
circuit. Notice that the designer’s ground is defined by a node called gnd,
whereas the simulator’s ground is defined by 0. There is a 0V DC vsource called
Vgnd between gnd and 0. Hence, the current will be flowing in a gnd->V0-
>vdd->MP1->out->MN1->gnd loop. There will be no current through Vgnd.

Figure 16

Next, review the design check statement.

dcpath1 dyn_dcpath ith=200u duration=1n net=[vdd 0]

time_window=[1n 20n]

The above statement checks for any DC paths between voltage sources, “vdd”
and “0”, with a current larger than 200uA and for a duration longer than 1ns,
within the time window from 1ns to 20ns. It will check the path, vdd->MP1-
>out->MN1->gnd->Vgnd->0, and will find no violation because the current
through Vgnd is below ith throughout the simulation.

Selecting [vdd 0] is a common mistake users make. Therefore, it is required to

select a proper ground; that is, [vdd gnd]. Note that the net=[] parameter
should contain at least two nets.

Sometimes, users use a very small resistor instead of 0V vsource between gnd
and 0. A similar mistake can be done with such resistors.

Action 2: Run the netlist with Spectre.

% spectre dyn_dcpath.scs

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Action 3: Open the result file, dyn_dcpath_common_mistake.dynamic.xml,

with a web browser.

It reports a path through PMOS “MP1” and NMOS “MN1” from net vdd to net gnd.

It reports NO path from net vdd to net 0 because the current through Vgnd (0A)
is less than 200uA.

Sometimes, users use a very small resistor instead of 0V vsource between gnd
and 0. A similar mistake can be done with such resistors.

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6. Dynamic Floating-Node-Induced DC Leakage Path Check:

Transient Based
The definition of Highz/floating node is given in Appendix: Floating Node Detection.

dyn_floatdcpath has two flavors:

1. The first flavor is based on transient analysis that is enabled by the

time_window and duration parameters. Consider
time_window=[1.1e-07 1.5e-07] duration=1e-10. Here,
dyn_floatdcpath will check each time step between [1.1e-07 1.5e-
07]. It will be a violation if there is a path and highz node for a duration
more than 1e-10 sec between transient time points [1.1e-07 1.5e-07].

2. The second flavor is based on leakage analysis (DC) that is enabled by the
leaki_times parameter. This flavor should be used in standby or power-
down mode. Consider leaki_times=[1.1e-07]. Here, it will do a leakage
analysis at time point 1.1e-07, and the check will use the DC solution at
1.1e-07. It will be a violation if there is a path and highz node based on the
DC solution. Therefore, in this flavor, the time_window and duration
parameters do not apply. See the “Workshop Exercise for Dynamic Check
Based on Leakage Analysis” section.

Ignoring parameter `time_window' because both `leaki_times'

and `time_window' are specified, and `leaki_times' has more
priority over `time_window'.

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Action 1: Open the dyn_floatdcpath_tran.scs netlist, and review the circuit

and the design check statement.

Figure 17: Circuit

dyn1 dyn_highz node=[*] duration=1n fanout=gate

time_window=[0n 20n]

The above statement checks for any high-impedance node in the design with a
duration larger than 2ns, within the time window from 0ns to 20ns.

dyn2 dyn_dcpath net=[vdd2 0] duration=1n ith=1u

time_window=[0n 20n]

The above statement checks for any DC paths between voltage sources, “vdd2”
and “0”, with current larger than 1uA and for duration longer than 1ns, within the
time window from 0ns to 20ns. Note that the net=[] parameter should contain
at least two nets.

dyn3 dyn_floatdcpath net=[vdd2 0] duration=1n ith=1u

time_window=[0n 20n]

The above statement checks for any Float DC paths between the voltage
sources, “vdd2” and “0”, with the current larger than 1uA and for a duration
longer than 1ns, within the time window from 0ns to 20ns. Note that the net=[]
parameter should contain at least two nets.

Action 2: Run the netlist with Spectre.

% spectre dyn_floatdcpath_tran.scs

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Action 3: Open the result file, dyn_floatdcpath_tran.dynamic.xml, with a

web browser.

Figure 18: Two PWL sources

Check the connectivity of devices in the dyn_floatdcpath_tran.scs netlist.

This simple circuit uses two PWL sources as described in Figure 17. Find out
which node will have high impedance and at what time range. Verify your finding
with the check result.

The result file reports that the out1 node is a high-impedance node. There are
two violations as shown below:

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The result file reports two dyn_dcpath violations as shown below:

The node out is highz in the following violation windows:

Start 5.296171E-09 1.530560E-08

Duration 4.811802E-09 4.694399E-09
Stop 1.010797E-08 2.000000E-08

dyn_dcpath reports the following violation windows:

Start 1.322106E-09 1.050328E-08

Duration 8.982214E-09 9.496717E-09
Stop 1.030432E-08 2.000000E-08

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Therefore, dyn_floatdcpath should be the union of the above two tables.

Start 5.296171E-09 1.530560E-08

Duration 4.811802E-09 4.694399E-09
Stop 1.010797E-08 2.000000E-08

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7. Dynamic MOSFET Voltage Check

Action 1: Open the dyn_mosv.sp netlist, and review the circuit and the design
check statement.

mos1 dyn_mosv model=[nmos] cond="v(g,s)>1.9" duration=2n

The above statement checks for any MOSFET with model nmos that satisfies the
condition v(g,s)>1.9V for a duration longer than 2ns.

mos2 dyn_mosv model=[nmos] cond="v(g,s)>1.9" duration=2n

inst=[x2]

The above statement is similar to the mos1 check, but it will only check the
instance in x2.

Action 2: Run Spectre on the netlist.

% spectre +spice dyn_mosv.sp

Action 3: Open the result file, dyn_mosv.dynamic.xml, with a web browser.

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In this example, the first check, mos1, reports two violations by x1.mn2 and
x2.mn2. The violations can be seen on the following graph. The green plot
corresponds to v(g,s) of NMOS x1.mn2. The red plot corresponds to v(g,s)
of NMOS x2.mn2.

The circuit is shown below:

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The last three columns are as follows:

The “Dissatisfied” column shows the expression that is true at the “Check
Time”. In other words, “Dissatisfied” shows the region where the design intent is
dissatisfied. The “Violating Value” is the voltage value at the “Check Time”. The
“Check Time” is equal to the start for violation.

The second check, mos2, reports one violation by x2.mn2, which is the
MOSFET inside x2.

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8. Dynamic MOSFET Voltage Check: extreme

The “extreme” feature is supported only in Spectre® and Spectre® APS.

Action 1: Open the dyn_mosv_extreme.scs netlist and review the circuit.

Since the source is grounded, the Vgs of MOSFET is the same as netG. Vgs is
shown below:

Since the source is grounded, the Vds of MOSFET is the same as netD. Vds is
shown below:

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Action 2: Review the design check statement.

mosDio7e dyn_mosv model=[] inst=[] cond="v(g,s)<-0.4 ||

v(g,s)>0.4" duration=1n sample=extreme

The above statement reports any MOSFET if V(g,s) is going outside the range
of -0.4V and 0.4V, for a duration longer than 1ns. With sample=extreme, it
will report the maximum overshoot/undershoot value.

mosDio0e dyn_mosv model=[] inst=[] cond="l>40n && w>1u &&

v(g,s)>0.4 && v(d,s)>0.4" duration=1n sample=extreme

The above statement reports any MOSFET with Vgs and Vds greater than 0.4V
for a duration larger than 1n. With sample=extreme and the > symbol, it will
report the maximum overshoot value.

Action 3: Run Spectre on the netlist.

% spectre dyn_mosv_extreme.scs

Action 4: Open the result file, dyn_mosv_extreme.dynamic.xml, with a web

browser.

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The first check statement reports two violations. The first violation is between
1.6n and 4.4n, with an overshoot of 0.89V at 3n. The second violation is
between 5.6n and 8.4n, with an undershoot of -0.89V at 7n.

The second check statement reports one violation between 2.6n and 4.4n. The
maximum overshoot of Vgs is 0.89V at 3n. Similarly, the maximum overshoot of
Vds is 0.89 at 4n.

Action 5: Open the dyn_mosv_extreme.dynamic.rpt result file.

The text equivalent of the second check statement is as follows:

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9. Dynamic Resistor/Capacitor Voltage Check

Action 1: Open the dyn_resv_capv.sp netlist, and review the circuit and the
design check statements.

resv1 dyn_resv cond="v(1,2)>0.2" duration=0.5n

The above statement checks for any resistor that has a voltage greater than
0.2V across its terminals, for a duration longer than 0.5ns.

capv1 dyn_capv cond="v(1,2)>0.2" duration=0.5n

Similarly, the above statement checks for any capacitor that has a voltage
greater than 0.2V across its terminals, for a duration longer than 0.5ns. Notice
that “1” stands for the positive terminal, and “2” stands for the negative terminal
of a device.

Action 2: Run XPS on the netlist.

% spectre +spice +xps +cktpreset=sram dyn_resv_capv.sp

Action 3: Open the result file, dyn_resv_capv.dynamic.xml, with a web

browser.

The result file reports that resistor r1 has a voltage greater than 0.2V for a
duration longer than 0.5ns. The voltage across the terminals of resistor r1 is
given in the following graph. Notice that the violation starts at 1.011ns and stays
for a duration of 0.685ns, which is longer than the duration given in the
statement.

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Similarly, the result file reports that capacitor c1 has a voltage greater than 0.2V
for a duration longer than 0.5ns.

This check is supported only by XPS FASTSPICE. For Spectre and Spectre
APS, use the assert statement.

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10. Dynamic Diode Voltage Check

Action 1: Open the dyn_diodev.sp netlist, and review the circuit and the design
check statements.

dv1 dyn_diodev model=diode1 cond="v(a,c)>0.5" duration=25E-

The above statement will check for any diode with model name diode1 that has
a voltage more than 0.5V across its terminals, for a duration longer than 25ns.

Action 2: Run the netlist with XPS.

% spectre +spice +xps +cktpreset=sram dyn_diodev.sp

Action 3: Open the result file, dyn_diodev.dynamic.xml, with a web browser.

The result file reports two diodes, “d1” and “d2”, which have a violation. The “d1”
diode has a violation starting at 51.7ns for a duration of 52.8ns. The “d2” diode
has a violation starting at 4ns for a duration of 46.4ns.

Analyze the netlist to identify this violation. This check is supported only by XPS
FASTSPICE. For Spectre and Spectre APS, use the assert statement.

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11. Dynamic Excessive Element Current Check

Action 1: Open the dyn_exi.scs netlist, and review the circuit and the design
check statement.

exi1 dyn_exi dev=[*] ith=900u duration=2n time_window=[1n

20n]

The above statement checks for any device that carries a current greater than
900uA for a duration longer than 2ns, in the time window 1ns to 20ns.

Action 2: Run the netlist with Spectre.

% spectre dyn_exi.scs

Action 3: Open the result file, dyn_exi.dynamic.xml, with a web browser.

In this example, the first check, exi1, reports two violations by MN1 and MP1.
The violation starts at 10ns and remains for a duration of 4.8ns. The maximum
current during this violation is also given in the report.

The current through MP1 and MN1 is shown in Figure 14 and Figure 15.

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12. Dynamic Excessive Rise and Fall Time Check

The WL decoder circuit has 8 address inputs (AD<7:0>) and 256 outputs
(WL<255:0>). Depending on the input address, only one of 256 WLs will be “fired”.
In the stimulus setup, AD<7:0> is cycled between 00/h and FF/h. Thus, WL<0> and
WL<255> are fired alternatively. At 20n, AD<7:0> is 00/h and WL<0> is high,
whereas at 50n, AD<7:0> is FF/h and WL<255> is high.

Action 1: Open the dyn_exrf.sp netlist, and review the circuit and the design
check statement.

exrf1 dyn_exrf node=[*] subckt=[decdec3_4] rise=1p

fall=1p utime=30n vlth=0.36 vhth=1.44 time_window=[0 50n]

The above statement checks for all nodes in the decdec3_4 subckt, which have
either a rise/fall time longer than 1ps or an undefined state longer than 30ns, in
the time window of 0ns to 50ns. The rise time is defined as the time taken by a
waveform from vlth to vhth. Similarly, fall time is defined as the time taken by
a waveform from vhth to vlth. Undefined state is defined as the time when the
waveform is between vlth and vhth.

Action 2: Run the netlist with Spectre.

% spectre +spice dyn_exrf.sp

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Action 3: Open the result file, dyn_exrf.dynamic.xml, with a web browser.

Click on the Duration column header to sort this column in descending order.

Figure 19

The result table reports that the XTOP.XPRE2.XI1.XI32.net15 node is in an

undefined state for a duration of 35.47ns, starting at 0ns. The undefined time is
shown in the plot below. Notice that the undefined time is longer than 30ns,
which violates the condition given in the design statement within the time window
of 0ns to 50ns.

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The XTOP.XPRE2.XI1.XI32.net15 node is shown in Figure 19 in red. Notice

that it is not driven to either vdd (1.8V) or gnd because signals
XTOP.XPRE2.WRB<1> and XTOP.XPRE2.WR<0> are switched.

Figure 20

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The fall time of XTOP.XPRE2.WRB<1> is 5.29352n – 5.18688n = 0.10664n.

The rise time of XTOP.XPRE2.WRB<1> is 35.5749n– 35.4742n = 0.1007n. Notice

that ViVA shows interpolated values.

In many scenarios, only nodes connected to gates are desired. You can filter the
report to do this by adding fanout=gate in the check statement.

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Action 4: Open the dyn_exrf.sp netlist, and add fanout=gate in the check
statement.

exrf1 dyn_exrf node=[*] subckt=[decdec3_4] rise=1p

fall=1p utime=30n vlth=0.36 vhth=1.44 time_window=[0 50n]
fanout=gate

Notice that the fall and rise times of XTOP.XPRE2.WRB<1> shown in Figure 19
are 107ps and 98ps, respectively. Notice that XTOP.XPRE2.WRB<1> is driven
by NMOS/PMOS (pink) shown in Figure 20.

Now, decrease the width of NMOS/PMOS to increase the fall/rise time and to see
if the check can catch it.

Action 5: Open the decoder.net netlist, and change the width of NMOS to 0.015
and PMOS to 0.036.

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Action 6: Run the netlist with Spectre.

Action 7: Open the result file, dyn_exrf.dynamic.xml, with a web browser.

The above result table reports that the XTOP.XPRE2.WRB<1> node has a fall
time of 7.3ns, starting at 6.3ns.

The fall time is shown in the following plot. Notice that the fall time is longer than
1ps; therefore, it violates the condition given in the design statement.

Similarly, the result table reports that the XTOP.XPRE2.WRB<1> node has a rise
time of 7.0ns, starting at 36.9ns. The rise time is shown in the plot. Notice that
the rise time is longer than 1ps, which violates the condition given in the design
statement.

In the plot, the fall and rise times are 7.31417n (13.6154n - 6.30123n) and
7.0193n (43.8813n - 36.862n), respectively, which are the same as reported by
the check.

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Action 8: Open the result file, dyn_exrf.static.xml, with a web browser.

Notice that the static check can also catch it. To know more about the
static_rcdelay check, see the static checks chapter above.

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13. Dynamic Glitch Check

Action 1: Open the dyn_glitch.sp netlist, and review the circuit and the design
check statement.

dyn_glitch1 dyn_glitch node=[IN OUT] duration=1n low=0

high=1.2

The above statement checks the IN and OUT nodes for a glitch for a duration
shorter than 1ns. A glitch occurs when:

• A low signal goes above the mid-level, and crosses the mid-level again in
a time less than the user-defined duration.

• A high signal goes below the mid-level, and crosses the mid-level again in
a time less than the user-defined duration.

The mid-level is equal to 0.5*(low+high). In this statement, the values for low
and high are 0V and 1.2V, respectively. Therefore, the mid-level is equal to
0.6V.

Action 2: Run the netlist with Spectre.

% spectre +spice dyn_glitch.sp

Action 3: Open the dyn_glitch.dynamic.xml result file with a web browser.

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In this example, the check reports two nodes with violations. For the IN node, the
crest is greater than “low (static) voltage (0V) + 0.6V”, around
2.09ns for a duration of 0.25ns. Also, for the IN node, it reports the trough that
is less than “high (static) voltage (1.2V) - 0.6V”, around 12ns for
the duration 0.16ns. Notice that the duration for both crest and trough of the IN
node is shorter than the duration given in the check statement.

See the following plot for more details:

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14. Dynamic Setup and Hold Check

The purpose of this section is to get familiar with the check mechanism and the
output report. For this purpose, a trivial example is used.

Action 1: Open the dyn_setuphold.sp netlist, and review the circuit and the
design check statement.

This check reports any setup-time and hold-time violations. This check will report
any timing violation if the signal net transition happens within the setup-time
violation window, which is set by setup_time, and/or hold-time violation
window, which is set by hold_time.

my_dyn_sh1 dyn_setuphold node=[in] edge=rise ref_node=out

ref_edge=rise setup_time=3n vhth=2.5 ref_vhth=2.5

This statement checks if the difference between the rising edges of the signal
node, node=[in], and the reference node, ref_node=out, is within the setup-
time window. The rising edge of the reference node is defined as the time point
when its voltage crosses ref_vhth=2.5V. Similarly, the rising edge of a signal
node is defined as the time point when its voltage crosses vhth=2.5V.

my_dyn_sh2 dyn_setuphold node=[in] edge=fall ref_node=out

ref_edge=fall setup_time=3n vlth=0.5 ref_vlth=0.5

This statement checks if the difference between the falling edges of the signal
node, node=[in], and the reference node, ref_node=out, is within the setup-
time window. The falling edge of a reference node is defined as the time point
when its voltage crosses ref_vlth=0.5V. Similarly, the falling edge of a signal
node is defined as the time point when its voltage crosses vlth=0.5V.

my_dyn_sh3 dyn_setuphold node=[out] edge=rise ref_node=in

ref_edge=rise hold_time=3n vhth=2.5 ref_vhth=2.5

This statement checks if the difference between the rising edges of the signal
node, node=[out], and the reference node, ref_node=in, is within the hold-
time window.

my_dyn_sh4 dyn_setuphold node=[out] edge=fall ref_node=in

ref_edge=fall hold_time=3n vlth=0.5 ref_vlth=0.5

This statement checks if the difference between the falling edges of the signal
node, node=[out], and the reference node, ref_node=in, is within the hold-
time window.

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Action 2: Run the netlist with Spectre.

% spectre +spice dyn_setuphold.sp

Action 3: Open the result file, dyn_setuphold.dynamic.xml, with a web

browser.

The first check reports the following setup-time violations. Notice the type of
check is “setup”.

In this plot, the green-colored line is the reference net out and the orange-
colored line is the signal net in. Marker A is for the reference net, and marker B
is for the signal net.
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© 2023 Cadence Design Systems, Inc. DO NOT DISTRIBUTE. Page 90
Static and Dynamic Checks: RAK

Notice that the difference between the rising edges of the signal net and the
reference net is 130ps, which is less than the setup-time window of 3ns. In this
check, the violation window starts from “Reference Time” minus setup_time,
where “Reference Time” is 6.96ns and setup_time is 3ns. Therefore, the
violation window starts from 3.96ns, as shown in the above plot. Moreover, the
violation window ends at “Reference Time”.

In this plot, the green-colored line is the reference net out and the orange-
colored line is the signal net in. Marker A is for the reference net, and marker B
is for the signal net.

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Notice that the difference between the falling edges of the signal net and the
reference net is 140ps, which is less than the setup-time window of 3ns. In this
check, the violation window starts from “Reference Time” minus setup_time,
where “Reference Time” is 8.97ns and setup_time is 3ns. Therefore, the
violation window starts from 5.97ns, as shown in the above plot. Moreover, the
violation window ends at “Reference Time”.

The third check reports the following hold-time violations. Notice the type of
check is “hold”.

In this plot, the orange-colored line is the reference net in and the green-colored
line is the signal net out. Marker A is for the reference net, and marker B is for
the signal net

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Notice that the difference between the rising edges of the reference net and the
signal net is 130ps, which is less than the hold-time window of 3ns. In this
check, the violation window starts from “Reference Time”, where “Reference
Time” is 6.83ns. The violation window ends at “Reference Time” plus
hold_time (3ns). Therefore, the violation window ends at 9.83ns, as shown in
the above plot.

In this plot, the orange-colored line is the reference net in and the green-colored
line is the signal net out. Marker A is for the reference net, and marker B is for
the signal net.

Notice that the difference between the falling edges of the signal net and the
reference net is 138ps, which is less than the hold-time window of 3ns. In this
check, the violation window starts from “Reference Time”, where “Reference
Time” is 8.83ns. The violation window ends at “Reference Time” plus
hold_time (3ns). Therefore, the violation window ends at 11.83ns, as shown
in the above plot.

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15. Dynamic Setup and Hold Check: Scoping

The purpose of this section is to get familiar with the global and local scope
mechanisms. For this purpose, an SRAM example is used.

Action 1: Open the sram16k.sp netlist, and review the circuit and the design check
statement.

AD_SETUP_TIME dyn_setuphold node=[A\<*\>] edge=both

ref_node=PRE ref_edge=fall setup_time=5n vlth=0.2 vhth=0.8
ref_vlth=0.2

This statement checks if the difference between both edges of the signal node,
node=[A\<*\>], and the reference node, ref_node=PRE, is within the setup-
time window. The falling edge of the reference node is defined as the time point
when its voltage crosses ref_vhth=0.2V. Similarly, the rising edge of a signal
node is defined as the time point when its voltage crosses vhth=0.8V. The
falling edge of a signal node is defined as the time point when its voltage crosses
vlth=0.2V. The signal node from A<0> to A<9> will be checked. It is required
to use backslash in front of < and >.

If the subckt parameter is not specified, node and ref_node are considered
global nodes with hierarchical names starting from the top level. If the subckt
parameter is specified, node and ref_node are considered local nodes to that
subckt. In other words, node and ref_node will belong to the instances of the
specified subckt. Only one subckt value must be specified per check, with no
wildcard.

LOCAL_SETUP_TIME dyn_setuphold node=[net130] edge=rise

ref_node=PRE_ ref_edge=rise setup_time=5n
subckt=decoder4_16 vhth=0.8 ref_vhth=0.8

This statement checks if the difference between the rising edges of the signal
node, node=[net130], and the reference node, ref_node=PRE_, is within the
setup-time window. The rising edge of a reference node is defined as the time
point when its voltage crosses ref_vhth=0.8V. Similarly, the rising edge of a
signal node is defined as the time point when its voltage crosses vhth=0.8V.
Note that since the subckt=decoder4_16 parameter is specified, the signal
node and reference node must be a part of the decoder4_16 subckt. PRE_ and
net130 are the port and internal node of decoder4_16, respectively.

Action 2: Run the netlist with Spectre.

% spectre +spice sram16k.sp

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Action 3: Open the result file, sram16k.dynamic.xml, with a web browser.

The first check reports the following setup-time violations. Notice that the check
statement does not have a backslash. Further, notice that the “Ref Node Name”
and “Signal Node Name” are hierarchical names starting from the top level.

The second check reports the following setup-time violations. Notice that all
instances of the decoder4_16 subckt are checked. Further, notice that the “Ref
Node Name” and “Signal Node Name” are hierarchical names starting from the
top level. Since edge=both, both edges will be checked.

The PRE_ reference port of the X1.XIdecod1.XI45 instance is compared with

the X1.XIdecod1.XI45.net130 signal. Similarly, the PRE_ reference port of
the X1.XIdecod1.XI46 instance is compared with the
X1.XIdecod1.XI46.net130 signal. Since the PRE_ reference ports of the
X1.XIdecod1.XI45 and X1.XIdecod1.XI46 instances are connected to
X1.PRE_, only X1.PRE_ will be shown. Further, notice that
X1.XIdecod1.XI45 and X1.XIdecod1.XI46 are instances of the
decoder4_16 subckt.

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16. Dynamic Noisy Node Check

Action 1: Open the dyn_noisynode.sp netlist, and review the circuit and the
design check statement.

u1 dyn_noisynode node=[*] duration=10n e1=5e4 e2=2e16

skip=150e-12

The above statement reports any node that has a waveform with the first
derivative dv/dt greater than e1 and the second derivative d2v/dt2 greater than
e2, for the duration longer than 10ns. Any stable phase less than 150ps, during
the unstable duration of 10ns, will be ignored.

Action 2: Run the netlist with Spectre.

% spectre +spice dyn_noisynode.sp

Action 3: Open the result file, dyn_noisynode.dynamic.xml, with a web

browser.

In this example, the check reports two nodes with violations. Nodes 2 and 3 are
noisy nodes from approximately 0s to 20ns.

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17. Dynamic Node Capacitance Check

Action 1: Open the dyn_nodecap.sp netlist, and review the circuit and the design
check statement.

n1 dyn_nodecap node=[*] time=[0 5n]

The above statement reports the total capacitance on each node at a time equal
to 0 and 5ns. Device capacitances, voltage-dependent capacitances, and
grounded and coupling caps are combined into one value.

Action 2: Run the netlist with Spectre.

% spectre +spice dyn_nodecap.sp

Action 3: Open the dyn_nodecap.dynamic.xml result file with a web browser.

In this example, this check reports two nodes with their capacitances at each
time point given in the “time” parameter.

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18. Dynamic Subckt Port Power Check

This check is useful for power budgeting.

Action 1: Open the dyn_subcktpwr.sp netlist, and review the circuit and the
design check statements.

dyn1 dyn_subcktpwr inst=[] port=[] depth=1 time_window=[0

10n] power=on

The above statement reports port currents and port powers through all ports of all
subcircuit instances. The global ports are not included. It also reports subckt
powers consumed by all subcircuit instances.

Action 2: Run the netlist with Spectre.

% spectre +spice dyn_subcktpwr.sp

Action 3: Open the result file, dyn_subcktpwr.dynamic.xml, with a web

browser.

The port current is positive when the current is going into a subcircuit. This check
will report the average, RMS, maximum, and minimum values of the current
entering all ports, as shown below.

x2.out will not be printed because its current is 0A.

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Power analysis can be done by using the 'power' parameter. With power=on,
two additional sections are generated. The first section reports the average,
RMS, maximum, and minimum power entering at all ports. The first section is
given below.

x2.out will not be printed because its current is 0A.

The second section reports the average, RMS, maximum, and minimum sum of
port powers by the instance given in the first section. For example, the sum of x1
port (3.585049e-05-1.913725e-05+2.852404e-04+0) is 3.019537e-04 W. If all
ports are accounted, it provides the power consumed by each instance of a
subcircuit, which is given in the 'inst' parameter. The second section is given
below.

Notice that the wildcard * in port=[*] will only read the port of the subcircuit
given in subckt. If there are global nodes, they will not be read by port=[*].
Therefore, for global nodes, you need to manually specify the port.

Notice that the time window should not be overlapped. For example, for a
different time window, use time_window=[0n 5n 5.1n 10n]. A time window
such as [0n 5n 5n 10n] is considered as a bad practice.

The filter parameter can be used to filter out ports that are connected only to
the gate of MOSFETs.

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19. Dynamic Subckt Port Power Check: Tree Based

This check is useful to trace the current through ports. In this tree-based approach, a
root of the tree is selected by the "net” parameter. From this root, the current is
traced down the hierarchy until the depth or device is reached.

Action 1: Open the dyn_subcktpwr_tree.sp netlist, and review the circuit and
the design check statements.

inst_based dyn_subcktpwr inst=[] port=[] depth=5

time_window=[0 10n]

The above statement reports port currents through all ports of all the subcircuit
instances.

tree_based_AVDD dyn_subcktpwr net=AVDD depth=5

time_window=[0 10n]

The above statement reports port currents through all the ports that are
connected to net AVDD. Ports connected to net AVDD are shown below.

tree_based_DVDD dyn_subcktpwr net=DVDD depth=5

time_window=[0 10n]

The above statement reports port currents through all ports that are connected to
net DVDD.

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Ports connected to net DVDD are shown below:

Action 2: Run the netlist with Spectre.

% spectre +spice dyn_subcktpwr_tree.sp

Action 3: Open the dyn_subcktpwr_tree.dynamic.xml result file with a web

browser.

The port current is positive when it is going into a subcircuit. This check will
report the average, RMS, maximum and minimum values of the current entering
all ports, as shown below.

20. Dynamic Pulse Width Check

Action 1: Open the dyn_pulsewidth.sp netlist, and review the circuit and the
design check statements.

chk1 dyn_pulsewidth node=[out1] pwmin_low=25n pwmax_low=30n

pwmin_high=25n pwmax_high=30n vlth=0.2 vhth=1.0

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The above command will check the node out1 and report if either of the
following conditions satisfies:

o The pulse width in logic-low state is outside the range of the pwmin_low
(25n) and pwmax_low (30n) parameters.

o The pulse width in logic-high state is outside the range of the pwmin_high
(25n) and pwmax_high (30n) parameters.

Action 2: Run the netlist with Spectre.

% spectre +spice dyn_pulsewidth.sp

Action 3: Open the dyn_pulsewidth.dynamic.xml result file with a web

browser.

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The result file reports that the pulse width in high state has two violations. The
source of the two violations is shown in the following figure.

49.95n 9.95n 29.95n

Similarly, the result file reports that the pulse width in low state has two
violations. The source of the two violations is shown in the following figure.

9.8n 29.8n 49.84n

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21. Dynamic Power Density Check

Action 1: Open the dyn_powerdensity.scs netlist, and review the circuit and the
design check statement.

Figure 21: Circuit

Figure 22: Two PWL sources

Check the connectivity of the devices in the dyn_powerdensity.scs netlist.

This simple circuit uses two PWL sources, as described in Figure 7. When inp is
low, MP1 is ON. When inn is high, MN1 is ON. When both MP1 and MN1 are ON,
there is a large current flow between vdd and gnd. Moreover, the power
dissipation is high. MN1 or MP1 are in ON state within “10ns to 15ns”, “30ns to
35ns”, and “50ns to 55ns” time windows.

As shown in Figure 7, vdd is boosted up to make MN1 dissipate more power

within a “30ns to 35ns” time window.

chk1 dyn_powerdensity shift=2n window=6n

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The above statement reports the average window with the highest power
consumption for each MOSFET. The power consumption will be checked in 6n
sec average windows, shifted by 2n sec.

Action 2: Run the netlist with Spectre.

% spectre dyn_powerdensity.scs

Action 3: Open the result file, dyn_powerdensity.dynamic.xml, with a web

browser.

The width reported is the instance width of MOSFET. The instance width of MN1
is 2u m.

MN1 has the maximum average power of 1.999364m W, within the [30n 36n]
average window. This is the same value as calculated by the ViVA calculator, as
shown below.

The report is sorted with “Max Avg Power”.

22. Dynamic Active Node Check

Action 1: Open the dyn_actnode.sp netlist, and review the circuit and the design
check statements.

chk2 dyn_actnode node=[*] dv=3.2 type=act time_window=[0

300n]

The above command will check all nodes and will report only the active nodes
between the time window of 0ns and 300ns. A node is considered active if its
peak-to-peak voltage between a given time window is larger than 3.2V.

Action 2: Run the netlist with Spectre.

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% spectre +spice +aps dyn_actnode.sp

Action 3: Open the result file, dyn_actnode.dynamic.xml, with a web browser.

Click the “Vpp(V)” header to sort by this column.

There are two tables.

The first table shows the percentage of active nodes in each time window. This
table is shown regardless of the value set in the “type” parameter.

The second table shows a list of active nodes. There are 20 active nodes. The
most active node, X5.NE, has a peak-to-peak voltage of 7.3V.

The other active node, X5.N2N1485, has a peak-to-peak voltage of 3.74V.The

plot of this active node is shown below. Notice that the peak-to-peak voltage is
3.74V between 0ns and 300ns.

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The maximum and minimum voltage during this time_window is 5.15V and 1.41V,
respectively.

Notice that the time window should not be overlapped. For example, for a
different time window, use time_window=[0n 5n 5.1n 10n]. A time window
such as [0n 5n 5n 10n] is considered as a bad practice.

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23. Dynamic Subckt Instance Activity Check

Action 1: Open the dyn_activity.sp netlist, and review the circuit and the
design check statement.

chk1 dyn_activity inst=[x1 x2] time_window=[0n 20n]

min_activity=0

The above command will check the activity percentage of instances X1 and X2.
The activity percentage is a ratio of the number of events happening in an
instance to the number of events happening in the whole circuit. Events start
recording between the specified time window of 0ns and 20ns.

Action 2: Run the netlist with Spectre.

% spectre +spice +xps +cktpreset=sram dyn_activity.sp

Action 3: Open the result file, dyn_activity.dynamic.xml, with a web browser.

The result file reports that there are 10 instances with an activity above 0%. The
most active instance, X2, has an activity percentage of 88.6%. Notice that since
there are only two instances in a circuit, the sum of X1 and X2 is 100%.

Notice that the time window should not be overlapped. For example, for a
different time window, use time_window=[0n 5n 5.1n 10n]. A time window
such as [0n 5n 5n 10n] is considered as a bad practice.

This check is only supported in XPS FASTSPICE.

24. Dynamic Subckt Port Voltage/Current Check

This reports the instances of the user-specified 'subckt', fulfilling the conditional
expression on port voltages and port currents for a time longer than the user-
specified 'duration'. Only one subckt is allowed per statement.

Voltages and currents of a port can be referenced by the subckt's port name. For
example, consider a subckt definition, ".subckt NOT port_A port_B". Here,
the supported subckt port names are v(port_A), v(port_B),
v(port_A,port_B), i(port_A), and i(port_B). The port current is positive
when the current is going into a subckt.

Supported operators are +, -, *, /, ==, !=, <, <=, >, >=, ||, &&, and !.

All design instances of the subcircuit specified in ‘subckt’ will be checked.

Action 1: Open the dyn_subcktport.sp netlist, and review the circuit and the
design check statements.

cur3 dyn_subcktport subckt=decwl64b cond="i(inh_VDD)>100u"

duration=0.1n

vol0 dyn_subcktport subckt=decand3_pre

cond="v(inh_VDD)>1.7" duration=10n

Action 2: Run the netlist with Spectre.

% spectre +spice +aps dyn_subcktport.sp

Action 3: Open the result file, dyn_subcktport.dynamic.xml, with a web

browser.

25. Dynamic Delay Check

The purpose of this section is to get familiar with the global and local scope
mechanisms. For this purpose, an SRAM example is used.

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Action 1: Open the sram16k.sp netlist, and review the circuit and the design check
statement.

DELAY dyn_delay node=[A\<3\>] edge=rise ref_node=A\<2\>

ref_edge=rise min_time=1n max_time=100n vhth=4.5
ref_vhth=4.5

This statement checks if the delay between the rising edges of the reference
node, ref_node=A\<2\>, and the signal node, node=[A\<3\>], is outside the
range of min_time=1n and max_time=100n. The trigger is the reference
node. The rising edge of the reference node is defined as the time point when its
voltage crosses ref_vhth=4.5V. Similarly, the rising edge of a signal node is
defined as the time point when its voltage crosses vhth=4.5V. Since the check
is a Spectre syntax, it is required to use a backslash in front of < and >.

LOCAL_DELAY dyn_delay node=[net142] edge=fall

ref_node=net136 ref_edge=fall min_time=1n max_time=100n
vhth=0.5 ref_vhth=0.5 subckt=decoder4_16

This statement checks if the difference between the rising edges of the signal
node, node=[net142], and the reference node, ref_node=net136, is outside
the range of min_time=1n and max_time=100n. The trigger is the reference
node. The rising edge of a reference node is defined as the time point when its
voltage crosses ref_vhth=0.5V. Similarly, the rising edge of a signal node is
defined as the time point when its voltage crosses vhth=0.5V. Note that since
the subckt=decoder4_16 parameter is specified, the signal node and the
reference node need to be a part of the decoder4_16 subckt.

Action 2: Run the netlist with Spectre.

% spectre +spice sram16k.sp

Action 3: Open the result file, sram16k.dynamic.xml, with a web browser.

The first check reports the following violations. Notice that the check statement
does not have a backslash. Further, notice that the “Ref Node Name” and “Signal
Node Name” are hierarchical names starting from the top level.

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The second check reports the following violations. Notice that all instances of the
decoder4_16 subckt are checked.

The following waveform shows the delay between the

X1.XIdecod1.XI45.net136 and X1.XIdecod1.XI45.net142 signals.

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26. Stop Simulation with the First Violation

The purpose of this section is to get familiar with a way to stop simulation (error) with
the first violation found by a checker.

Action 1: Open the stop_sim_with_first_violation.scs netlist, and review

the circuit and the design check statement.

hz1 dyn_highz node=[*] duration=2n error_limit=1

The above statement checks for all nodes, and reports only one violation. Notice,
the default value of error_limit is 10000.

The circuit is shown in Figure 6.

Action 2: Run the netlist with Spectre.

% spectre stop_sim_with_first_violation.scs

Action 3: Open the stop_sim_with_first_violation.log simulation log.

When violation count reaches its error_limit, the following message in the
log is issued:

Warning from spectre at time = 10.1193 ns during transient

analysis 'tran'.

WARNING (SPECTRE-20015): Violations of instance 'hz1'

reaches its limit('1'), further violations will be
ignored.

Action 4: Enable the following line:

optStopSim options warning_id=[SPECTRE-20015]

warning_change_severity=error

The above statement will change the severity level of SPECTRE-20015 from
warning to error.

Error found by spectre at time = 10.1193 ns during

transient analysis 'tran'.

ERROR (SPECTRE-20015): Violations of instance 'hz1'

reaches its limit('1'), further violations will be
ignored.
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Static and Dynamic Checks: RAK

Workshop Exercise for Dynamic Check Based on

Leakage Analysis
This section introduces several dynamic checks that are based on leakage analysis.

As against transient-based dynamic checks, these leakage-based checks aim to identify

the leakage current or power problems in various standby or power-down modes.
Traditionally, leakage simulations require very long transient simulations to fully reach
the final state of the standby or power-down mode. In the final state, capacitors are fully
charged or discharged.

Spectre accelerates the leakage current and power simulation by deploying a new
methodology that requires you to only provide the time point (leaki_times) where all
input signals are at their steady state. Spectre will perform a DC analysis at the
specified time point by converting transient sources into the DC source using the value
from the leaki_times time point. The DC analysis will be equivalent to a very long
transient simulation but provides the benefit of taking much less time.

To enable the leakage current and power simulation in Spectre in multiple power
modes, use the following options:

Spectre format:

opt1 options leaki_times=[4u 10u] //(defines input-steady state

time points in multiple power mode)

save v1:p vdd:p //(current probes on power supplies)

Spice format:

.options leaki_times=[4u 10u] //(defines input-steady state time

points in multiple power mode)

.probe tran i(v1) i(vdd) //(current probes on power supplies)

Following is an example of the command-line option to run the leakage simulation using
APS:

% spectre -64 +aps input.scs...

Following is an example of the command-line option to run the leakage simulation using
XPS:

% spectre -64 +xps +cktpreset=sram_pwr input.scs...

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As a result of the above settings, Spectre APS/XPS performs a transient simulation until
4us. Then, it performs a leakage analysis with the circuit biased at the 4us condition to
calculate the leakage currents i(v1) and i(vdd). After finishing leakage analysis at
4u, Spectre APS/XPS continues the transient simulation until 10us and performs
another leakage analysis with the circuit biased at the 10us condition. The result of the
leakage current simulation is reported in a file with the <netlist>.<tran>.leaki
format, where <netlist> is the netlist name and <tran> is the transient analysis
name. This file will be located in the .raw directory. The content of this file is shown
below.

i(v1): t= 4.0000e-06 val= -2.1293e-10

i(vdd): t= 4.0000e-06 val= -3.1166e-09

i(v1): t= 1.0000e-05 val= -4.3421e-10

i(vdd): t= 1.0000e-05 val= -6.9654e-09

There are differences between APS and XPS. The differences are as follows:

In APS, a steady-state check will be performed before doing the leakage current
simulation. It helps in the sense that you do not need to probe all nodes to see if steady
state is achieved. APS will check all nodes and will report the top ten non-steady-state
nodes. If steady state is achieved, the convergence in the leakage analysis is
guaranteed. If steady state is not achieved, the leakage analysis may or may not
converge. The result of a steady-state check is reported in the log file, as shown below:

***** Checking steady state at time = 4 us

***** Steady state is not found at time = 4 us. Top 3 non-

steady nodes are following:

net1

net2

net3

***** Checking steady state at time = 10 us

***** Steady state is found at time = 10 us

Using Spectre XPS FASTSPICE gives the following message in the log when doing the
leakage current simulation:
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Static and Dynamic Checks: RAK

simulating leakage current at 7.5e-09s, pid=27003 ... done...

CPU time 0.00s, elapse time 0.01s, memory used = 22.46 MB

Using Spectre APS gives the following message in the log when doing the leakage
current simulation:

***** Perform leaki and checker analysis for tran simulation at

time = …

Leakage and checker analysis time: CPU = 108.823 s, elapsed =

36.2673 s.

More information about leakage analysis is available in the Spectre manual at

“Introducing the Virtuoso Spectre Circuit Simulator > Spectre eXtensive Partitioning
Simulator > XPS SRAM Leakage Current Simulation”.

There are a few checks that are based on leakage analysis. These checks are
performed after the leakage analysis (DC) is finished and use the leakage analysis (DC)
solution to perform the check. Refer to Table 1 to see which MMSIM mode supports the
leakage-analysis-based approach.

xml output in leakage analysis approach

With Spectre, APS, XPS-S, and XPS-FASTSPICE, the

dyn_dcpath/dyn_floatdcpath violations will go into the regular xml file, with format
<netlist>.dynamic.xml. However, with XPS-MS, the
dyn_dcpath/dyn_floatdcpath violations will go into a separate xml file, with format
<netlist>.dynamic.leaki_<time>.xml and the regular xml file will not contain
any of the leakage-based check results. Unfortunately,
dyn_dcpath/dyn_floatdcpath checks will appear in <netlist>.dynamic.xml
with zero violation count and all other checks will appear in
<netlist>.dynamic.leaki_<time>.xml with zero violation count. Having two xml
files can be confusing. Therefore, in future,
<netlist>.dynamic.leaki_<time>.xml will be merged into the parent
<netlist>.dynamic.xml.

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1. Dynamic DC Leakage Current Path Check: leaki Based

Action 1: Open the dyn_dcpath_leaki.scs netlist, and review the circuit and the
design check statement.

dcpath2 dyn_dcpath ith=200u net=[vdd 0] leaki_times=[12.5n]

The above statement checks for any DC paths between the “vdd” and “0”
voltage sources, with a current larger than 200uA at leaki_times 12.5n.

Figure 23

The check will do the following two steps:

First, this check will internally do the leakage analysis at time 12.5ns to
determine the floating nodes. More information about leakage analysis is
available in the Spectre manual.

Second, the path detection algorithm will use the DC solution to detect a path
between vdd and 0 with a current more that 200u A (ith).

Action 2: Run the netlist with Spectre.

% spectre dyn_dcpath_leaki.scs

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Action 3: Open the dyn_dcpath_leaki.dynamic.xml result file with a web

browser.

The result file reports two DC paths. The path Id 0 shows the path through
PMOS “MP2” and NMOS “MN2”. The path Id 1 shows the path through PMOS
“MP1” and NMOS “MN1”. The violation is based on the leakage analysis at 12.5n
sec.

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This path report has the following two sections:

a. The first section shows a path that is found starting “From Net” vdd “To
Net” 0. Since this is a check based on leakage analysis, the name of the
table is "Dynamic dcpath check based on leaki analysis". At a given
net, as per KCL, the current entering the net is equal to the current exiting
the net. The “Total Current” is the current entering the vdd net (“From
Net”). The “Total Current” 2.860e-03 is the sum of 9.555e-04 and
1.905e-03. The net vdd is connected to MP1, MP2, and V0, as shown in
Figure 23.

b. The second section shows the actual instances in the path. The first
column, “Instance”, contains the instances in the path. The second
column contains the current through instances. The current is taken from
the DC solution.

Similar to the xml report, the text report is shown below:

Notice that the presence of four rows does not mean that there are four
violations. There are only two violations. The first two rows belong to one
violation with Id equal to 0. In the first two rows, all columns from “Checker
Name” to “Total Current (A)” have the same values. Only columns “Instance”
and “Current’ are different, which belong to the second section in xml.

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2. Dynamic Floating-Gate-Induced Leakage Check: Possible-Case

Current
Action 1: Open the dyn_floatdcpath.scs netlist, and review the circuit and the
design check statements.

dyn1 dyn_floatdcpath leaki_times=[7.5n] net=[vdd1 vdd2 0]

sweep=no

The above statement will check for any leakage paths between the nets that are
induced by floating gates at leaki_times. The net parameter should contain at
least two nets.

The check will do the following three steps:

First, this check will internally do the leakage analysis at time 7.5ns, to
determine the floating nodes. More information about leakage analysis is
available in the Spectre manual.

Second, the floating-node-detection algorithm will use the DC solution to detect

floating nodes. All MOSFETs with floating gates can be reported using the
floatgate=yes parameter (default is no). For more details about the algorithm,
refer to Appendix: Floating Node Detection.

Third, this check will report any leakage path from power supplies (vdd1, vdd2)
to ground, induced by floating gates. When the sweep parameter is set to no, the
leakage-path detection is based on conducting rules, as shown in -h.

If you do not want to run the third step and are only interested in the floating
gates detected at the second step, use the following statement without the net
parameter.

dyn2 dyn_floatdcpath leaki_times=[7.5n] floatgate=yes

Action 2: Run the netlist with Spectre.

% spectre dyn_floatdcpath.scs –outdir spectre

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Action 3: Open the result file, dyn_floatdcpath.dynamic.xml, with a web

browser.

This simple circuit uses the same sources as described in Figure 7. Find out any
floating gate at 7.5ns and the leakage path induced by such a floating gate.
Verify your finding with the check result.

Notice that this table gives all MOSFETs with floating gates. Here, the out node
is floating and it is connected to the gate of MP2 and MN2. Since there are two
MOSFETs, the violation count is 2.

The result file reports a DC leakage path through the “MP2” and “MN2” path
elements, which is induced by the floating node out at time 7.5ns. The path
report is shown below. Since one path is reported, the violation count is 1.

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This path report has the following three sections:

a. The first section shows a path that is found starting “From Net” vdd “To
Net” 0.

b. The second section shows the actual instances in the path. The first
column, “Instance”, contains the instances in the path. The second
column contains the current through the instances. The third column
establishes the link between the floating node and the MOSFET. The third
column may contain either a node name or N/A. If it is a node name, it
means that the corresponding element is a MOSFET and its gate is
floating. The fourth column shows the voltage of the floating gate.

c. The third section shows the state of MOSFETs in the path. It does not
report anything other than MOSFET. The first column, “Device”, is the
MOSFET name. The second column is the model name. The following
columns are the terminal names and voltages.

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3. Dynamic Floating-Gate-Induced Leakage Check: Worst-Case

Current
The purpose of this section is to get familiar with the sweep feature in APS. Starting
15.1, sweep=all is default for APS and XPS-MS.

Not all floating nodes are problematic. They are problematic if they induce a huge
leakage current in the next stage. Some customers want to know the worst possible
leakage current induced by a floating node. This can be achieved by using the
sweep feature in APS and XPS-MS.

The check will do the following three steps:

First, this check will internally do the leakage analysis at time 7.5ns to determine
the floating nodes. More information about leakage analysis is available in the
Spectre manual.

Second, the floating-node-detection algorithm will use the DC solution to detect

floating nodes. All MOSFETs with floating gates can be reported using the
floatgate=yes parameter (default is no). For more details about the algorithm,
see Appendix: Floating Node Detection.

Third, this check will report any leakage path from power supplies (vdd1, vdd2) to
ground, induced by floating gates. When the sweep parameter is set to single or
all, the leakage-path detection is based on the current. In the current-based path-
detection method, the floating node voltage is swept and the current in the path is
measured. After the measurement, the current-based method reports the qualifying
paths carrying an absolute current higher than the ith parameter. Either all floating
nodes are swept at once (sweep=all), or each floating node is swept individually
(sweep=single). The following parameters are relevant to the current-based path-
detection method: vmin, vmax, points, rforce, and ith.

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Action 1: Open the dyn_floatdcpath_sweep_all.scs netlist, and review the

circuit and the design check statements.

dyn2 dyn_floatdcpath net=[vdd 0] leaki_times=[7.5n]

sweep=all ith=0.5m vmin=0 vmax=1.1 points=3 rforce=1

In the above circuit, the worst-case current through MP2>MN2>MN3 will happen
when the floating node, out1, becomes 1.1V.

Action 2: Run the netlist with Spectre.

% spectre dyn_floatdcpath_sweep_all.scs

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Action 3: Open the result file, dyn_floatdcpath_sweep_all.dynamic.xml,

with a web browser.

The second section indicates that the worst-possible current is 0.55mA, through
MP2>MN2>MN3, with floating node out1 at almost 1.1V. Notice that only the path
with a current more than ith will be reported.

When the sweep parameter is set to all, it will force the voltage on all floating
nodes together. When “vmin=0 vmax=1.1 points=3”, it will force three
voltage points between vmin and vmax.

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4. Dynamic Floating-Gate-Induced Leakage Check: Worst-Case

Current: sweep=single: distribute
The purpose of this section is to get familiar with the distributed feature in the
sweep=single flow.

Action 1: Open the dyn_floatdcpath_sweep_single_distribute.scs

netlist, and review the circuit and the design check statements.

dyn_single dyn_floatdcpath net=[vdd vss] leaki_times=[10n

100n] floatgate=yes points=9 sweep=single ith=0.5m
distribute=fork numprocesses=5

In the above circuit, the worst-case current through MP2>MN2>MN3 will happen
when the floating node, out1, becomes 1.1V.

Action 2: Remove “distribute=fork numprocesses=5”. Notice that the default

value of distribute is ‘no’.

Action 3: Run the netlist with Spectre.

% spectre dyn_floatdcpath_sweep_single.scs

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Action 4: Open the result file,

dyn_floatdcpath_sweep_single_distribute.dynamic.xml, with a web
browser. There will be 10 paths like the following.

The second section indicates that the worst-possible current is 0.50mA, through
X0.MP2> X0.MN2> X0.MN3, with floating node X0.out1 at 1.05V. Notice that
only the path with a current more than ith will be reported.

When the sweep parameter is set to single, it will force the voltage on each
floating node individually.

Action 5: Add “distribute=fork numprocesses=5”, which was removed

before.

Action 6: Run the netlist with Spectre.

% spectre dyn_floatdcpath_sweep_single.scs

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Action 7: Open the result file,

dyn_floatdcpath_sweep_single_distribute.dynamic.xml, with a web
browser. The report will be similar to distribute=no.

The user should select numprocesses carefully based on machine resources.

The best way to think is how many Spectre jobs can be run on this machine
simultaneously.

The elapsed time of dyn_floatdcpath in distributed mode should be less than

that in non-distributed mode (default). To compare the elapsed time related to
dyn_floatdcpath, see the following entry in the public log:

Total leakage current computation time: CPU = 152.975 ms,

elapsed = 16.4335 s.

A bigger case will show a better speed-up with the distribute flow. In smaller
cases, such as this, it will not show any speed-up. The purpose of this section is
to explain the use model only.

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5. Dynamic Floating-Gate-Induced Leakage Check: Filtering Path

Per Floating MOSFET
Action 1: Open the dyn_floatdcpath_path_per_fm.scs netlist, and review the
circuit and the design check statements.

dynA1 dyn_floatdcpath net=[vdd1 0] leaki_times=[7.5n]

detailed_path=yes sweep=no

The above statement will check for any leakage paths between the nets that are
induced by floating gates at leaki_times. The check will report all possible
paths because the value of detailed_path is set to yes.

Figure 24

Action 2: Run the netlist with Spectre.

% spectre dyn_floatdcpath_path_per_fm.scs –outdir spectre

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Action 3: Open the result file, dyn_floatdcpath_path_per_fm.dynamic.xml,

with a web browser.

Find out any floating gate at 7.5ns and the leakage path induced by such a
floating gate. Verify your finding with the check result.

The result file reports two DC leakage paths through a similar path element
“MNA1” that is induced by a floating node float at time 7.5ns.

To see one path per floating MOSFET (that is, MNA1), use the per_fm option for
the detailed_path parameter, as shown in the following statement:

dynA2 dyn_floatdcpath net=[vdd1 0] leaki_times=[7.5n]

detailed_path=per_fm sweep=no

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6. Dynamic Floating-Gate-Induced Leakage Check: Filtering Path

Per Floating Node
Action 1: Open the dyn_floatdcpath_path_per_fn.scs netlist, and review the
circuit and the design check statements.

dynB1 dyn_floatdcpath net=[vdd1 0] leaki_times=[7.5n]

floatgate=yes detailed_path=yes sweep=no

Figure 25

Action 2: Run the netlist with Spectre.

% spectre dyn_floatdcpath_path_per_fn.scs

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Action 3: Open the result file, dyn_floatdcpath_path_per_fn.dynamic.xml,

with a web browser.

Find out any floating gate at 7.5ns and the leakage path induced by such a
floating gate. Verify your finding with the check result.

The result file reports two DC leakage paths through a similar path element
“MNA1” that is induced by a floating node, float, at time 7.5ns.

To see one path per floating node (that is, float), use the per_fn option for the
detailed_path parameter, as shown in the following statement:

dynB2 dyn_floatdcpath net=[vdd1 0] leaki_times=[7.5n]

floatgate=yes detailed_path=per_fn sweep=no

Note that the per_fn option for detailed_path is only supported in APS and
Spectre, but not in XPS FASTSPICE.

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7. Dynamic Floating-Gate-Induced Leakage Check: Filtering Diode-

Connected Nodes
The purpose of this section is to get familiar with the new filter_dioConNodes
option in APS. This option is not available in XPS yet. Some customers expect a
node not to be floating if it is connected to VDD or Gnd through mosDiode.

Action 1: Add mosDiode by enabling the following statement in

dyn_floatdcpath_filter_diocon_nodes.scs:

//MN_dio (out out 0 0) nch w=2u l=45n

Figure 26

Action 2: Add the filter_dioCon_nodes=1 option in the check statements.

hz1 dyn_highz node=[*] duration=2n time_window=[0n 20n]

filter_dioCon_nodes=1

fdc dyn_floatdcpath net=[vdd 0] leaki_times=[7.5n]

filter_dioCon_nodes=1

Action 3: Run the netlist with Spectre.

% spectre dyn_floatdcpath_filter_diocon_nodes.scs

Action 4: Open the dyn_floatdcpath_filter_diocon_nodes.dynamic.xml

result file.

It will have zero violation.

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8. Dynamic Floating-Gate-Induced Leakage Check: Debugging

Utility
This leaki-based dyn_floatdcpath will perform the following three steps:

First, this check will internally do the leakage analysis at leaki_times to determine
the floating nodes.

Second, the floating-node-detection algorithm will use the DC solution to detect

floating nodes. All MOSFETs with floating gates can be reported using the
floatgate=yes (default is no) parameter. For more details about the algorithm,
see Appendix: Floating Node Detection.

Third, this check will report any leakage path from power supplies to ground,
induced by floating gates.

Action 1: Open the debugging_utility.scs netlist, and review the circuit and
the design check statement.

Figure 27: Highz debug circuit

If you do not want to run the third step and are only interested in the floating
gates detected at the second step, use the following statement without the net
parameter.

dyn2 dyn_floatdcpath leaki_times=[7.5n] floatgate=yes

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Check the connectivity of devices in the netlist. This simple circuit uses two PWL
sources as described in Figure 25. Find out which node will have high impedance
and at what time range. Verify your finding with the check result.

Figure 28: Two PWL sources

Action 2: Run the netlist with Spectre.

% spectre +aps debugging_utility.scs

Action 3: Open the result file, debugging_utility.dynamic.xml, with a web

browser.

Notice that this table gives all MOSFETs with floating gates. Here, the net2
node is floating and it is connected to the gate of MP2 and MN2. Since there are
two MOSFETs, the violation count is 2.

To use the debug utility, a net needs to be selected, where the net is a full
hierarchical name. Consider the “net2” net for investigation at the leaki_time
point 7.5n.
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© 2023 Cadence Design Systems, Inc. DO NOT DISTRIBUTE. Page 135
Static and Dynamic Checks: RAK

Action 4: Add debug_net in the check statement.

dyn2 dyn_floatdcpath leaki_times=[7.5n] floatgate=yes

debug_net=[net2]

Action 5: Run the netlist with Spectre.

% spectre +aps debugging_utility.scs

A debug report is written into a file with the following format:

<netlistName>_<checkName>_<debug_time>.report.log

Action 6: Open the debugging_utility_dyn2_7.500000e-09.report.log

result file.

Highz net: net2 0.513436V

MP2 ON (ids= -2.456944e-05 gds= 9.830336e-05 region= saturation)

MP1 OFF (ids= -1.672934e-11 gds= 3.070317e-05 region= subthreshold) net1 HIGHZ

MN2 OFF (ids= 2.456908e-05 gds= 1.620640e-05 region= subthreshold)

MN0 OFF (ids= 4.107096e-11 gds= 1.827120e-04 region= subthreshold) net3 HIGHZ

C1 OFF ()

The report shows the devices that are OFF, causing the net2 node to highz.
Using the above report, draw a circle crossing the OFF devices.

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Workshop Exercise for Dynamic Floating Node

Statistical Check
As against transient-based dynamic checks, this check forks another transient process
with certain nodes forced to certain voltages. Once the forked transient process is
finished, the parent transient process with continue.

This check reports leaky MOSFET/BJT caused by floating nodes. It can also detect
floating nodes caused by other floating nodes.

This check deploys a statistical method of forcing ('pinging') different voltages on the
gate of MOSFET and the base of BJT. Ping means randomly forcing a node either to 0
or VDD, or ramping from 0 to VDD. Only MOSFET gate or BJT base nodes are pinged.
Ping is realized by applying a voltage source, in series with a large resistor
(ping_resistor) on each node. Strength of a ping will be weaker (because of large
ping_resistor) than the other drivers on each node.

Algorithm is the following

• Run transient simulation till “ping_start”.

• Find the qualified nodes to exercise pings according to domains.
• For each qualified node, evaluate the domain_voltage.
• Create pings randomly by using seed. One-third of the qualified nodes will be
selected for HIGH. One-third of the qualified nodes will be selected for LOW. One-
third of the qualified nodes will be selected for RAMP.
• Evaluate ping_duration and ping_resistor.
• At “ping_start”, start applying pings sequentially.

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• For each ping:

• Right before applying the ping, store all MOSFET drain currents and BJT
collector currents as reference current (Iref).
• For the first half of “ping_duration”:
• Force the HIGH/LOW to each node through a resistor with value
“ping_resistor”.
• Check the device current (Iping) at 0.95 of “0.5*ping_duration”.
A fail is detected if:
• |Iref-Iping| > max(pingiabsthresh, pingirelthresh*min(|Iref|,|Iping|))
• For the second half of “ping_duration”:
• Force the RAMP to each node through a resistor with value
“ping_resistor”. Check the maximum (Iping,max) and minimum
(Iping,min) device current during the RAMP. A fail is detected if either:
• |Iref-Iping,max| > max(pingiabsthresh_ramp, pingirelthresh*min(|Iref|,|Iping,max|))
• |Iref-Iping,min| > max(pingiabsthresh_ramp, pingirelthresh*min(|Iref|,|Iping,min|))

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1. Dynamic Floating Node Statistical Check: Worst-Case Current

Action 1: Open the dyn_float_tran_stat.scs netlist, and review the circuit and
the design check statements.

dynSta1 dyn_float_tran_stat domains=[vdd vss]

ping_start=[20n] ping_count=30 ping_duration=10u
ping_iabsthresh=100e-9 ping_iabsthresh_ramp=100e-9
ping_irelthresh=1000 save=all

Action 2: Run the netlist with Spectre.

% spectre dyn_float_tran_stat.scs –outdir spectre

Action 3: Open the result file, dyn_float_tran_stat.dynamic.xml, with a web

browser.

With Ping Index 1, it shows two MOSFETS.

Action 4: Open the file, dyn_float_tran_stat_dynSta1_5.000000e-

09.ping.info, which is in the raw directory.

With Ping Index 1, the above section shows the random selection for each
qualified node. Notice that N1 is randomly selected for RAMP_UP.

Action 5: Open the file, dyn_float_tran_stat_dynSta1.domain.nodes,

which is in the raw directory.

The above image shows that for N1, HIGH is 1.1V, whereas LOW is 0V.

Action 6: Plot ping_index 1 in ViVA.

For ping_index 1, during RAMP_UP, N1 was ramped from 0V to 1.1V. As a

result, there is a high current in MP1 and MN1. This current is reported in reported
in above plot

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Action 7: Next, open the result file, dyn_float_tran_stat.dynamic.xml, with

a web browser.

With Ping Index 16, it shows two MOSFETs.

Action 8: Open the file, dyn_float_tran_stat_dynSta1_5.000000e-

09.ping.info.

With Ping index 16, above section shows the random selection for each
qualified node. Notice N1 and N3 are randomly selected as HIGH and RAMP_UP,
respectively.

Action 9: Open the file, dyn_float_tran_stat_dynSta1.domain.nodes.

Above shows that for N1 and N3, HIGH is 1.1V, whereas LOW is 0V.

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Action 10: Plot ping_index 16 in ViVA.

For ping_index 16, N1 is HIGH, making N3 floating. During RAMP_UP on N3, it

was ramped from 0V to 1.1V. As a result, there is a high current in MP3 and MN3.
This current is reported in above plot

Action 11: Open the result file, dyn_float_tran_stat.dynamic.xml, with a

web browser. Then, scroll down on the section showing “Floating Node
Violation”.

This tables shows which nodes are floating. The table is sorted by “Floating
Probability” in descending order. A node having 0% probability will not be printed.

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By looking at the schematic, N1 appears to be always floating. However, this

methodology works with voltages at the start and end of the first phase.
Therefore, the reference voltage is important in detecting the probability of a
floating node.

The reference voltage of N1 at 20n is 0.1, which is already low. When HIGH is
forced, the difference can be noticed. When LOW is forced, the difference cannot
be noticed. There are 30 pings. 13 are pinged LOW, and 17 are pinged HIGH.
Therefore, the probability is 17/30, which is 56.66%.

In general, if a node is floating and its reference voltage is near HIGH or LOW at
ping start, its floating probability will be around 50%. Next, if the reference
voltage is somewhere between HIGH or LOW (for example, VDD/2), the floating
probability will be 100%.

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Appendix: Floating Node Detection

A floating (or highz) node is a node that does not have a path to VDD or GND. In other
words, if a node has a path to VDD, it is not a highz node. If a node has a path to GND,
it is not a highz node. If a node does NOT have a path to VDD and GND, it is a highz
node.

The floating (or highz) node-detection algorithm is based on the state of individual
devices, which may be either ON or OFF. Such a state is defined by a Boolean
expression called a conducting rule, which may be either TRUE or FALSE.

Consider the following conducting rules:

1. BJT is in ON state if “ic > BJT_ITH” or “vbe > BJT_VBE” is TRUE, where ic
and vbe are the collector current and voltage difference between base and
emitter, respectively, of a BJT. BJT_ITH and BJT_VBE are parameters given by
a user.
2. Diode is in ON state if “vac > DIODE_VTH” is TRUE, where vac is the voltage
across the diode. DIODE_VTH is the parameter given by a user.
3. MOSFET is in ON state if the region is either triode or saturation.
4. For more conducting rules, see help by typing:

%spectre –h dyn_highz

A single node can have many routes to VDD or GND. The algorithm will check all
possible routes for each node to VDD or GND. If any route contains devices in ON state,
such a node has a path to VDD or GND. However, if a node does not have any path to
VDD or GND, it is considered as floating.

The user can set the BJT_ITH and BJT_VBE parameters in the dyn_highz and
dyn_floatdcpath checks.

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Appendix: Ground Node in Virtuoso

The design check is netlist-based and requires to be set up to match the nodes defined
in the netlist. In Virtuoso, when you add a gnd, (by adding the analogLib->gnd
component), the net name appears to be gnd!. This is shown in the following figure.

net2

net1

gnd

When the netlist is formed, the netlist does not contain gnd!. However, ground is
defined by “0”, as follows:

global 0 vdd!

// Library name: My_library

// Cell name: My_case

// View name: schematic

NM2 (net1 net2 0 0)

Users working with Virtuoso might consider ground as gnd!, and will most likely use the
following statement:

chk1 dyn_floatdcpath net=[vdd! gnd!] …

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However, the checker will not be able to find the gnd! node in the netlist and issue the
following warning:

WARNING (SPECTRE-20019):

Node 'gnd!' not found in the floatdcpath checker 'chk1'.

The checker is ignored.

The workaround is to check the netlist and use the correct node name. For example,
use the following statement:

chk1 dyn_floatdcpath net=[vdd! 0] …

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