National Institute of Technology,

Silchar

Department of
Electronics and Instrumentation Engineering

Experiment No. – 12
Digital Electronics Lab (EI-216)

 NAME – Gaurab Das,

 SCHOLAR ID – 1915043,
 DATE OF SUBMISSION – 23/04/2021.

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 SHIFT REGISTER
Aim of the Experiment – To implement all four 3-bit shift
registers mentioned below using J-K flip-flop 
(1) SISO (2) SIPO (3) PISO (4) PIPO

Objective – The main objective of this experiment is to understand

the working and construction of some popular shift registers.

Software Used – CircuitVerse for simulation purpose.

Theory –
 Introduction – The shift register is a sequential logic circuit that
stores binary data (multiple 1’s and 0’s) and used to transfer data in
digital systems. The contents of a register are shifted once (either left
or right) in every clock cycle, so it is called as shift register.

Shift registers consists of an arrangement of flip-flops. As a flip-flop

has 1-bit memory, so the storage capacity of a register is determined
by the number of flip-flops used. An n-bit register is a collection of n
D flip-flops (with a common clock input). So, a 3-bit register contains
three flip-flops and is used to store a total of three bits. Shift registers
allow transfer of data from a stage to another within the register or
into or out of the register, as per the clock input.

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 Basic Concept of D flip flop –

Symbol 

Truth Table 

Clock D Q

1 0 0

1 1 1

Suppose the flip-flop is positive edge triggered, then 

 If D = 1 is applied at the positive going edge of the clock, then Q
becomes 1 or remains same if it was already 1.
 If D = 0 is applied at the positive going edge of the clock, then Q
becomes 0 or remains same if it was already 0.

Hence, D flip-flop stores one bit of data and can be called as a single-
bit register.

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 Types of shift registers – Shift registers can be classified on
the basis in which data is entered into the register for storage and the
way in which data is outputted from the register.

Thus, the classification is 

(1) Serial-Input Serial-Output (SISO) shift register,
(2) Serial-Input Parallel-Output (SIPO) shift register,
(3) Parallel-Input Serial-Output (PISO) shift register, and
(4) Parallel-Input Parallel-Output (PIPO) shift register.

 SISO shift register – Data input comes in serially, means one

bit at a time and stored output too goes out serially on an another line.

Construction  Let us consider a 4-bit SISO shift register designed

using four positive edge triggered D flip-flops with serial input line
(D0) and serial output line (Q3).
 Serial data input is placed on D0 input of 1st flip-flop (FF0),
 Q0 output of 1st flip-flop goes to D1 input of 2nd flip-flop (FF1),
 Q1 output of 2nd flip-flop goes to D2 input of 3rd flip-flop (FF2),
 Q2 output of 3rd flip-flop goes to D3 input of 4th flip-flop (FF3), and
 Q3 output of fourth flip-flop is finally taken out.

Circuit Diagram 

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Working  Suppose the register is initially clear (means Q3 = Q2 =
Q1 = Q0 = 0), then the steps to store the four bits (1010) are 

 Let us place bit by bit from left to right starting with left most bit.
So first of all, 1 is placed on the data input line making D0 = 1 for
FF0. The first positive edge of the clock sets first flip-flop (means
FF0 stores the data input, Q0 = 1).
 Next, the second bit which is a 0 is placed on the data input line
making D0 = 0 for FF0 and D1 = 1 for FF1 as D1 input of FF1 is
connected to Q0 output. The second positive edge of the clock sets
second flip-flop (means FF1 stores the output of FF0, Q1 = 1) and
resets first flip-flop (means FF0 stores the data input, Q0 = 0). So
the data stored in FF0 is shifted to FF1 and FF0 stores the input
data.
 Again, the third bit which is a 1 is placed on the data input line
making D0 = 1 for FF0, D1 = 0 for FF1 as D1 input of FF1 is
connected to Q0 output and D2 = 1 for FF2 as D2 input of FF2 is
connected to Q1 output. The third positive edge of the clock sets
third flip-flop (means FF2 stores the output of FF1, Q2 = 1), resets
second flip-flop (means FF1 stores the output of FF0, Q1 = 0) and
sets first flip-flop (means FF0 stores the data input, Q0 = 1). So the
data stored in FF1 is shifted to FF2, data stored in FF0 is shifted to
FF1 and FF0 stores the input data.
 The last bit which is a 0, is placed on the data input line making D0
= 0 for FF0, D1 = 1 for FF1 as D1 input of FF1 is connected to Q0
output, D2 = 0 for FF2 as D2 input of FF2 is connected to Q1 output
and D3 = 1 for FF3 as D3 input of FF3 is connected to Q2 output.
The fourth positive edge of the clock sets fourth flip-flop (means
FF3 stores the output of FF2, Q3 = 1), resets third flip-flop (means
FF2 stores the output of FF1, Q2 = 0), sets second flip-flop (means
FF1 stores the output of FF0, Q1 = 1) and resets first flip-flop
(means FF0 stores the data input, Q0 = 0). So the data stored in FF2
is shifted to FF3, data stored in FF1 is shifted to FF2, data stored in

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 FF0 is shifted to FF1 and FF0 stores the input data. That is how,
four bits are serially entered into the shift register and stored.
To get remaining data output, bits are further shifted serially out and
become available at Q3. After fourth positive edge of the clock, we
have left most bit at Q3 (means Q3 = 1). Similarly after fifth, sixth and
seventh positive edge of the clock, we have Q3 = 0, Q3 = 1 and Q3 = 0
respectively. After eighth positive edge of the clock, the register is
clear again.

Timing Diagram 

 SIPO shift register – Data input comes in serially (one bit at a

time) and stored output goes out in parallel (output of each stage is
available). All bits are available at the output line simultaneously after
the data is stored.

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Construction  Let us consider a 4-bit SIPO shift register designed
using four positive edge triggered D flip-flops 
 Serial data input is placed on D0 input of 1st flip-flop (FF0),
 Q0 output of 1st flip-flop goes into D1 input of 2nd flip-flop (FF1),
 Q1 output of 2nd flip-flop goes into D2 input of 3rd flip-flop (FF2),
 Q2 output of 3rd flip-flop goes into D3 input of 4th flip-flop (FF3),
 And finally, output of each flip-flop is taken out. A 4-bit SIPO shift
register has one serial input line (D0) and four parallel output lines
(Q3, Q2, Q1 and Q0).

Circuit Diagram 

Working  Suppose the register is initially clear (means Q3 = Q2 =

Q1 = Q0 = 0), then the steps to store the four bits (1110) are 

 Let us place bitwise starting with left most bit. So first of all, 1 is
placed on the data input line making D0 = 1 for FF0. The first
positive edge of the clock sets first flip-flop (means FF0 stores the
data input i.e., Q0 = 1).
 Next, the second bit which is a 1 is placed on the data input line
making D0 = 1 for FF0 and D1 = 1 for FF1 as D1 input of FF1 is
connected to Q0 output. The second positive edge of the clock sets
second flip-flop (means FF1 stores the output of FF0, Q1 = 1) and
leaves first flip-flop unchanged (means FF0 stores the data input,
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 Q0 = 1). So, the data stored in FF0 is shifted to FF1 and FF0 stores
the input data.
 Again, the third bit which is a 1 is placed on the data input line
making D0 = 1 for FF0, D1 = 1 for FF1 as D1 input of FF1 is
connected to Q0 output and D2 = 1 for FF2 as D2 input of FF2 is
connected to Q1 output. The third positive edge of the clock sets
third flip-flop (means FF2 stores the output of FF1, Q2 = 1) and
leaves first as well as second flip-flop unchanged (means FF1
stores the output of FF0 and FF0 stores the data input, Q0 = Q1 = 1).
So, the data stored in FF1 is shifted to FF2, data stored in FF0 is
shifted to FF1 and FF0 stores the input data.
 The last bit which is a 0 is placed on the data input line making D0
= 0 for FF0, D1 = 1 for FF1 as D1 input of FF1 is connected to Q0
output, D2 = 1 for FF2 as D2 input of FF2 is connected to Q1 output
and D3 = 1 for FF3 as D3 input of FF3 is connected to Q2 output.
The fourth positive edge of the clock sets fourth flip-flop (means
FF3 stores the output of FF2, Q3 = 1), leaves second as well as third
flip-flop unchanged (means FF2 stores the output of FF1 and FF1
stores the output of FF0, Q1 = Q2 = 1) and resets first flip-flop
(means FF0 stores the data input, Q0 = 0). So the data stored in FF2
is shifted to FF3, data stored in FF1 is shifted to FF2, data stored in
FF0 is shifted to FF1 and FF0 stores the input data. That is how
four bits are serially entered into the shift register and stored. So
after fourth positive edge of the clock, data output is available at
Q3, Q2, Q1 and Q0.

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 Timing Diagram 

 PISO shift register – Data input comes in parallel; that means

bits are entered simultaneously into respective stages and the stored
output goes out serially, bit by bit on one line.

Construction  Let us consider a 4-bit PISO shift register designed

using four positive edge triggered D flip-flops. It has four parallel
input lines (D3, D2, D1 and D0) and one serial output line (Q3).
Level of Shift/Load signal allows four bits of data to load in parallel
or shift in the register 
 When Shift/Load = 0, data input comes in and the positive edge
of the clock sets or resets flip-flops according to the input; which
means data present at D3, D2, D1 and D0 input is loaded in parallel
into the register simultaneously.

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 When Shift/Load = 1, shifting operation takes place and the Q0
output of first flip-flop goes to D1 input of second flip-flop (FF1),
Q1 output of second flip-flop goes to D2 input of third flip-flop
(FF2) and Q2 output of third flip-flop goes to D3 input of fourth
flip-flop (FF3).

Circuit Diagram 

Working  Suppose the register is initially clear (means Q3 = Q2 =

Q1 = Q0 = 0) and Shift/Load = 1, then the steps to store the four bits
(0101) into the register are 

 Let us place each bit in parallel into the register. The left most bit
which is a 0 is placed on Data3 input line. The second bit which is
a 1 is placed on Data2 input line. The third bit which is a 0 is
placed on Data1 input line and the right most bit which is a 1 is
placed on Data0 input line.
 As Shift/Load signal goes low, bits placed on Data3, Data2, Data1
and Data0 input line can reach D3, D2, D1 and D0 input of the
corresponding flip-flop making D3 = 0, D2 = 1, D1 = 0 and D0 = 1.
That is how, the four bits are entered in parallel into the register.
 The first positive edge of the clock resets fourth flip-flop (means
FF3 stores D3 input, Q3 = 0), sets third flip-flop (means FF2 stores
D2 input, Q2 = 1), resets the second flip-flop (means FF1 stores D1
input, Q1 = 0) and sets first flip-flop (means FF0 stores D0 input,
Q0 = 1). That is how, four bits of data are stored in the register and

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 left most bit is available at Q3. To get remaining data output, bits
are further shifted serially out and become available at Q3.
 The moment Shift/Load signal goes high, data outputs Q0, Q1, Q2
and Q3 remain same and data inputs D0, D1, D2 and D3 changes
according to the previous stage output as Q0 output of first flip-flop
can reach D1 input of second flip-flop (means D1 = Q0), Q1 output
of second flip-flop can reach D2 input of third flip-flop (means D2
= Q1) and Q2 output of third flip-flop can reach D3 input of fourth
flip-flop (means D3 = Q2).
 The second positive edge of the clock sets fourth flip-flop (means
FF3 stores the output of FF2, Q3 = 1), resets third flip-flop (means
FF2 stores the output of FF1, Q2 = 0), sets second flip-flop (means
FF1 stores the output of FF0, Q1 = 1) and resets first flip-flop (as
no data input, so Q0 = 0). So, the data stored in FF2 is shifted to
FF3, data stored in FF1 is shifted to FF2 and data stored in FF0 is
shifted to FF1. That is how, second bit is available at Q3.
 The third positive edge of the clock resets fourth flip-flop (means
FF3 stores the output of FF2, Q3 = 0), sets third flip-flop (means
FF2 stores the output of FF1, Q2 = 1), resets second flip-flop (as no
data input, so Q1 = 0) and leaves the first flip-flop unchanged (as
no data input, so Q0 = 0). So, the data stored in FF2 is shifted to
FF3 and data stored in FF1 is shifted to FF2. That is how, third bit
is available at Q3.
 The fourth positive edge of the clock sets fourth flip-flop (means
FF3 stores the output of FF2, Q3 = 1), resets third flip-flop (as no
data input, so Q2 = 0) and leaves first as well as second flip-flop
unchanged (as no data input, so Q0 = Q1 = 0). So, the data stored in
FF2 is shifted to FF3 and the right most bit is available at Q3.
 The fifth positive edge of the clock resets fourth flip-flop (as no
data input, so Q3 = 0) and leaves first, second as well as third flip-
flop unchanged (as no data input, so Q0 = Q1 = Q2 = 0). Thus, the
register is clear again.

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 Timing Diagram 

 PIPO shift register – Data input comes in parallel, that means

bits are entered simultaneously into respective stages and the stored
output goes out in parallel; thus output of each stage is available.

Construction  Let us consider a 4-bit PIPO shift register designed

using four positive edge triggered D flip-flops and it has four parallel
input lines (D3, D2, D1 and D0) and four parallel output lines (Q3, Q2,
Q1 and Q0).
Level of Shift/Load signal allows four bits of data to load in parallel
or shift in the register 
 When Shift/Load = 0, data input comes in and the positive edge
of the clock sets or resets flip-flops according to the input; which
means data present at D3, D2, D1 and D0 input is loaded in parallel
into the register simultaneously.

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 When Shift/Load = 1, shifting operation takes place and Q0 output
of first flip-flop goes to D1 input of second flip-flop (FF1), Q1
output of second flip-flop goes to D2 input of third flip-flop (FF2)
and Q2 output of third flip-flop goes to D3 input of fourth flip-flop
(FF3).

Circuit Diagram 

Working  Suppose the register is initially clear (means Q3 = Q2 =

Q1 = Q0 = 0) and Shift/Load = 1, then the steps to store the four bits
(1101) into the register are 

 Let us place each bit in parallel into the register. The left most bit
which is a 1 is placed on Data3 input line. The second bit which is
a 1 is placed on the Data2 input line. The third bit which is a 0 is
placed on the Data1 input line and the right most bit which is a 1 is
placed on Data0 input line.
 As Shift/Load signal goes low, bits placed on Data3, Data2, Data1
and Data0 input lines can reach D3, D2, D1 and D0 input lines of
corresponding flip-flop making D3 = 1, D2 = 1, D1 = 0 and D0 = 1.
That is how, four bits are entered in parallel into the register.
 The first positive edge of the clock sets fourth flip-flop (means FF3
stores D3 input, Q3 = 1), sets third flip-flop (means FF2 stores D2
input, Q2 = 1), resets second flip-flop (means FF1 stores D1 input,
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 Q1 = 0) and sets first flip-flop (means FF0 stores D0 input, Q0 = 1).
That is how, the four bits of data are stored in the register and are
available at Q3, Q2, Q1 and Q0.
 The moment Shift/Load signal goes high, data output Q0, Q1, Q2
and Q3 remain same and data input lines D0, D1, D2 and D3 change
according to the previous stage output as Q0 output of first flip-flop
can reach D1 input of second flip-flop (means D1 = Q0), Q1 output
of second flip-flop can reach D2 input of third flip-flop (means D2
= Q1) and Q2 output of third flip-flop can reach D3 input of fourth
flip-flop (means D3 = Q2).
 The second positive edge of the clock leaves the fourth flip-flop
unchanged (means FF3 stores the output of FF2, Q3 = 1), resets
third flip-flop (means FF2 stores the output of FF1, Q2 = 0), sets
second flip-flop (means FF1 stores the output of FF0, Q1 = 1) and
resets first flip-flop (as no data input, so Q0 = 0). So the data stored
in FF2 is shifted to FF3, data stored in FF1 is shifted to FF2 and
data stored in FF0 is shifted to FF1.
 The third positive edge of the clock resets fourth flip-flop (means
FF3 stores the output of FF2, Q3 = 0), sets third flip-flop (means
FF2 stores the output of FF1, Q2 = 1), resets second flip-flop (as no
data input, so Q1 = 0) and leaves the first flip-flop unchanged (as no
data input, so Q0 = 0). So, the data stored in FF2 is shifted to FF3
and data stored in FF1 is shifted to FF2.
 The fourth positive edge of the clock sets fourth flip-flop (means
FF3 stores the output of FF2, Q3 = 1), resets third flip-flop (as no
data input, so Q2 = 0) and leaves first as well as second flip-flop
unchanged (as no data input, so Q0 = Q1 = 0). So, the data stored in
FF2 is shifted to FF3.
 The fifth positive edge of the clock resets fourth flip-flop (as no
data input, so Q3 = 0) and leaves first, second as well as third flip-
flop unchanged (as no data input, so Q0 = Q1 = Q2 = 0). Thus, the
register is clear again.

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Timing Diagram 

Simplified Circuit Diagram 

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 Conversion of J-K flip-flop into D flip flop –

J-K Flip-Flop  J-K flip flop is basically an S-R flip-flop having

feedback from the output lines. It prevents the invalid/not used state
that is obtained from S-R flip flop when both the inputs are 1.
D Flip-Flop  D flip-flop is a modified S-R flip-flop which has an
additional inverter at the input. It prevents the inputs from becoming
the same value.
Conversion – Step 1  We construct the characteristic table of D
flip-flop and excitation table of J-K flip-flop 

Conversion – Step 2  Using K-map simplification, we find the

boolean expression of J and K in terms of D 

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 𝐉=𝐃
𝐊=𝐃

Conversion – Step 3  We construct the circuit diagram of the

conversion of J-K flip-flop into D flip-flop 

Experimental Setup –
 SISO shift register

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 SIPO shift register

 PISO shift register

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 PIPO shift register

Result – We have correctly implemented the logic circuits for all

four 3-bit shift registers  Series-Input Series-Output (SISO), Series-

Input Parallel-Output (SIPO), Parallel-Input Series-Output (PISO) and
Parallel-Input Parallel-Output (PIPO) using J-K flip-flop.

Conclusion – After successfully achieving the aim and objective

of this experiment, we can conclude by saying that we have understood
the working and construction of some popular shift registers.

Signature

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