Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs

- Construct the circuit and apply the power (remember to note IC codes and their pin numbers).
Apply all possible combinations to the input; obtain the output value then take note of the outputs F2
in the Table 1.3.

Student’s implementation on breadboard

 Give your comments on F1 and F2 results:

The results of them are the same.

EXPERIMENT 4
 Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs

❑
Objectives: Implementation of a Boolean function f ( x , y , z )=∑ (2 , 3 , 5 ,7 ) by using a 8x1
❑
Multiplexer.
Connection diagram and function table:

Equipments:
- Analog Discovery Studio
- Integrated Circuits (ICs): 74LS151, 74LS04.
- Connection wires.
Procedure:
Draw the schematic diagram to implement the boolean function using 74LS151.
 Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs

Application cicruit

- Construct the circuit and apply the power (remember to note IC pin numbers).
- Apply all possible combinations to the inputs and obtain and take note of the outputs F Test in
the Table 1.4.

x y z f fTest
0 0 0 0 0
0 0 1 0 0
0 1 0 1 1
0 1 1 1 1
1 0 0 0 0
1 0 1 1 1
1 1 0 0 0
1 1 1 1 1
 Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs

Table 1.1

Student’s implementation on breadboard

 Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs

EXPERIMENT 5
❑
Objectives: Implementation of a Boolean function ( x , y , z )=∑ ( 2 , 3 ,5 , 7 ) by using a 3x8
❑
Decoder.
Equipments: x y z f fTest
- Analog Discovery Studio 0 0 0
- Integrated Circuits (ICs): 74LS138, and other logic 0 0 1
gates. 0 1 0
- Connection wires.
0 1 1
Connection diagram and function table: 1 0 0
1 0 1
1 1 0
1 1 1
Table 1.2
 Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs

Procedure:
Draw the schematic diagram to implement the boolean function using 74LS138.
 Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs

Application cicruit

- Construct the circuit and apply the power (remember to note IC pin numbers).
- Apply all possible combinations to the inputs and obtain and take note of the outputs F Test in
the Table 1.5.
Student’s implementation on breadboard
Lab 1: Implementation of Boolean function on breadboard with logic gates and functional ICs
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

LAB 1: IMPLEMENTATION OF
BASIC LOGIC GATES AND
FUNCTIONAL ICs ON FPGA
Student’s names: Class:
Student ID: Date:

A. PRELAB
In Lab 2, the project use the LEDR, LEDG, and SW as peripherals. Below are the basic
headers code of these peripherals when students synthesize a project on Intel Quartus. (Note:
Import file DE2_pin_list/assignment).

Note, the top-level file of the project must be named the name of the header file, for example
"lab2tn1_wrapper", with the module "lab2tn1" being the module containing the code
describing the design of experiment 1.

Ex: The experiment of writing hardware design in SystemVerilog language for the function
f ( x , y , z )=x yz as experiment 1 of lab 2, we have the following SystemVerilog code:
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

Figure 2.1: Implementation of f ( x , y , z )=x yz – module “lab2tn1”

Below is top level “lab2tn1_wrapper” that implement f ( x , y , z )=x yz :

Figure 2.2: Implementation of f ( x , y , z )=x yz – module “lab2tn1_wrapper”

Next, students perform the simulation, and load the Kit as instructed at Lab 0.
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

For the experiments that require the use of IC 74LS151/74LS138, students write the code
describing this IC and call that module as above.
PREPARATION 1
Objective: Implementation of Boolean function f ( x , y , z )=x yz + xy z + xy on FPGA DE2.
Procedure:
● Construct the truth table of f ( x , y , z )=x yz + xy z + xy
● Write the SystemVerilog code that describe f ( x , y , z )=x yz + xy z + xy s instructed in
lab 0 with the following pin assignment:
○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively.
○ Pin f assigned to LEDG0.
● Compile and simulate the project. The output waveform have to show all possible
input combinations. Capture the output waveform.

Truth table SystemVerilog code

Waveform:
Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

PREPARATION 2
Objectives: Write SystemVerilog code to X Y Z F Fsim FKit
describe the truth table in Table 2.1. 0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Table 2.3

Procedure:
● Write the SystemVerilog code that describe the digital circuit in Figure 2.3 with the
following pin assignment:
○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively.
○ Pin f assigned to LEDG0.
● Compile and simulate the project. The output waveform have to show all possible
input combinations. Capture the output waveform.
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

Truth table SystemVerilog code

Waveform:

PREPARATION 3
Objective: Write SystemVerilog code to describe the digital circuit in Figure 2.3.
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

Figure 2.3

Procedure:
● Write the SystemVerilog code that describe the digital circuit in Figure 2.3 with the
following pin assignment:
○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively.
○ Pin f assigned to LEDG0.
● Compile and simulate the project. The output waveform have to show all possible
input combinations. Capture the output waveform.

Truth table SystemVerilog code

Waveform:
Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

PREPARATION 4
Objective: Write SystemVerilog code to describe IC Multiplexer 74LS151. Implement
❑
function f ( x , y , z )=∑ (1 , 2 , 4 , 7 ) using that multiplexer.
❑

Procedure:
● Write SystemVerilog code describe IC multiplexer 74LS151 operation.
● Using above multiplexer, write SytemVerilog code implementing Boolean function
❑
f ( x , y , z )=∑ (1 , 2 , 4 , 7 ) :
❑

○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0

respectively
○ Pin f assigned to LEDG0
○ Call IC 74LS151 as a submodule.
● Compile and simulate the project. The output waveform have to show all possible
input combinations. Capture the output waveform.
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

Truth table SystemVerilog code

Waveform:

PREPARATION 5
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

Objective: Write SystemVerilog code to describe IC Decoder 74LS138. Implement function

❑
f ( x , y , z )=∑ ( 0 ,2 , 5 ,7 ) using that decoder.
❑

Procedure:
● Write SystemVerilog code describe IC decoder 74LS138 operation.
● Using above decoder, write SytemVerilog code implementing Boolean function
❑
f ( x , y , z )=∑ ( 0 ,2 , 5 ,7 ):
❑

○ Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0

respectively
○ Pin f assigned to LEDG0
○ Call IC 74LS138 as a submodule.
● Compile and simulate the project. The output waveform have to show all possible
input combinations. Capture the output waveform.

Truth table SystemVerilog code

Waveform:
Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA
Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

B. LAB MANUAL:

I. OBJECTIVES:

- Understand how to use FPGA kits, programming software .

- Understand how to design a basic functional ICs on FPGA
- Understand the process of describing hardware on FPGAs.

II. LAB PREPARATION:

- To prepare well for the test, students MUST read Appendix 1 first and complete the
steps of Sample lab in Appendix 2, and submit it with Prelab 2 before entering class.
- Students must complete and submit Prelab 2 before entering class.
- Students read the appendix and the Kit DE2 Manual to understand how to use the
DE2 Kit, wiring, peripherals, and how to use Quartus software to simulate and
synthesize circuits. Students refer to the documentation to understand how to write
hardware designs in the SystemVerilog language.

III. LAB INSTRUCTIONS:

EXPERIMENT 1
Objectives: Implementation of a function math f ( x , y , z )=x yz + xy z + xy on DE 2 kit.
Procedure:
x y z f fSim fKit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

Table 2.4

 Apply all possible combinations to the inputs and take note the outputs in the f
column of Table 2.2.

 Draw the logic diagram of F:

 Write the SystemVerilog describe the operation of f ( x , y , z )=x yz + xy z + xy with the

pin assignment as follows:
o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively.
o Pin f assigned to LEDG0.
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

 Synthesize the SystemVerilog design and take note the output in the fsim column in
Table 2.2.

(Insert a photo demonstrating simulation results)

 Students view the result of the circuit (Tool  Netlist Viewer  RTL Viewer). Is
this result similar to the logic gate diagram drawn above? Exlain.

(RTL viewer result)

 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

 Download the code to DE2 Kit. Does the design perform exactly as required? Take
note the results in f Kit column of Table 2.2

(Project demonstration on DE2 kit)

EXPERIMENT 2
Objectives: Implementation of a boolean function given in the truth table on DE 2 kit.

X Y Z F Fsim FKit

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 1
Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

Table 2.5

Procedure:
 Write the Boolean expression of f (x, y, z):

 Draw the logic diagram of f:

 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

 Write the SystemVerilog describe the operation of f ( x , y , z )with the pin assignment
as follows:
o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively.
o Pin f assigned to LEDG0.

 Synthesize the SystemVerilog design and take note the output in the fsim column in
Table 2.3.

(Insert a photo demonstrating simulation results)

 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

 Students view the result of the circuit (Tool  Netlist Viewer  RTL Viewer). Is
this result similar to the logic gate diagram drawn above? Exlain.

(RTL viewer result)

 Download the code to DE2 Kit. Does the design perform exactly as required? Take
note the results in f Kit column of Table 2.3.

(Project demonstration on DE2 kit)

 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

EXPERIMENT 3
Objectives: Implementation of a boolean function given in the following schematic.
X Y Z Fsim FKit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Figure 2.4
Table 2.6

Procedure:

 Write the SystemVerilog describe the operation of f ( x , y , z )with the pin assignment
as follows:
o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0
respectively.
o Pin f assigned to LEDG0.
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

 Synthesize the SystemVerilog design and take note the output in the fsim column in
Table 2.4.

(Insert a photo demonstrating simulation results)

 Students view the result of the circuit (Tool  Netlist Viewer  RTL Viewer). Is
this result similar to the logic gate diagram drawn above? Exlain.

(RTL viewer result)

 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

 Download the code to DE2 Kit. Does the design perform exactly as required? Take
note the results in f Kit column of Table 2.4.

(Project demonstration on DE2 kit)

EXPERIMENT 4
Objectives: Write SystemVerilog code to describe IC
Multiplexer 74LS151.
❑
Implement function f ( x , y , z )=∑ (1 , 2 , 4 , 7 ) using that
❑
multiplexer.
Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

x y z f fsim fKit
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

Table 2.7

Procedure:
 Draw the circuit that implement f(x,y,z) using 74LS151.

 Write SystemVerilog code describe IC multiplexer 74LS151 operation.

 Using above multiplexer, write SytemVerilog code implementing Boolean function
❑
f ( x , y , z )=∑ (1 , 2 , 4 , 7 ) :
❑

o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0

respectively
o Pin f assigned to LEDG0
o Call IC 74LS151 as a submodule.
 Synthesize the SystemVerilog design and take note the output in the fsim column in

Table 2.5. (Insert a photo demonstrating simulation results)

 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

 Students view the result of the circuit (Tool  Netlist Viewer  RTL Viewer). Is
this result similar to the logic gate diagram drawn above? Exlain.

(RTL viewer result)

 Download the code to DE2 Kit. Does the design perform exactly as required? Take
note the results in f Kit column of Table 2.5.

(Project demonstration on DE2 kit)

 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

EXPERIMENT 5
Objectives: Write SystemVerilog code to describe IC x y z f fsim fKit
Decoder 74LS138. 0 0 0
❑
0 0 1
Implement function f ( x , y , z )=∑ ( 0 ,2 , 5 ,7 ) using that
❑
0 1 0
decoder.
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2.8

Procedure:
 Draw the circuit that implement f(x,y,z) using 74LS138.
 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

 Write SystemVerilog code describe IC decoder 74LS138 operation.

 Using above multiplexer, write SytemVerilog code implementing Boolean function
❑
f ( x , y , z )=∑ ( 0 ,2 , 5 ,7 ):
❑

o Pins x, y, z assigned to SW2, SW1, SW0 and LEDR2, LEDR1, LEDR0

respectively
o Pin f assigned to LEDG0
o Call IC 74LS138 as a submodule.
 Synthesize the SystemVerilog design and take note the output in the fsim column in

Table 2.5. (Insert a photo demonstrating simulation results)

 Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA

 Students view the result of the circuit (Tool  Netlist Viewer  RTL Viewer). Is
this result similar to the logic gate diagram drawn above? Exlain.

(RTL viewer result)

 Download the code to DE2 Kit. Does the design perform exactly as required? Take
note the results in f Kit column of Table 2.5.

(Project demonstration on DE2 kit)

Lab 2: Implementation of Boolean function with logic gates and functional ICs on FPGA
 Lab 3: Combinational Circuit – Sequential Circuit Design

LAB 2: COMBINATIONAL CIRCUIT

AND SEQUENTIAL CIRCUIT DESIGN
Student’s name: Class:
Student ID: Date:

A. PRELAB

Question 1: Design Full Adder block.

A full adder is a combinational circuit that performs the arithmetic sum of three input bits. It consists of
three inputs and two outputs. Two of the input variables, denoted by A and B, represent the two significant
bits to be added. The third input, Ci (input carry), represents the carry from previous lower significant
position. Two outputs are S (Sum) and Co (output carry).
Truth table: Logic Diagram:
A B Ci S Co

Table 3.9 The truth table of the Full Adder

Implement Full Adder on breadboard using logic gates.
List all required ICs:
 Lab 3: Combinational Circuit – Sequential Circuit Design

Application Circuit:
GND

+5V
14

13

12

11

10

14

13

12

11

10

14

13

12

11

10
9

8
1 2 34

ON
1

7
GND
+5V

Question 2: Design a 4 bit full adder/full subtractor circuit using IC 74LS283 . The circuit has three inputs:
Sel (1bit), A (4bit) và B (4bit) and 2 outputs: S (4bit), Cout (1bit).
- When Sel = 0, S = A + B
- When Sel = 1, S = A – B
74LS283 is an IC 4-bit ripple-carry adder. It adds two 4-bit binary numbers [A (A4A3A2A1) and B
(B4B3B2B1)] and a carry in bit (Cin). It is composed of four fulladders. The augend’s bits of “B” are
added to the addend bits of “A” respectfully of their binary position. Each bit addition produces a sum (S)
and a carry out (Co). The carry out is then transmitted to the carry in (Ci) of the next higher-order bit. The
final result produces a sum of four bits S (S4S3S2S1) plus a carry out (Cout) bit.
 Lab 3: Combinational Circuit – Sequential Circuit Design

Figure 3.5: 4-bit parallel adder

Figure 3.6: IC 74LS283 – pin diagram

Draw logic diagram and show how to design: 4-bit parallel adder
 Lab 3: Combinational Circuit – Sequential Circuit Design

List all required IC to implement 4-bit parallel adder circuit:

Application circuit:

Question 3: Design 0 7 up counter, using IC D-FF 74LS74

 Lab 3: Combinational Circuit – Sequential Circuit Design

Asynchronous counters are counters that are configured such that all flip-flops are not triggered
simultaneously by a common clock. Since each flip-flop in the counter is triggered by the flip-flop in
series before it, these counters are also referred to as ripple counters. There are many types of
asynchronous counters. An UP counter counts in an ascending sequence while a DOWN counter counts
in a descending sequence. A counter can also count UP and DOWN on command; such a counter is
known as an UP/DOWN counter.

Figure 3.7: Schematic symbol and Function symbol of IC 74LS74

Logic diagram of 0 – 7 up counter:

 Lab 3: Combinational Circuit – Sequential Circuit Design

Application circuit:

Question 4: Design sequential circuit for the state diagram in Figure 3.4:
 Lab 3: Combinational Circuit – Sequential Circuit Design

State table:

TT hiện tại Ngõ vào TT kế tiếp

S1 S0 X S1+ S0+
A 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 1
Table 3.10
Figure 3.8
Logic diagram:
S1+ = ; S0+ =
 Lab 3: Combinational Circuit – Sequential Circuit Design

Required ICs:

Application circuit:
GND

+5 V

9
8

9
8

9
8
14

13

12

11

10

14

13

12

11

10

14

13

12

11

10
1 2 34

ON
1

7
GND
+5 V
 Lab 3: Combinational Circuit – Sequential Circuit Design

B. LAB MANUAL:

I. OBJECTIVES

 Design 4-bit parallel adder/subtractor using IC 74LS283.

 Know how to design combinational circuit and sequential circuit.
II. PREPARATION

Students have to complete Prelab before class. Students without lab preparation won’t
be allowed to join in the class..
III. LAB INSTRUCTIONS
EXPERIMENT 1
Objective: Using logic gates, design Full Adder circuit.
Equipments:
- Analog Discovery Studio
- Integrated Circuits (ICs) : 74LS86, 74LS08, 74LS32
- Connection wires.
Procedure:
 Logic diagram:
 Lab 3: Combinational Circuit – Sequential Circuit Design

 Application circuit:

GND

+5V
14

13

12

11

10

14

13

12

11

10

14

13

12

11

10
9

8
1 2 34

ON
1

7
GND
+5V

 Construct the circuit and apply the power.

 Apply all possible combinations to the inputs of the circuit and experimentally
obtain the output values given in Table 3.3 and take note of the outputs in the
Table.
INPUTS OUTPUTS
A B Ci S Co

Table 3.11
 Lab 3: Combinational Circuit – Sequential Circuit Design

EXPERIMENT 2
Objectives: Design a 4 bit full adder/full subtractor circuit using IC 74LS283. The circuit has three inputs:
Sel (1bit), A (4bit) và B (4bit) and 2 outputs: S (4bit), Cout (1bit).
- When Sel = 0, S = A + B
- When Sel = 1, S = A – B
Equipments:
- Analog Discovery Studio
- Integrated Circuits (ICs) : IC 74LS283, 74LS86
- Connection wires.
Procedure:
 Logic diagram:

 Application circuit:
 Lab 3: Combinational Circuit – Sequential Circuit Design

 Construct the circuit and apply the power. Apply all possible combinations to the

inputs (A4 A3 A2 A1 B4 B3 B2 B1) of the circuit and experimentally obtain the

output values given in Table 3.4 and take note of the outputs (Cout S4 S3 S2 S1)
in the Table 3.4:
A Số A Số B B Ngõ ra (bas
S (base (base
e 10)
10) 10)
A A3 A2 A1 B4 B3 B2 B1 Cou S4 S3 S2 S1
0 10 1 0 1 0 1 0 1 1 11
0 14 1 1 1 0 1 0 1 0 10
0 12 1 1 0 0 0 1 0 0 4
0 5 0 1 0 1 0 0 1 1 3
0 4 0 1 0 0 0 1 0 1 5
0 13 1 1 0 1 1 1 0 1 13
0 6 0 1 1 0 1 0 0 1 9
0 2 0 0 1 0 1 0 0 0 8
0 1 0 0 0 1 0 0 1 0 2
0 7 0 1 1 1 0 0 0 1 1
0 15 1 1 1 1 0 1 1 0 6
0 9 1 0 0 1 1 1 1 1 15
1 10 1 0 1 0 1 0 1 1 11
1 14 1 1 1 0 1 0 1 0 10
 Lab 3: Combinational Circuit – Sequential Circuit Design

1 12 1 1 0 0 0 1 0 0 4
1 5 0 1 0 1 0 0 1 1 3
1 4 0 1 0 0 0 1 0 1 5
1 13 1 1 0 1 1 1 0 1 13
1 6 0 1 1 0 1 0 0 1 9
1 2 0 0 1 0 1 0 0 0 8
1 1 0 0 0 1 0 0 1 0 2
1 7 0 1 1 1 0 0 0 1 1
1 15 1 1 1 1 0 1 1 0 6
1 9 1 0 0 1 1 1 1 1 15
 Lab 3: Combinational Circuit – Sequential Circuit Design

Table 3.12

EXPERIMENT 3
Objectives: Examination of D Flipflop – IC 74LS74.
Equipments:
- Analog Discovery Studio
- Integrated Circuits (ICs) : 74LS74.
- Connection wires.
Preliminary information: The schematic symbol and the function table of 74LS74 dual
rising edge triggered D flip-flops is shown in Fig. 3.5.
 Lab 3: Combinational Circuit – Sequential Circuit Design

Figure 3.9 The schematic symbol and the function table of 74LS74 dual rising edge triggered
D flip-flops.
Procedure:
 Logic diagram:

 Application circuit:
 Lab 3: Combinational Circuit – Sequential Circuit Design

 Construct the circuit and apply the power.

 Apply first the following Preset, Clear, D and then the CLK to the inputs of the
circuit, given in Table 3.5 (follow the given inputs from top to down) and
experimentally obtain the output values and take note of the outputs in the Table.
Notes: Output status changes only when rising edge clock appears. Rising edge clock
is created when you turn the switch from level 0 to level 1.
ASYNCHRONOUS INPUTS SYNCHRONOUS INPUTS OUTPUTS
COMMENT
PRESET CLEAR D CLK Q Q’
0 0 X X
1 0 X X
0 1 X X
1 1 0 0
1 1 1 0
1 1 0 1
1 1 1 1
1 1 0 ↓
1 1 1 ↓
1 1 0 ↑
1 1 1 ↑
 Lab 3: Combinational Circuit – Sequential Circuit Design

Table 3.13

EXPERIMENT 4
Objectives: Design 0 7 up counter, using IC D-FF 74LS74.
Equipments:
- Analog Discovery Studio
- Integrated Circuits (ICs) : 74LS74.
- Connection wires.
Procedure:
 Logic diagram:

 Application circuit:
 Lab 3: Combinational Circuit – Sequential Circuit Design

 Construct the circuit and apply the power. In the beginning of the experiment, connect
the Clock to a switch.

 Set the input A = 0 and B = 1, note the result:

 Set the input A = 1 and B = 0, note the result:

 Set A = B = 1, supply Clock signal using Digital Pattern Generator. Set the parameter
as below:
 Lab 3: Combinational Circuit – Sequential Circuit Design

- Click to Add channels  Signal  DIOx (x: 0 – 15)

- Output: PP (Push – Pull)
- Type: Clock
- Parameter1: change the frequency from 1Hz, 10Hz and 100Hz,… and observe the
operation of the counter. After which frequencies you cannot observe the changing
of count values by your eyes.

EXPERIMENT 5
Objectives: Design sequential circuit for the state
diagram in Figure 3.6.
Equipments:
- Analog Discovery Studio
- Integrated Circuits (ICs) : 74LS74, 74LS08,
74LS32.
- Connection wires.
Procedure:
Figure 3.10
 Logic diagram:
 Lab 3: Combinational Circuit – Sequential Circuit Design

 Application circuit:

GND

+5V

14

13

12

11

10

14

13

12

11

10

14

13

12

11

10
9

8
1 2 34

ON
1

7
GND
+5V

 Construct the circuit and apply the power.

 Reset the state machine to put it in state A.

Connect the Clock and input X to two DIOs of Analog Discovery Kit and set them as
a switch. Move the switch X to either on or off position according to the table, turn on
the switch and then turn off to make a pulse into CLK input

 Complete the table below to show the states corresponding to the given input
sequence:

Inpu 0 1 1 0 0 0 1
t

State A

Verify that this sequence follows the transitions as dictated by the state transition
table in Figure 3.6.
Lab 3: Combinational Circuit – Sequential Circuit Design
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

LAB 3: IMPLEMENTATION OF BASIC

COMBINATIONAL AND SEQUENTIAL
LOGIC CIRCUITS ON FPGA
Họ và tên: Lớp TN:
MSSV: Ngày:

A. PRELAB
PREPARATION 1
Objectives: Describe Full Adder circuit using SystemVerilog.
Read the following program.
module FA_ex1(
input A,
input B,
input Ci,
output S,
output Co);

assign S = A ^ B ^ Ci;
assign Co=(A&B)|(A&Ci)|(B&Ci);
Figure 4.11: Full Adder
endmodule
 Compile the above program and simulate the output waveform in all cases of the input.
Capture the output waveform..
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

PREPARATION 2
Objective: Describe 4-bit adder/subtractor using SystemVerilog.
Design 4-bit adder/subtractor which has 2 inputs A and B respectively, 1 output S and the
flags Ci and Co. Its operation depends on the input sel:
o sel=0: S = A + B
o sel=1: S = A - B

Students write the SystemVerilog code that performs the operation of the combinational
circuit in two methods:
- Method 1: Instantiate Full Adder module (using preparatory lesson 1).

Hint:
wire wire0,wire1,wire2
FA_ex1 u0(.Ci(0),.A(A[0]),.B(B[0]),.S(S[0]),.Co(wire0));
FA_ex1 u1(.Ci(wire1),.A([1]),.B([1]),.S(S[1]),.Co(wire1));
…

- Method 2: Write SystemVerilog code using data flow model.

Hint:
always@(*) assign S=(sel)?A+B:A-B;
if (sel)
…
else
…
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Compile the above program and simulate the output waveform in all cases of the input.
Capture the output waveform.

PREPARATION 3
Objective: Design the combinational circuit that decodes BCD numbers to common anode 7-
segment LED codes.
Complete the truth table of the decoder circuit:
I3 I2 I1 I0 g f e d c b a
0 0 0 0 1 0 0 0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0 Figure 4.12 Common anode 7-segment
1 0 0 1 LED
1 0 1 0 (source: internet)

1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table 4.14

 Write SystemVerilog code that describe the decoder.

 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

Hint: Use case statement….

input [3:0]I;
always@(*) begin
case(I)
4’b0000: out <= 7’b1000000;
4’b0001: out <= …
…
endcase;
end
 Compile the above program and simulate the output waveform in all cases of the input.
Capture the output waveform.

PREPARATION 4
Objective: Design a circuit that converts a pulse of frequency 50 MHz to a pulse of frequency
1 Hz.
Gợi ý:
- A pulse of frequency 50MHz will make 50 000 000 oscillations in 1s. (1 oscillation
consists of 1 high-level and 1 low-level).
- A pulse with a frequency of 1Hz will make 1 oscillation in 1s.
- Applying the principle of the counter circuit, the circuit receives an input pulse of 50MHz,
when the input pulse counts 25 000 000, that will reverse the state of the output pulse.
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

Hint:
integer i=0;
reg temp=0;
always_ff@(posedge clk)
begin
i = i + 1;
if (i == 25 000 000) begin
out = ~ out;
i = 0;
end
end

 Compile the above program and simulate the output waveform in all cases of the input.
Capture the output waveform.

PREPARATION 5
Objective: Describe a state machine using systemverilog.
 Draw a state machine for the requirement in experiment 5 of Lab 4. Students explain
the meaning of states and encode the state into a bit string.
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students design the state machine above using systemverilog language. (Refer to the
program below.) Assume the state machine have :
o Input: X (1 bits)
o Output: Y (1 bits)

There are 4 states: S0 (00), S1 (01), S2 (10), S3(11)

FSM code:

input X; // Input declaration

input clk; // Clock declaration
output reg [1:0]Y; // Output declaration
parameter S0=2'b00, S1=2'b01, S2=2'b10, S3=2'b11; //State definition
reg [1:0]pre_state, next_state; //State register
// Synchronous State-Transition always@(posedge Clock) block
always@(posedge clk) begin
if (rst) begin
pre_state <= S0;
end
else
pre_state <= next_state;
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

end
// Conditional State Transition always@(pre_state or X) block
always@(pre_state or X) begin
case(pre_state)
S0: if (X) next_state <= S1;
else next_state <= S0;
S1: if (!X) next_state <= S2;
else next_state <= S0;
S2: if (!X) next_state <= S3;
else next_state <= S2;
S3: if (!X) next_state <= S0;
else next_state <= S3;
endcase;
end
// Output Logic depending on the state
always@(*) begin
case (pre_state)
S0: Y <= 2'b00;
S1: Y <= 2'b10;
S2: Y <= 2'b11;
S3: Y <= 2'b01;
endcase;
end
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Compile the above program. Then, students simulate the output waveform in all cases
of the input. Capture the output waveform.
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

B. LAB MANUAL

I. OBJECTIVES

- Understand how to use FPGA kits, programming software.

- Understand how to design a basic combinational and sequential logic circuits on
FPGA.
- Understand the process of describing hardware on FPGAs.

II. PREPARATION:

- To prepare well for the test, students MUST read Appendix 1 first and complete the
steps of Sample lab in Appendix 2, and submit it with Prelab 4 before entering class.
- Students must complete and submit Prelab 4 before entering class.
- Students read the appendix and the Kit DE2 Manual to understand how to use the DE2
Kit, wiring, peripherals, and how to use Quartus software to simulate and synthesize
circuits. Students refer to the documentation to understand how to write hardware
designs in the SystemVerilog language.

III. LAB INSTRUCTIONS

EXPERIMENT 1
Objective: Design the combinational circuit that calculates the absolute value of a 4-bit
number (the input is A, the output is S).
 Students draw the logic gate diagram of the circuit to be designed
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:
o Pins A[3:0] assigned to SW[3:0]
o Pins S[3:0] assigned to LEDR[3:0].

 Students compile the above program. Then, students simulate the output waveform in
all cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit)
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students view the results (Tool  Netlist Viewer  RTL Viewer) of the circuit.

 Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)
Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

EXPERIMENT 2
Objective: Design the combinational circuit that implements the ALU
The ALU calculates two 4-bit numbers (the two inputs are A and B respectively, the output is
S, the flags are Ci and Co) through the 2-bit input: Sel.

- If Sel=00: S=A+B

- If Sel=01: S=A-B

- If Sel=10: S=A AND B

- If Sel=11: S=A OR B

 Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:

o Pins A[3:0] assigned to SW[3:0]

o Pins B[3:0] assigned to SW[7:4]

o Pins Ci assigned to SW[8]

o Pins S[3:0] assigned to LEDR[3:0]

o Pins Co assigned to LEDR[4]

 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students compile the above program. Then, students simulate the output waveform in
all cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit).

 Students view the results (Tool  Netlist Viewer  RTL Viewer) of the circuit..
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)

EXPERIMENT 3
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

Objective: Design a 3-bit down counter circuit.

The count value changes every 1s. The output is connected to a common anode 7-segment
LED. In addition, the counter has an RST pin (active high) used to reset the counter state to 0.

Hint:

- The clock signal is generated from the frequency divider from 50MHz to 1Hz.

- Students use the 7-segment LED decoder module in PRELAB, connecting the output of
the counter to the input of the module.

 Students draw the logic gate diagram of the circuit to be designed

 Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:

o 7-segment LED ouput assigned to HEX[0]

 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

o Pins RST assigned to SW[0]

 Students compile the above program. Then, students simulate the output waveform in
all cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit)
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students view the results (Tool  Netlist Viewer  RTL Viewer) of the circuit.

 Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

EXPERIMENT 4
Objective: Design a 4-bit up counter circuit from 5 to 14.
The count value changes every 1s. The output is connected to a common anode 7-segment
LED. In addition, the counter has an RST pin (active high) used to reset the counter state to 0.

Hint:

- The clock signal is generated from the frequency divider from 50MHz to 1Hz.

- Students use the 7-segment LED decoder module in PRELAB, connecting the output
of the counter to the input of the module.

- Students need to write a 4-bit binary to BCD converter module.

 Students draw the logic gate diagram of the circuit to be designed

 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:

o Two 7-segment LED outputs assigned to HEX [1], HEX[0]

o Pins RST assigned to SW[0]

 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students compile the above program. Then, students simulate the output waveform in
all cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit)

 Students view the results (Tool  Netlist Viewer  RTL Viewer) of the circuit.
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)

EXPERIMENT 5
Objective: Design a sequential circuit has 1 input (X) and 1 output (Z). Output Z = 1 if the
total number of bit 1 received is divisible by 3 (0, 3, 6, 9, … are numbers divisible by 3 ) and
the total number of 0 bits received is an even number (greater than 0).
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

Note:

- Students design a sequential circuit according to Mealy or Moore type state

machines.

- The clock signal is generated from the frequency divider from 50MHz to 1Hz.

 Students draw the logic gate diagram of the circuit to be designed

 Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:

o Input X assigned SW[0]

o Output Z assigned to LEDR[0]

 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students compile the above program. Then, students simulate the output waveform in
all cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit)
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students view the results (Tool  Netlist Viewer  RTL Viewer) of the circuit.

 Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

EXPERIMENT 6
Objective: Describe FSM using SystemVerilog.
An automatic pet food and water supply system with 2 inputs are 2 push buttons RED, BLUE;
and 2 outputs are FOOD, WATER signals to activate the food and water

 RED button (R signal, pressing R=1, otherwise R=0): when the animal needs to
eat, press the RED button 3 times. Then signal F (FOOD) = 1 to activate the food
supply machine.
 BLUE button (signal B; pressing B=1, otherwise B=0): when the animal wants to
drink, press the BLUE button 2 times. Then signal W (WATER) = 1 to activate the
water supply machine.

Note:

- Students design a sequential circuit according to Mealy or Moore type state

machines.

- The clock signal is generated from the frequency divider from 50MHz to 1Hz

- When the signal F or W is equal to 1, if any button is pressed, the system will return
to the reset state.

- At each time, there is only 1 button pressed.

 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

- Buttons need to be operated consecutively, if there is 1 button in the wrong sequence,

the state machine will return to the original state. (e.g. when the buttons are pressed in
sequence (RED, RED, BLUE), the state machine returns to the reset state).

 Students draw block diagram (state machines)

 Students write the SystemVerilog code to perform the function's circuit as instructed
from Prelab with the pin assignment as follows:

o Input RED and BLUE assigned SW[1:0]

o Output FOOD and WATER assigned to LEDR[1:0]

 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students compile the above program. Then, students simulate the output waveform in
all cases of the input. Capture the output waveform.
(Insert a photo demonstrating that the student has simulated the circuit)
 Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.

 Students view the results (Tool  Netlist Viewer  RTL Viewer) of the circuit.

 Students download the code to the DE2 Kit.

(Insert a photo proving that the student has uploaded the Kit)
Lab 4: Implementation of combinational circuit and sequential circuit on FPGA.
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

LAB 4: CIRCUIT IMPLEMENTATION

ON BREADBOARD AND
COMMUNICATION WITH FPGA
Student’s name: Class:
Student ID: Date:

A. PRELAB
Part I: Creating a 1 Hz Clock for the DE 2 Kit
Kit DE2 CLOCK_50 pin is connected to a source of 50 MHz clock on the PCB. If connect the
design to this pin, you get this clock speed (Oscillate 50 million times in 1 second). In more common
real world applications , sometimes we need changes at 1 time per second (Clock 1 Hz).
To generate 1 Hz Clock on Kit DE2, as studied in LAB 4, you need to load a register with a value
of 50 million, then decrease the register value each clock. Use a flag to compare the register value
with zero, we now know when the register oscillated for 50 million times (or 1 second in this
scenario). The flag is our 1 Hz clock.
Requirement: Write SystemVerilog code for 1 Hz Clock Generator module which blinks LEDR0
on Kit De2 every 1 second.
Example System Verilog code for this module :
// Ho Chi Minh University of Technology

// Faculty of Electrical & Electronics Engineering

// Department of Electronics

// EE1016 - EE1010 : Ky Thuat So

//

// Lab 5 : Thiet ke he thong den giao thong

// Thuc hien giao tiep DE2 - GPIO - Breadboard - ICs/LEDs/LCDs

// Module change 50 MHz to 1 sec

//

///////////////////////////////////////////////
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

module secgen (

input clk,

input rst,

output sec

);

///////////////////////////////////////////////

parameter CLKCONST = 50000000; //clock 50 MHz

///////////////////////////////////////////////

reg [25:0] temp; // 26-bit 67M

wire tmpzr;

assign tmpzr = temp == 0;

always_ff @(posedge clk) begin

if (rst)

temp <= CLKCONST; //50M

else if (tmpzr)

temp <= CLKCONST;

else

temp <= temp - 1;

 Lab 5: Circuit implementation on breadboard and communication with FPGA.

end

assign sec = tmpzr;

endmodule

Part II: State machine for Traffic lights control manual mode
Draw the state machine for Traffic lights control manual mode. Read the requirement for
Experiment 1 Lab 5.

Requirements: Students should refer to the topic and draw the state machine for the main
controller of this system:

Part III: State machine for Traffic lights control Autonomous mode
Draw the state machine for Traffic lights control Autonomous mode. Read the requirement for
Experiment 2 Lab 5.
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Requirements: Students should refer to the topic and draw the state machine for the main
controller of this system:

Part IV: GPIO Components of the DE2 Kit

Students refer to the DE2 Terrasic kit datasheet and learn the order of GPIO_0 and GPIO_1 pins,
how to install LEDs to GPIO_0 of the DE2 kit.

Requirements: Students draw how to connect the circuit with GPIO_0 of Kit DE2 to LED (note
the aesthetics) and resistors

Part V: 7 segment LED 5161BS

Students refer to datasheet IC led 7 segment 5161BS (For Common Anode LED)
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Requirements: Students draw how to connect the GPIO_0 of Kit DE2 to 7-segment LED (note the
aesthetics)

Part VI: 74LS47 7-segment led decoding IC

Students refer to datasheet IC decoding 7-segment led 74LS47 (For LED Common Anode)

Requirements: Students draw how to install the circuit connecting GPIO_0 of Kit DE2 to IC 74LS47
to 7-segment LED (note the aesthetics)
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Part VII: 16x2 . LCD interface

Students need to refer to the 16x2 LCD datasheet, most of which use the HD44780 control chip with
the following pinout:

Figure 5.13 LCD 16 x 2

LCD requires students to send Hex codes in the form of commands, which include the HEX
code to start and the HEX Code to write / erase content.
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Figure 5.14 Commands for 16x2 LCD module

The 16×2 LCD module has a preset command instruction set. Each command will make the
module perform a specific task. Commonly used commands and their functions are given in the
table below

Command Function
0F LCD is on, pointer is on, pointer is
blinking on
01 Clear full screen
02 Return to home screen
04 Cursor reduction
06 Increment pointer
0E Screen on, cursor blinking off
80 Returns the cursor to the first
position of row 1
Lab 5: Circuit implementation on breadboard and communication with FPGA.

C0 Returns the cursor to the first

position of row 2
38 Using 2 rows and a 5x7 matrix
83 Row pointer 1 position 3
3C Enable second line
08 Turn off the display and pointer
C1 Jump to line 2 position 1
OC Turn on the display, turn off the
cursor
C2 Jump to row 2, position 2
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Table 5.15 Command instruction set of LCD 16 x 2 module

Initialize LCD
The steps that must be taken to initialize the LCD are given below and these steps are
common for most applications.
B1: Send 38H to 8-bit data line for initialization
B2: Send 0FH to turn on the LCD, the cursor is ON and the cursor is blinking ON.
B3: Send 06H to increase the cursor position.
B4: Send 01H to clear the screen and return the cursor.
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Input data to LCD

The steps to send data to the LCD module are given below. The LCD module has RS,
R/W, and E pins. It is the logic state of these pins that causes the module to determine
whether a given data input is a command or data to be displayed.
Set R/W low.
Set RS=0 if data byte is command and make RS=1 if data byte is data to be displayed.
Put the data byte on the data register.
Pulse E from high to low.
Repeat the above steps to send other data.
Alphanumeric symbols can refer to the ASCII code table

Requirements: Students learn the meaning of LCD pins. Students write SystemVerilog
hardware code with the function of loading the LCD with the words "Chuan bi TN5"
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Refer to the example LCD module:

///////////////////////////////////////////////

// Ho Chi Minh University of Technology

// Faculty of Electrical & Electronics Engineering

// Department of Electronics

// EE1016 - EE1010 : Ky Thuat So

//

// Lab 5 : Thiet ke he thong den giao thong

// Thuc hien giao tiep DE2 - GPIO - Breadboard - ICs/LEDs/LCDs

// module simple lcds

//

///////////////////////////////////////////////

module lcddisp_ex(

input clk,

output reg lcd_e, lcd_rs,

output reg [7:0] data

);

//////////////////////////////////////////////////////

//preset lcd write

integer j = 1;

reg [7:0] Datas [1:15];

always @(posedge clk) begin

Datas[1] = 8'h38; //-- control instruction : configure - 2 lines, 5x7

matrix --
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Datas[2] = 8'h0C; //-- control instruction : Display on, cursor off --

Datas[3] = 8'h06; //-- control instruction : Increment cursor : shift

cursor to right --

Datas[4] = 8'h01; //-- control instruction : clear display screen --

Datas[5] = 8'h80; //-- control instruction : force cursor to begin at

first line --

Datas[6] = 8'h54; //-- T --

Datas[7] = 8'h68; //-- h --

Datas[8] = 8'h69; //-- i --

Datas[9] = 8'h20; //-- --

Datas[10] = 8'h4E; //-- N --

Datas[11] = 8'h67; //-- g --

Datas[12] = 8'h68; //-- h --

Datas[13] = 8'h69; //-- i --

Datas[14] = 8'h65; //-- e --

Datas[15] = 8'h6D; //-- m --

end

///////////////////////////////////////////////////////////

integer i = 0; //

always @(posedge clk) begin

//-- Delay for writing data

 Lab 5: Circuit implementation on breadboard and communication with FPGA.

if (i <= 1000000) begin

i = i + 1; lcd_e = 1;

data = Datas[j];

end

else if (i > 1000000 & i < 2000000) begin

i = i + 1; lcd_e = 0;

end

else if (i == 2000000) begin

j = j + 1; i = 0;

end

else i = 0;

//-- LCD_RS signal should be set to 0 for writing commands and to 1 for
writing data

if (j <= 5 )

lcd_rs = 0;

else if (j > 5 & j< 18)

lcd_rs = 1;

else if (j == 18)

lcd_rs = 0;

else if (j > 27) begin

lcd_rs = 1;

j = 5;
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

end

else

lcd_rs = 1;

//else if (j > 27) begin

// lcd_rs = 1;

/// j = 5;

//end

end

endmodule
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Student write their own LCD module accroding to Experiment 3 Lab 5.

In addition, with the Contrast Voltage pin, students need to install a rheostat to adjust. Students
redraw the circuit diagram connecting GPIO to LCD.
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Part VIII: Example Circuit

Example circuit of the experiment result, student could take these pictures as an advice.
Lab 5: Circuit implementation on breadboard and communication with FPGA.

Figure 5.15 Image wallet example 1

Lab 5: Circuit implementation on breadboard and communication with FPGA.
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Figure 5.16 Image wallet example 2

B. LAB MANUAL
I. OBJECTIVES:
- Apply theory to design in practice.
- Combines knowledge of hardware description languages and digital circuits.
II. LAB PREPARATION:

- Complete all tests 1, 2, 3, 4.

- Complete Pre-Lab 5
III. LAB INSTRUCTION:
EXPERIMENT 1

Target: Design a manually controlled traffic light system

Request: Design a traffic light system for an intersection with the following parameters:

Input (input):

- Buttons include:

o 1 RESET button. (Use Key0 button on Kit De 2)

o 1 Switch to change the direction the vehicle is moved (Use SW1 button on
Kit De 2)

Output (output):

- Students use Expansion Header output on Kit De 2 (using GPIO_0) to connect to

the following components:

- Two luminaires (The other two facing each other are optional) including:
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

o 1 Led 7 segments to count seconds

o 1 Red Led

o 1 Green Led

o 1 Yellow Led

Operation Description:

- After RESET, the traffic light system automatically operates in the mode

- In control mode:

o The direction the vehicle is allowed to move will light up in green

o The other direction is red light

o All counter lights show 9 seconds and do not change value

- When the vehicle direction changes (in control mode)

o The direction the vehicle was previously moved changes from green to
yellow, the countdown light shows 3 seconds and counts down to 0 and then
turns to red.

o The other direction keeps the red light until the previous direction turns red,
the countdown time from 3 seconds counts down to 0.

o At this time, the direction is changed to green light. All counter lights show
9 seconds and do not change value.

Test:
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Students use the De 2 kit with the SystemVerilog hardware description language for the above
hardware description circuit, connecting from GPIO 0 to the breadboard to represent the light
system. The system of buttons, switches used on the kit as required for the topic.

o Students redraw the block diagram of hardware design

o Students redraw the assembled circuit principle diagram (From GPIO to

components on Breadboard)
Lab 5: Circuit implementation on breadboard and communication with FPGA.

o Students redraw the FSM of the manual control system

Lab 5: Circuit implementation on breadboard and communication with FPGA.

o Rewrite the SystemVerilog wrapper (top_level) of the design

Lab 5: Circuit implementation on breadboard and communication with FPGA.

o Students present the results of their activities when program to the DE 2

Kit (image)
Lab 5: Circuit implementation on breadboard and communication with FPGA.
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

EXPERIMENT 2

Target: Design automatic traffic light system, two modes

Request:
Design a traffic light system for an intersection with the following parameters:
Input (input):
- Buttons include:
o 1 RESET button. (Use Key0 button on Kit De 2)
o 1 Switch between auto and control mode (Use SW0 on Kit De 2)
o 1 Switch to change the direction the vehicle is moved (Use SW1 button
on Kit De 2)
Output (output):
- Replace connection between GPIO_0 Kit De 2 to 7-segment Led to Connect from
GPIO_0 Kit De 2 to IC 74LS47 to 7-segment Led.
Operation Description:
- After RESET, the traffic light system automatically operates according to the
mode set to SW0.
- Control mode as experiment 1
- In automatic mode:
o In each direction, the car moves in turn
o The direction to be moved has a green light within 5 seconds count down
to 0, change to yellow light and from 2 seconds count down 0. At this
time, the direction turns to red light, countdown time 9 counts down to 0.
o The other direction displays a red light and the countdown time 9 counts
down to 0 (The other direction coincides with the red light for 1 second)
and turns to green within 5 seconds of counting down to 0, turning to
yellow and from 2 seconds count down to 0. And so on.
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

Note:
The time in the request is for reference only, students use and apply the counting method
so that the system works properly.
Test:
Students use the De 2 kit with the SystemVerilog hardware description language for the
above hardware description circuit, connecting from GPIO 0 to the breadboard to represent
the light system. The system of buttons, switches used on the kit as required for the topic.
o Students redraw the block diagram of hardware design

o Students redraw the assembled circuit principle diagram (From GPIO to

components on Breadboard)
Lab 5: Circuit implementation on breadboard and communication with FPGA.

o Students redraw the FSM of the automatic control system

o Rewrite the SystemVerilog wrapper (top_level) of the design

Lab 5: Circuit implementation on breadboard and communication with FPGA.

o Students present the results of their activities when program to the DE 2

Kit (image)
Lab 5: Circuit implementation on breadboard and communication with FPGA.
 Lab 5: Circuit implementation on breadboard and communication with FPGA.

EXPERIMENT 3

Target: Design an automatic, two-mode traffic light system as above using IC 74LS47
with an LCD advertising board placed at the corner of the intersection.
Request:
- Students connect the 16 x 2 LCD module using GPIO_1 to the breadboard, display
the ad "Thi Nghiem 5 KTS" in row 1, "BM Dien Tu DHBK" in row 2.

Test:
Students use the De 2 kit with the SystemVerilog hardware description language for the
above hardware description circuit, connecting from GPIO 0 to the breadboard to represent
the light system. The system of buttons, switches used on the kit as required for the topic.
o Students redraw the block diagram of hardware design
Lab 5: Circuit implementation on breadboard and communication with FPGA.

o Students redraw the assembled circuit principle diagram (From GPIO to

components on Breadboard)

o Rewrite the SystemVerilog wrapper (top_level) of the design

Lab 5: Circuit implementation on breadboard and communication with FPGA.

o How is the description hardware LCD communication with

SystemVerilog done? Rewrite the SystemVerilog code for LCD
communication.

o Students present the results of their activities when program to the DE 2

Kit (image)
Lab 5: Circuit implementation on breadboard and communication with FPGA.
 Appendix 1: Quartus and Ubuntu Installation on Windows.

APPENDIX 1: QUARTUS AND UBUNTU

INSTALLATION ON WINDOWS

A. UBUNTU INSTALLATION ON WINDOWS:

I. Download and install Xming and WSL2:

Download and install Xming:

Xming is X Server on Windows operating system, used to run Linux applications on
Windows.
Xming download link: https://sourceforge.net/projects/xming/
Download WSL2 Kernel: (only do this step if the computer uses Windows 11 operating
system)
WSL2 Kernel is a tool that allows users to run Linux in Windows.
Link download:
https://wslstorestorage.blob.core.windows.net/wslblob/wsl_update_x64.msi

II. Install Ubuntu on Windows:

Step 1: Turn on Windows Subsystem for Linux

 Appendix 1: Quartus and Ubuntu Installation on Windows.

- Open Control Panel Programs and

Features “Turn Windows features
on or off”.
- Select “Windows Subsystem for
Linux, Virtual Machine Platform”
- For Windows 11, install WSL2
Kernel.
- Restart Windows.

Figure Appendix 1.1 “Turn Windows features on or

off”

Step 2: Open Windows Store Find and Install Ubuntu 22.04.1 LTS

Figure Appendix 1.2 Windows Store

Figure Appendix 1.3 Starting Ubuntu

- Boot Ubuntu 22.04.1 LTS

- Set Username and Password. Note: the password will NOT be displayed on the
screen.
 Appendix 1: Quartus and Ubuntu Installation on Windows.

Figure Appendix 1.4 Setting UNIX username and password

- Determine the working directory of Ubuntu in Windows:enter command cd ~;

explorer.exe . .In the home directory , find a folder named username set; Right
click on this folder, select Pin to Quick Access . All files and folders created in
Ubuntu are stored in the username folder.

Bước 3: Download the following file (install203.tar) and save it in a folder named username
set: https://drive.google.com/file/d/1F2aKS83WR8D6xWmu1k4xSWetmcbcmeue/view?
usp=sharing

Figure Appendix 1.5 Position of “install203” folder

Test: After completing the above steps, when booting Ubuntu  type “ ls ” (list the files in
the directory)  the install203.tar file appears.

Install the install203.tar file :

Open Ubuntu 22.04.1 LTS and run the following command:

 Appendix 1: Quartus and Ubuntu Installation on Windows.

$ sudo apt -y install make

$ chmod 755 install203.tar
$ tar xvf install203.tar
$ cd install203/
$ make

III. Some basic commands in Linux

In the Ubuntu terminal, in front of the $ Displays the name of the current directory.

Figure Appendix 1.6 Terminal Ubuntu

Some basic commands:

ls List (list) files in the directory

tree Similar to ls as in a directory tree

mkdir abc Make directory (create directory) name “ abc ”

cd abc Change directory (go to directory) abc

cd .. Change directory to previous directory

micro file1.sv Tạo/soạn thảo file tên “file1.sv” bằng micro

 Appendix 1: Quartus and Ubuntu Installation on Windows.

cp file1.sv file2.sv Copy file1.sv to the current directory and name it file2.sv

cp file1.sv abc/ Copy file1.sv to folder abc

cp file1.sv abc/file3.sv Copy file1.sv to abc folder and name it file3.sv

mv file1.sv file0.sv Move file1.sv to file0.sv (rename)

mv file0.sv abc/ Move file0.sv to folder abc

mv abc/file3.sv . Move file3.sv in directory abc to current directory

cp -r abc/ xyz/ Copy directory abc và đặt tên là xyz

pwd Indicate current directory path

rm file1.sv Remove (delete) file1.sv

rm file2.sv xyz/file1.sv Remove (delete) file2.sv and file1.sv in folder xyz

rm -rf xyz Remove directory xyz

 Appendix 1: Quartus and Ubuntu Installation on Windows.

You should type these commands in the above order, each time you enter, remember to enter
ls or tree , and pwd to understand how it works.
Micro : Alt+G for keyboard shortcuts, for example “^S Save” means to Save, press Ctrl+S..
 Appendix 1: Quartus and Ubuntu Installation on Windows.

B. INSTALL QUARTUS 13.0SP1

Step 1: Download and install Quartus 13.0sp1.
Download link: https://www.intel.com/content/www/us/en/software-kit/711791/intel-quartus-
ii-web-edition-design-software-version-13-0sp1-for-windows.html
Unzip the installation file. Right click the Setup file  select Run as Administrator .
Choose the installation address as C:\altera .
Note: When installing Quartus, select components : select Cyclone devices to communicate
with DE2 and DE10 kit.
Step 2: Install the communication driver with the FPGA kit
- USB connection between the FPGA kit and the computer. Power supply to the
FPGA kit.
- Open Control Panel Device Manager Other devices, right click USB-Blaster
select Update Driver Browse for drivers on your computer select the path to
the folder containing the USB – Blaster.
 Appendix 1: Quartus and Ubuntu Installation on Windows.

Figure Appendix 1.7 Installing the USB driver – Blaster

 Appendix 2: Sample lab.

APPENDIX 2: DIGITAL CIRCUIT DESIGN FLOW

USING SYSTEMVERILOG

A. DESIGN FLOW

Figure Appendix 2.8 Digital design flow using SystemVerilog

1. RTL Coding: Algorithm design, FSM,... to solve the set requirements, the design
language here is SystemVerilog HDL.
2. Lint Check: Checks for syntax/syntax errors or coding practices that may cause errors
or bugs. Lint needs to be run after writing the code. Note, Lint Check is a static code
checking process - ie the code will not be run, so the correctness and operation of the
code will not be checked.
→ If Lint Check gives an error, need to read the error to know what is the error, in
which line → Correct the code
3. Verification: Check the operation of the code - based on the design requirements, for
this input, the code is expected to give the output. This is the process of checking the
correctness of the code.
 Appendix 2: Sample lab.

→ If Verification has an error, need to read the code to know what is the error, in
which line → Correct the code → Lint Check
4. Implementation: The design after Verification is completed and meets the
requirements, it will be uploaded to the KIT (DE2 or DE10 or other FPGA KIT).

B. COMBINATIONAL LOGIC MODELING

I. Problem:

Design the following combinational circuit

Inputs:
data0, data1 : 3 bit
sel : 2 bit
Outputs:
result : 3 bit

Operation:
 Appendix 2: Sample lab.

sel result
0 0 0
0 1 data0 & data1
1 0 data0 | data1
1 1 data0 ^ data1
II. Design:
 Appendix 2: Sample lab.

Create Project
At ~ ( cd ~ if necessary), create directory projects , in it create directory lab0 , in
lab0 get the template on GitHub to use, name it ex01 .

gettemplate ex01
Type ls to see the files and directories in the current directory, or tree if you want to see the
directory tree.
 Appendix 2: Sample lab.

$ tree
.
└── ex01
├── filelist
├── makefile
├── quartus
│ ├── de10_pin_assign.qsf
│ └── de2_pin_assign.qsf
└── test
├── driver.cpp
└── tb_top.cpp

3 directories, 6 files
A project should be neatly organized as follows:
• Go to ex01 : (cd ex01 )and create directory src : mkdir src
• All design .sv files need to be placed in the src directory .
• Edit: create file or edit file (if file already exists) type: micro <filename>
• Design files need to be declared in the filelist.
 Appendix 2: Sample lab.

Figure Appendix 2.9 Create project

Code
 Appendix 2: Sample lab.

Create a design file named design_1.sv and place it in src.

micro src/design_1.sv hoặc cd src rồi micro design_1.sv

src/design_1.sv

1 module design_1 (
2 // input
3 input logic [2:0] data0_i,
4 input logic [2:0] data1_i,
5 input logic [1:0] sel_i,
6
7 // output
8 output logic [2:0] result_o
9 );
10
11 // local declaration
12 logic [2:0] and_tmp; // temporary for and result
13 logic [1:0] or_tmp; // temporary for or result
14 logic [2:0] xor_tmp; // temporary for xor result
15
16 assign and_tmp = data0_i & data1_i;
17 assign or_tmp = data0_i | data1_i;
18 assign xor_tmp = data0_i ~^ data1_i;
19
20 always_comb begin : proc_mux
21 case (sel_i)
22 2'b00: result_o = '0;
23 2'b01: result_o = and_tnp;
24 2'b11: result_o = or_tmp;
25 2'b11: result_o = xor_tmp;
26 endcase
27 end
28
29 endmodule : design_1

At ex01, open and add the filename to the filelist . Enter micro filelist or if in src
then go to ex01 by typing cd ..
 Appendix 2: Sample lab.

filelist

1 src/design_1.sv

Lint Check
Step 1: Run Lint Check to check for errors, type make lint.

$ make lint
------------------> LINT CHECK <------------------
%Error: src/design_1.sv:23:25: Can't find definition of variable: 'and_tnp'
: ... Suggested alternative: 'and_tmp'
23 | 2'b01: result_o = and_tnp;
| ^~~~~~~
%Error: Exiting due to 1 error(s)
make: *** [makefile:50: lint] Error 1
$
Bước 2: Analysis and debugging

After running Lint, the above code has a bug on line 23, and_tnp could not be
found because it was mistyped here and declared as and_tmp . Correct line 23, repeat
Step 1 , make lint.

$ make lint
------------------> LINT CHECK <------------------
%Warning-WIDTH: src/design_1.sv:17:18: Operator ASSIGNW expects 2 bits on the
Assign RHS, but Assign RHS's OR generates 3 bits.
: ... In instance design_1
17 | assign or_tmp = data0_i | data1_i;
| ^
... For warning description see https://verilator.org/warn/WIDTH?v=4.225
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable
this message.
%Warning-WIDTH: src/design_1.sv:24:23: Operator ASSIGN expects 3 bits on the
Assign RHS, but Assign RHS's VARREF 'or_tmp' generates 2 bits.
: ... In instance design_1
24 | 2'b11: result_o = or_tmp;
| ^
%Warning-CASEOVERLAP: src/design_1.sv:25:7: Case values overlap (example
pattern 0x3)
25 | 2'b11: result_o = xor_tmp;
 Appendix 2: Sample lab.

| ^~~~~
%Warning-CASEINCOMPLETE: src/design_1.sv:21:5: Case values incompletely
covered (example pattern 0x2)
21 | case (sel_i)
| ^~~~
%Error: Exiting due to 4 warning(s)
make: *** [makefile:50: lint] Error 1
$
 Appendix 2: Sample lab.

Analysis and debugging:

1. The first error, %Warning-WIDTH: src/design_1.sv:17 → error about bit

length mismatch, further reading we see that or_tmp is 2 bits but the RHS (Right
Hand Side - right) result is 3 bits, this is because the declaration of or_tmp is 2 bits (
[1:0]). → Fix or_tmp declaration line (line 12) to 3 bits: [2:0]

2. The next error on line 24 is similar.

3. Error on line 25, %Warning-CASEOVERLAP: src/design_1.sv:25 → error

about duplicate value compare case. Reviewing the code, there are 2 cases 2'b11.

4. Error on line 21, %Warning-CASEINCOMPLETE: src/design_1.sv:21 →

error about missing case comparison. This error is caused by
the missing 2'b10 instance . So error lines 21 and 25 are related, fix line 24
to 2'b10.

Bước 3: Sau khi debug, lặp lại Bước 1, make lint.

 Appendix 2: Sample lab.

$ make lint
------------------> LINT CHECK <------------------
$
No errors, the next step is Verification.

Verification
Set Up: To verify the above design, it is necessary to create a driver to drive the input and set
the condition in the output corresponding to the specific input.
Input values, aka test transactions, are generated randomly, so we don't know exactly what
inputs are being fed into and pre-compute the outputs for comparison. In addition, manual
calculation that way, for large design with thousands of test samples, will be difficult for the
designer, so have to check the output automatically, here using assertions to check.
Bước 1: Create file top.sv in directory ex01 , call file design_1.sv.

1. Declare input and output as in design_1 , add clock. Each clock pulse is a test
transaction.
top.sv

1 module top (
2 // input
3 input logic clk_i,
4 input logic [2:0] data0_i,
5 input logic [2:0] data1_i,
6 input logic [1:0] sel_i ,
7 // output
8 output logic [2:0] result_o
9 );
10

2. Call the design_1 module. Note, after the dot is the port name of the design, in
the brackets is the signal/data name connected to that port.
top.sv

11 design_1 dut (
12 .data0_i (data0_i ),
13 .data1_i (data1_i ),
14 .sel_i (sel_i ),
15 .result_o(result_o)
16 );
17
 Appendix 2: Sample lab.

3. Set the condition for the output. Use the assert keyword to constrain the output
like the code below as required by the design, for example, if sel = 2'b11 , then the
result must be equal to xor two data, otherwise the simulation will fail because the
design is not satisfactory. assertion case. Here there is a total of 4 conditions with 4
sel values.
top.sv

18 always @(posedge clk_i) begin : proc_assertions

19 if (sel_i == 2'b00)
20 assert (result_o == '0);
21 if (sel_i == 2'b01)
22 assert (result_o == (data0_i & data1_i));
23 if (sel_i == 2'b10)
24 assert (result_o == (data0_i | data1_i));
25 if (sel_i == 2'b11)
26 assert (result_o == (data0_i ^ data1_i));
27 end
28
29 endmodule : top

Step 2: Create driver to drive input randomly (easier to detect bugs than preset input and
check output, because output output only needs to be constrained to check correctness)

1. Create file driver.cpp in test : micro test/driver.cpp or cd test then

micro driver.cpp

test/driver.cpp

1 #define MAX_SIM 20
2
3 void set_random(Vtop *dut, vluint64_t sim_unit) {
4 dut->data0_i = rand()%8;
5 dut->data1_i = rand()%8;
6 dut->sel_i = rand()%4;
7 }
 Appendix 2: Sample lab.

2. Note 1: the input includes data0_i, data1_i, and sel_i, but needing to be in the
form dut->data0_i, … clk_i is always automatically given, so top.sv
should always have the logical input clk_i
3. Note 2: this is a C++ file, to generate random, use the function rand() , divide the
remainder by 4 because sel_i only has 2 bits, and data has 3 bits, so divide and divide
by 8. If you want to keep the value fixed, for example data0_i is 3'b101 , just
assign dut->data0_i = 0b101 (C++ assignment).
4. Note 3: MAX_SIM is the number of random samples generated.
Simulating:
Step 1: Run Simulating to check for errors, enter make sim.

$ make sim
-------------------> BUILD <----------------------
...
...
...
-----------------> SIMULATING <-------------------
[0] %Error: top.sv:26: Assertion failed in TOP.top.proc_assertions: 'assert' failed.
%Error: top.sv:26: Verilog $stop
Aborting...
make: *** [makefile:61: sim] Aborted (core dumped)
$
Read the error and see Assertion failed on line 26 of top.sv , check line 26 and see
that this assertion binds the output of sel = 2'b11 , which proves design_1.sv is
false when sel = 2'b11.

Step 2 : Open waveform to observe, enter make wave . Select top → Select all signals in
the lower cell → Select Insert . Output is 001 instead of 110.
 Appendix 2: Sample lab.

Figure Appendix 2.10 Simulation results during verification process

It is possible to open the menu and save the selection of this signal: File → Write Save
File

Step 3: Check the design_1.sv code again and observe:

src/design_1.sv

1 assign xor_tmp = data0_i ~^ data1_i;

8
Bug on line 18 because the math was supposed to be ^ but was ~^ . Edit code.
Step 4 : Repeat Step 1 . Run sim: make sim.

$ make sim
-------------------> BUILD <----------------------
...
...
...
-----------------> SIMULATING <-------------------
$
No error. Repeat Step 2 , observing the waveform: make wave.
 Appendix 2: Sample lab.

$ make wave
-----------------> WAVEFORMS <--------------------

Figure Appendix 2.11 Simulation results after verification

Step 5: Done.

Implementation
Set Up
Step 1: Create wrapper.sv file.
The wrapper file will call design_1 like top.sv , but the input and output will be from
the following file:
https://www.terasic.com.tw/cgi-bin/page/archive.pl?CategoryNo=53&No=30&PartNo=4
(download file DE2_UserManual_1.6 or DE2 Pin Table )
input has data0_i , data1_i , and sel_i , uses switches as input, pin name as shown in
table 4.1 in above file. There are 8 bits in total, assign data0_i as SW 2, SW 1, and SW 0,
data1_i as SW 5, SW 4, and SW 3, and sel_i as SW 7 and SW 6. So input will be
declared as line 3 and assigned as 3 lines 9, 10, 11.
Output has only result_o and has 3 bits, used as output, table 4.3 in the file above mentions
led. Select red LEDR 2, LEDR 1, and LEDR 0. So the output will be declared as line 5 and
assigned as line 12.
 Appendix 2: Sample lab.

quartus/wrapper.sv

1 module wrapper (
2 // input
3 input logic [7:0] SW,
4 // output
5 output logic [2:0] LEDR
6 );
7
8 design_1 dut (
9 .data0_i (SW[2:0] ),
10 .data1_i (SW[5:3] ),
11 .sel_i (SW[7:6] ),
12 .result_o(LEDR[2:0])
13 );
14
15 endmodule : wrapper

Step 2 : Create a project in Quartus.

1. Open Quartus.
2. Choose File → New Project Wizard.
 Appendix 2: Sample lab.

a. To directory quartus in ex01.

Figure Appendix 2.12 Project directory

 Appendix 2: Sample lab.

b. Name the project wrapper . Since the actual project is the ex01
directory , it needs to be named exactly like the file name of the file,
wrapper.sv.

Figure Appendix 2.13 Directory, Name, Top-Level Entity settings.

c. Next to continue.
3. Select … to get the source code
a. Point to directory wrapper.sv which is quartus, select all files →
Open → Add .
b. Point to the directory containing the source code as src, select all files →
Open → Add.
c. Make sure the Type column is SystemVerilog HDL File.
d. Next to continue.
4. For DE2
a. Device family selects Cyclone II .
b. Available devices select EP2C35F672C6 .
 Appendix 2: Sample lab.

c. Finish to complete.

Figure Appendix 2.14 Family and device settings.

Step 3: Import pin assignment of DE2.

1. Choose AssignmentsImport Assignments .
2. Select … , point to quartus and select de2_pin_assign.qsfOpenOK.
Step 4: Compilation
Ctrl+L or Processing → Start Compilation
 Appendix 2: Sample lab.

Figure Appendix 2.15 Compilation results

Check the message window has no errors → proceed to upload to KIT.

Programmers

1. Connect the DE2 using the USB cord at the Blaster port
 Appendix 2: Sample lab.

Figure Appendix 2.16 DE2 connection

2. Choose Tools → Programmers

Figure Appendix 2.17 Programmer

3. Check connected: USB-Blaster X, if No Hardware is displayed, click Hardware

Setup and select USB-Blaster X → Close.
 Appendix 2: Sample lab.

4. Select Start to start loading. Check in the box Progress is 100% (successful), ie
successfully loaded.

Figure Appendix 2.18 Nạp kit thành công

C. SEQUENTIAL LOGIC/FSM MODELING

 Appendix 2: Sample lab.

I. Problem:

Design a circuit to count the number of button presses, if pressed and held, it is still counted as
a press, and a 7-segment LED display shows the number of presses..
II. Problem analysis:

The system receives input from a push button (when the button is pressed, the system receives
bit 1, otherwise, the system receives bit 0) and displays the output on a 7-segment LED
(output less than or equal to 9). In addition, the sequential system has clock and reset inputs
(selective active low reset). When the push button is pressed, the sequencer receives signal 1
for only 1 cycle.
The circuit includes a counter, the state of the counter increments by 1 when receiving an
input signal of 1. In addition, the system needs a circuit that converts BCD to 7-segment LED,
displays the status of the counter on LED 7. paragraph.
The button block is an FSM (Finite State Machine) with 3 states: IDLE (waiting to receive),
PRESS (when the button is pressed in the first cycle), HOLD (the state is holding the button).

Figure Appendix 2.19 Block diagram

 Appendix 2: Sample lab.

Figure Appendix 2.20 Button block – state diagram

III. Design:

Create Project
Source template from GitHub to use, name it ex02

gettemplate ex02

Code

1. Create a design file named button.sv.

src/button.sv

1 module button (
2 // input
3 input logic clk_i,
4 input logic rst_ni,
5
6 input logic button_i,
7
8 // output
9 output logic stable_o
1 );
0
1 // local declaration
1 typedef enum logic [1:0] {
1 IDLE,
2 PRESS,
1 HOLD
3 } state_e;
1
 Appendix 2: Sample lab.

4 state_e state_d;
1 state_e state_q;
5
1 always_comb begin : proc_next_state
6 case (state_q)
1 IDLE: state_d = button_i ? PRESS : IDLE;
7 PRESS: state_d = button_i ? PRESS : IDLE;
1 HOLD: state_d = button_i ? HOLD : IDLE;
8 default: state_d = IDLE;
1 endcase
9 end
2
0 always_ff @(posedge clk_i) begin : proc_state_register
2 if (!rst_ni)
1 state_q <= IDLE;
2 else
2 state_q <= state_d;
2 end
3
2 // output combinational logic
4 assign stable_o = (state_q == PRESS) ? 1'b1 : 1'b0;
2
5 endmodule : button
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
 Appendix 2: Sample lab.

8
3
9
4
0
4
1
 Appendix 2: Sample lab.

2. Create a design file named counter.sv.

src/counter.sv

1 module counter (
2 // input
3 input logic clk_i,
4 input logic rst_ni,
5
6 input logic inc_i,
7
8 // output
9 output logic [3:0] counter_o
1 );
0
1 always_ff @(posedge clk_i) begin : proc_counter
1 if (!rst_ni)
1 counter_o <= '0;
2 else begin
1 if ((counter_o < 4'h9) && inc_i)
3 counter_o <= counter_o + 4'h1;
1 end
4 end
1
5 endmodule : counter
1
6
1
7
1
8
1
9
2
0
2
1
 Appendix 2: Sample lab.

3. Create a design file named hexled.sv.

src/hexled.sv

1 module hexled (
2 // input
3 input logic [3:0] data_i,
4
5 // output
6 output logic [6:0] hex_o
7 );
8
9 always_comb begin : proc_7seg_decoder
1 case (data_i)
0 4'h0: hex_o = 7'b100_0000;
1 4'h1: hex_o = 7'b111_1001;
1 4'h2: hex_o = 7'b010_0100;
1 4'h3: hex_o = 7'b011_0000;
2 4'h4: hex_o = 7'b001_1001;
1 4'h5: hex_o = 7'b001_0010;
3 4'h6: hex_o = 7'b000_0010;
1 4'h7: hex_o = 7'b101_1000;
4 4'h8: hex_o = 7'b000_0000;
1 4'h9: hex_o = 7'b001_1000;
5 4'ha: hex_o = 7'b000_1000;
1 4'hb: hex_o = 7'b000_0011;
6 4'hc: hex_o = 7'b100_0110;
1 4'hd: hex_o = 7'b010_0001;
7 4'he: hex_o = 7'b000_0110;
1 4'hf: hex_o = 7'b000_1110;
8 endcase
1 end
9
2 endmodule : hexled
0
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2
 Appendix 2: Sample lab.

7
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 Appendix 2: Sample lab.

4. Create a design file named design_2.sv.

src/design_2.sv

1 module design_2 (
2 // input
3 input logic clk_i,
4 input logic rst_ni,
5
6 input logic button_i,
7
8 // output
9 output logic [6:0] led_o
1 );
0
1 // local declaration
1 logic inc;
1 logic [3:0] counter;
2
1 button button0 (
3 .clk_i (clk_i ),
1 .rst_ni (rst_ni ),
4 .button_i(button_i),
1 .stable_o(inc )
5 );
1
6 counter counter0 (
1 .clk_i (clk_i ),
7 .rst_ni (rst_ni ),
1 .inc_i (inc ),
8 .counter_o(counter)
1 );
9
2 hexled hexled0 (
0 .data_i(counter),
2 .hex_o (led_o)
1 );
2
2 `ifdef VERILATOR
2 /*verilator lint_off UNUSED*/
3 logic pastvld;
2 always @(posedge clk_i) begin
4 pastvld <= 1'b1;
2
5 if (pastvld && $past(inc))
2 assert(!inc);
6
2 assert(counter <= 4'h9);
 Appendix 2: Sample lab.

7 end
2 /*verilator lint_on UNUSED*/
8 `endif
2
9 endmodule : design_2
3
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 Appendix 2: Sample lab.

Note: in the previous post because the circuit does not have a clock, but the assertion requires
a clock, so you must create assertions in the file top.sv . As for this example, there is clock
and binding outputs including outputs of button and counter , so assertions need to be
placed in
 Appendix 2: Sample lab.

design_2.sv , so can set binding for button output - with 1 click driving only output
up 1 in 1 cycle, which means the button's output cannot be equal to 1 in 2 consecutive cycles
(line 42) – and counter – only counts from 0 to 9 (line 44).
There is an extra signal pastvld, because in order to use $past to get the value at the
previous cycle, that value needs to be valid.
Since the pastvld is the signal for verification, and the asserts too, need to be ignored
when pouring into the KIT, put those lines in the following block:

3 `ifdef VERILATOR
5 /*verilator lint_off UNUSED*/
3
6 ...

.. /*verilator lint_on UNUSED*/

`endif
4
6
4
7
So, when running Lint Check, the part for this verification will be ignored, and so will when
running Quartus to dump it on KIT.

5. At ex02, open and add the filename in the filelist.

filelist

1 src/button.sv
2 src/counter.sv
3 src/hexled.sv
4 src/design_2.sv

6. At ex02, create a design file named top.sv.

top.sv

1 module top (
2 // input
3 input logic clk_i,
4 input logic rst_ni,
5
6 input logic button_i,
7
8 // output
9 output logic [6:0] led_o
1 );
0
 Appendix 2: Sample lab.

1 design_2 dut (
1 .clk_i (clk_i ),
1 .rst_ni (rst_ni ),
2 .button_i(button_i),
1 .led_o (led_o )
3 );
1
4 endmodule : top
1
5
1
6
1
7
1
8
1
9
 Appendix 2: Sample lab.

7. Create file driver.cpp in directory test

test/driver.cpp

1 #define MAX_SIM 200

2
3 void set_random(Vtop *dut, vluint64_t sim_unit) {
4 dut->rst_ni = (sim_unit > 4) && (rand()%30 != 0);
5 dut->button_i = (rand()%8 > 2);
6 }

a. Note 1: the input consists of rst_ni and button_i.

b. Because this test needs to run a lot to see the counter counting to 9, it is
necessary to set MAX_SIM to a large value, for example 200.
c. Note 2: dut->button_i = (rand()%8 > 2); the value of button_i
will be the result of rand()%8 , i.e. get a random number from 0 to 7, then
compare it with 2, which means button_i will be equal to 1 when the
random number is divided remainder is 3 to 7, and zero in the other case. Thus,
we have the probability:
P(button_i = 1) = 5/8 = 62.5%, P(button_i = 0) = 3/8 = 37.5%.
This makes the probability of button_i getting 1 of 2 consecutive cycles
higher, or the case of holding down is higher.
 Appendix 2: Sample lab.

d. Note 3: dut->rst_ni = (sim_unit > 4) && (rand()%30 != 0);

the value of rst_ni will be always zero, i.e. reset, when sim_unit <= 4 .
sim_unit is simulating unit, each clock pulse corresponds to 1 sim_unit .
Thus, we have a circuit that will reset for the first 4 cycles, then based on the
probability of (rand()%30 != 0) is 29/30 = 96.7%, or P( rst_ni = 0 ) =
3.3 %. This makes the probability that rst_ni is positively low, making it
easier to count up to 9 (and not count any more)..

Lint Check & Verification

Step 1: Run Lint Check to check for errors, make lint.
Step 2: Run Simulating to verify, make sim Debug
Step 3: Open waveform to observe the waveform, make wave.

Figure Appendix 2.21 Simulation result

DEBUG: bug at line 25 in button.sv

PRESS : state_d = button_i ? PRESS : IDLE;
→ PRESS : state_d = button_i ? HOLD : IDLE;
Recommended to fix a few more places in the button and counter modules to know
when there is a bug, how to read WARNING and ERROR to be able to debug.
Implementation
Step 1: Create wrapper.sv file.
The KEY push buttons are used to control the button_i, and rst_ni inputs (pin names as shown
in Table 4.2 in the DE2 Manual - see previous example). Assign button_i as KEY 2, rst_ni as
KEY 0. So input will be declared on line 4 and assigned on lines 12 and 13. Since the KEYs
on DE2 kit when not pressed give the value 1, to match the device Next, the button_i input of
the system is NOT of KEY 2, and rst_ni is an active low input, so there is no need to perform
the NOT operation.
 Appendix 2: Sample lab.

For the clock input, select the 50MHz clock (de2 pin clock, listed in table 4.5). Declare clock
as line 3 and wire as line 10.
The output led_o is a 7-segment led of 7 bits (the 7-segment LED on the DE2 kit is shown in
table 4.4 of the DE2 Manual file). Select led 7 segment number 0, HEX0, so the output will be
declared as line 7 and assigned as line 14.

quartus/wrapper.sv

1 module wrapper (
2 // input
3 input logic CLOCK_50,
4 input logic [2:0] KEY,
5
6 // output
7 output logic [6:0] HEX0
8 );
9
1 design_2 dut (
0 .clk_i (CLOCK_50),
1 .rst_ni (KEY[0] ),
1 .button_i(~KEY[2] ),
1 .led_o (HEX0 )
2 );
1
3 endmodule : wrapper
1
4
1
5
1
6
1
7
Step 2 : Create a project in Quartus (similar to the combinatorial design example).
Step 3: Import pin assignment of DE2 (similar to the combinatorial design example).
Step 4 : Compilation (similar to the combinatorial design example).
Step 5: Programmer (similar to the combinatorial design example).
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