COMPUTER SYSTEM ARCHITECTURE

UNIT-1

Digital Logic Circuit

What is Digital Computer? OR Explain the block diagram of digital computers.

 Digital computer is a digital system that performs various computational tasks.

 The word “DIGITAL” implies that the information in the computer is represented
by digits.
 Digital computers use the binary number system, which has two digits, 0 and 1.
 A binary digit is called a bit.
 Information is represented in digital computers in the groups of bit.
 By using various coding techniques, groups of bits can be made to represent not
only binary numbers but also other symbols, letters of alphabets and decimal digit.
 Bits are grouped together as bytes and words to form some type of
representation within the computer.
 A sequence of instructions for the computer is known as program.

Block diagram of a digital computer

Random Access Memory

Central Processing Unit

Input Output
Input-Output Processor Devices
Devices

 The hardware of the computer is usually divided into three major parts.
 The Central processing Unit (CPU) contains an arithmetic and logic unit for
manipulating data, a number of registers for storing data and control circuits for
fetching and executing instructions.
 The memory of a computer contains storage for instructions and data, it is called a
Random Access Memory (RAM) because the CPU can access any location in
memory at random and retrieve the binary information within a fixed interval of
time.
 The input and output processor contains electronic circuit for communication and
controlling the transfer of information between the computer and the outside world.
 The input and output device connected to the computer include keyboards, printers,
terminals, magnetic disk drives and other communication devices.

What is Gates? Explain the Logic Gates in brief.

  Binary information is represented in digital computers using electrical signals.
 These signals can be represented by voltage to specify one of two possible states.
 The two states represent a binary variable that can be equal to 1 or 0.
 The manipulation of binary information in a computer is done using logic circuits called
gates.
 Gates are blocks of hardware that produce signals of binary 1 or 0 when input logic
requirements are satisfied.
 There are various types of logic gates are commonly used in digital computer.
 Each gate has a different graphic symbols and operation.
 The input-output relationship of binary variables for each gate can be represented in
tabular form by Truth-Table.
 There are three types of gates:
o Basic / Fundamental Gates (AND, OR, NOT)
o Universal Gates (NAND, NOR)
o Exclusive Gates (EX-OR, EX-NOR)

LOGICAL GATES

Basic / Fundamental Gates Universal Gates Exclusive Gates

(AND, OR, NOT) (NAND, NOR) (EX-OR, EX-NOR)

Basic Gates
AND Gate:
 In this type of gate output is high only when all its inputs are high.
 If any single input is law then the output will remain low.
 So it is said that in AND gate the output is only high when the input is also high.

SYMBOL:

TRUTH-TABLE:

INPUT OUTPU
T
A B A AND
B
0 0 0
0 1 0
1 0 0

1 1 1
OR Gate:
 In this type of gate if any input signal is high then the output will be high.
 The output is only low only when all the inputs are low
SYMBOL:

TRUTH-TABLE:

INPUT OUTPU
T
A B A OR B
0 0 0
0 1 1
1 0 1

1 1 1

NOT Gate:
 This type of gate is also known as “Inverter”.
 It is a gate that contains only one input and only one output.
 The output is always opposite than the input signals.

SYMBOL:

TRUTH-TABLE:

INPUT OUTPU
T
A NOT
A
(A’)
0 1
1 0
 Universal Gates

NAND and NOR gates are known as universal gates because we can
construct any gate using NAND & NOR
gate.
NOR Gate:
 The NOR gate is the complement of the OR gate.
 As shown in the truth table that the output of NOR gate is exactly opposite than the
output of OR gate.
 This means that the output will be high when all the input is low.

SYMBOL:

TRUTH-TABLE:

INPUT OUTPU
T
A B A NOR
B
0 0 1
0 1 0
1 0 0

1 1 0

NAND Gate:
 The NAND gate is an AND gate followed by NOT gate.
 As shown in the truth table that the output of NAND gate is exactly opposite than
the output of AND gate.
 This means that the output will be high when all the input is high.

SYMBOL:

TRUTH-TABLE:
INPUT OUTPUT
A B A NAND
B
0 0 1
0 1 1
1 0 1
 1 1 0

Exclusive Gates
EX-OR Gate:
 This gate is produces high output whenever the two inputs are at opposite level.
 The EX-OR gate is the gate that produces high output for Odd number of high inputs.

SYMBOL:

TRUTH-TABLE:

INPUT OUTPUT
A B A EX-OR B
0 0 0
0 1 1
1 0 1

1 1 0

EX-NOR Gate:
 This gate is produces high output whenever the two inputs are at same level.
 The EX-OR gate is the gate that produces high output for Even number of high inputs.
 The truth table shows that output of this gate is exactly opposite of EX-OR gate.

SYMBOL:

TRUTH-TABLE:

INPUT OUTPUT
A B A EX-NOR
B
0 0 1
0 1 0
1 0 0

1 1 1
Combinational Logic Circuits

Write a note on Combinational Circuits

 A combinational circuit is the circuit where more than 1 circuit is designed into
single component.
 It has N no of inputs and M no of outputs.
 It is basically used to design digital applications and it transforms the data into
the digital manner.
 A combinational circuit is a connected arrangement of logic gates with a set of
inputs and outputs. At any given time, the binary values of the outputs are
a function of the binary values of the inputs.
 The design of a combinational circuit starts from a verbal outline of the
problem and ends in a logic circuit diagram. The procedure involves the
following steps:

1. The problem is stated.

2. The input and output variables are assigned letter symbols.
3. The truth table that defines the relationship between inputs
and outputs is derived.
4. The simplified Boolean functions for each output are obtained.
5. The logic diagram is drawn.

Arithmetic circuits:
 It is made of different arithmetic operators. There will be addition, substraction,
division, modules and any other arithmetic operations.

Half-Adder

 Half-Adder is a part of combinational circuit.

 It is basically designed for arithmetic addition.
 It is most basic digital arithmetic circuit.
 Performs the addition of two binary digits.
 The input variables of a half-adder are called the augend and the addend.
 The output variables of a half-adder are called the sum and the carry.
Full-Adder

 A full-adder performs the addition of three binary digits.

 Two half-adders can be combined to for a full-adder..
 Although a full adder has three inputs, it still only has two outputs since the
largest number is 1+1+1 = 3, and 3 can be represented by two bits.
WHAT IS THE DIFFERENCE BETWEEN HALF ADDER AND FULL ADDER?

Half adder Full adder

The most basic digital arithmetic circuit. A full-adder performs the addition of three
binary digits.
Performs the addition of two binary digits. It is used for multi bit additions.
Output is sum of two signals. Output is sum of three signals.
There are two input and two output There are three input and two output
terminal. terminal.
From full adder half adder cant not be built Two full adder makes one full adder
On EX-OR gate and one AND gate are Two EX-OR, two AND and one OR
used. gate is
used.

Flip Flops

What is Flip-flops

 A Flip-flop is a binary cell capable of storing one bit of information.

 It has two outputs, one for the normal value and one for the complement value of
the bit stored in it.
 Flip-flops are storage elements utilized in synchronous sequential circuits.
 Synchronous sequential circuits employ signals that effect storage elements only
at discrete instances of time.
 A timing device called a clock pulse generator that produces a periodic train of
clock pulses achieves synchronization.
 Values maintained in the storage elements can only change when the clock pulses.
 Hence, a flip-flop maintains a binary state until directed by a clock pulse to
switch states.
 The difference in the types of flip flops is in the number of inputs and the manner
in which the inputs affect the binary state.
 Flip-flops can be described by a characteristic table which permutates all
possible inputs (just like a truth table).
 The characteristic table of a flip-flop describes all possible outputs (called the
next state) at time Q(n+1) over all possible inputs and the present state at time Qn).
 The most common types of flip flops are:

 SR Flip-Flop (SET-RESET)
 JK Flip-Flop (MASTER SLAVE)
 D Flip-Flop (DELAY)
 T Flip-Flop (TOGGLE)
SR Flip-Flop
 Inputs:
 S (for set)
 R (for reset)
 C (for clock)

Outputs:
 Q
 Q'

The operation of the SR flip-flop is as follow.

 If there is no signal at the clock input C, the output of the circuit cannot
change irrespective of the values at inputs S and R.
 Only when the clock signals changes from 0 to 1 can the output be affected
according to the values in inputs S and R
 If S =1 and R = 0 when C changes when C changes from 0 to 1 output Q is set to 1.
If S = 0 and R =1 when C changes from 0 to 1.
 If both S and R are 0 during the clock transition, output does not change.
 When both S and R are equal to 1, the output is unpredictable and may go to either
0 or 1, depending on internal timing that occur within the circuit.

JK Flip-Flop

Inputs:
 J
 K
 C (for clock)

Outputs:
 Q
 Q'

The operation of the JK flip-flop is as follow.

 A JK Flip-Flop is a refinement of the SR flip-flop in that the indeterminate

condition of the SR type is defined in the JK type.
 Inputs J and K behave like inputs S and R to set and clear the flip-flop, respectively.
 When inputs J and K are both equal to 1, a clock transition switches the outputs of
the flip-flop to their complement state.
 Instead of the indeterminate condition of the SR flip-flop, the JK flip-flop has
a complement condition Q(n+1) = Q’(n) when both J and K are equal to 1.

D Flip-Flop
 Inputs:
 D (for data)
 C (for clock)

Outputs:
 Q
 Q'
The operation of the D flip-flop is as follow.

 The D Flip-Flop can be converted from SR Flip-Flop by inserting an inverter

between S and R and assigning the symbol D to the single input.
 The D input is sampled during the occurrence of a clock transition from 0 to 1.
 If D=1, the output of the flip-flop goes to the 1 state, but if D=0, the output of the
flip- flop goes to the 0 state.
 The next state Q(t+1) is determined from the D input. The relationship can be
expressed by a characteristic equation:
Q(t+1) = D
 D Flip-Flop has the advantage of having only one input (excluding ), but the
disadvantage that its characteristic table does not have a “no change” condition
Q(t+1) = Q(t).

T Flip-Flop

Inputs:
 T (for toggle)
 C (for clock)

Outputs:
 Q
 Q'

The operation of the T flip-flop is as follow.

 Most flip-flops are edge-triggered flip-flops, which means that the transition occurs
at a specific level of the clock pulse.
 A positive-edge transition occurs on the rising edge of the clock signal.
 A negative-edge transition occurs on the falling edge of the clock signal.
 Another type of flip-flop is called a master-slave flip-flop that is basically two flip-
flops in series.
 Flip-flops can also include special input terminals for setting or clearing the flip-
flop asynchronously. These inputs are usually called preset and clear and are useful
for initialing the flip-flops before clocked operations are initiated.

Flip-Flop Excitation Tables

 During the design of sequential circuits, the required transition from present state to next
state is known.
 What the designer needs to know is what input conditions must exist to implement
 the required transition.
 This requires the use of flip-flop excitation tables.
Excitation Tables
SR Flip-Flop Excitation
Table
Q(n+ S R
Q(n 1)
)
0 0 0 X
0 1 1 0

1 0 0 1

1 1 X 0

JK Flip-Flop Excitation
Table
Q(n Q(n+ J K
) 1)
0 0 0 X
0 1 1 X

1 0 X 1

1 1 X 0

D Flip-Flop Excitation
Table
Q(t) Q(t+1 D
)
0 0 0
0 1 1

1 0 0

1 1 1

T Flip-Flop Excitation
Table
Q(t) Q(t+1 T
)
 0 0 0
0 1 1

1 0 1

1 1 0

Write a note on Fixed point Number Representation:

Fixed point numbers are also known as whole numbers or Integers. The number of bits used
in representing the integer also implies the maximum number that can be represented in the system
hardware.
In addition to the bit length definition for integers, we also have a choice to represent them as
below:

 Unsigned Integer: A positive number including zero can be represented in this format. All
the allotted bits are utilised in defining the number. So if one is using 8 bits to represent the
unsigned integer, the range of values that can be represented is 28 i.e. "0" to "255". If 16 bits
are used for representing then the range is 216 i.e. "0 to 65535".
 Signed Integer: In this format negative numbers, zero, and positive numbers can be
represented. A sign bit indicates the magnitude direction as positive or negative. There are
three possible representations for signed integer and these are Sign Magnitude format, 1's
Compliment format and 2's Complement format.

Signed Integer – Sign Magnitude format: Most Significant Bit (MSB) is reserved for indicating
the direction of the magnitude (value). A "0" on MSB means a positive number and a "1" on MSB
means a negative number. If n bits are used for representation, n-1 bits indicate the absolute value of
the number. Examples for n=8:

Examples for n=8:

0010 1111 = + 47 Decimal (Positive number)

1010 1111 = - 47 Decimal (Negative Number)
0111 1110 = +126 (Positive number)
1111 1110 = -126 (Negative Number)
0000 0000 = + 0 (Postive Number)
1000 0000 = - 0 (Negative Number)

Write a note on Floating Point Representation.

 A number which has both an integer part as well as fractional part is
called Real or Floating point Number.
 For e.g. 2.365, 78.738789, 6.5643 etc are the examples of floating point
numbers.
 The floating point representation of numbers has two pars.

Sign Fixed Exponent

point
Mantiss
a
  The first part represents a sign fixed point number called Mantissa.
 The second part designated the position of decimal or binary point; this
part is known as exponent.
 The fixed point mantissa may be integer or fractional.
 For example : the decimal no +6132.789 is represent in floating point
with exponent and fraction as follows:

Sign Fixed Exponent

point
Mantiss
a
+ 0.6132789 04

 The value of exponent indicates that the actual position of decimal

point is 4 positions to the right of the indicated decimal point in the
fraction.
 We can also represent this number as +0.6132789 × 104 like scientific
notation.
 In general floating point is represented in the form of m × re.
 where
m=
mantissa
r = radix
e = exponent.

 In above example 6132789 is mantissa, 4 is exponent and 10 is radix.

Other Binary codes:
What is binary code?
Binary code is any data, text, or computer instructions represented using a two-symbol system.
These two numeral symbols are 0 and 1. Computers and digital electronic devices can only
communicate using 0’s and 1’s. For example, the text on your mobile app is in English, but there is a
background coding system translating those words to binary numbers for a computer to process.

Types of other binary codes

 8421 Codes
 2421 Codes
 Excess-3 Codes
 Gray Codes

8421 Code or BCD Code

The decimal numbers 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 can be expressed in Binary numbers as shown in the

following table. All these binary numbers again expressed in the last column by expanding into 4
bits. As per the weighted binary digits, the 4 Bit binary numbers can be expressed according to their
place value from left to right as 8421 (2³ 2² 2¹ 2⁰ = 8421).
 BINARY
DECIMAL NUMBER 4 BIT EXPRESSION(8421)
NUMBER

0 0 0000
1 1 0001
2 10 0010
3 11 0011
4 100 0100
5 101 0101
6 110 0110
7 111 0111
8 1000 1000
9 1001 1001

As per the above expression all the decimal numbers written in the 4 Bit binary code in the
form of 8421 and this is called as 8421 Code and also as Binary coded decimal BCD.
As this is a straight code, any Decimal number can be expressed easily because the weights of
the positions are straight for easy conversion into this 8421 code.
There are other forms of codes which are not so popular but rather confusing. They are 2421 code,
5211 code, reflective code, sequential code, non- weighted coded, excess-3 code and Grey code.
They are having their own importance for some of the exclusive applications and may be useful for
some of the special applications.

2421 Code

This code also a 4 bit application code where the binary weights carry 2, 4, 2, 1 from left to right.

DECIMAL NUMBER BINARY NUMBER

0 0
1 1
2 10
3 11
4 100
5 101
6 110
7 111
DECIMAL NUMBER BINARY NUMBER

8 1000
9 1001

Excess-3 code
The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express decimal
numbers. The Excess-3 code words are derived from the 8421 BCD code words adding (0011)2 or
(3)10 to each code word in 8421. The excess-3 codes are obtained as follows −

Example

Gray Code
It is the non-weighted code and it is not arithmetic codes. That means there are no specific weights
assigned to the bit position. It has a very special feature that, only one bit will change each time the
decimal number is incremented as shown in fig. As only one bit changes at a time, the gray code is
called as a unit distance code. The gray code is a cyclic code. Gray code cannot be used for
arithmetic operation.

Binary to Gray Codes Conversion

Gray to Binary Codes Conversion

Write a note on Error Detection Code. OR what do you mean by parity? Explain it
with error detection code.

 An error detection code is a binary code that detects error during

information transmission.
 The error detection code can not be correct error but gives just indication that
the error is presents.
 There are various techniques to detect error but the most common is parity bit.

Parity Bit

 A parity bit is an extra bit included with a binary message to make the total number
of 1’s either odd or even.
 Generally there are 2 techniques even and odd parity is used.
 In even parity bit the sum of all 1’s is even while in odd parity the sum of all 1’s is odd.
 For e.g. for three bit message has two possible parity shown in below table.
 Message P(odd) P(even)
Xyx
000 1 0

001 0 1

010 0 1

011 1 0

100 0 1

101 1 0

110 1 0

111 0 1

 During transformation of information from one location to another parity bit is

handle as follows:
o At sending end, the message transferred to parity generator.
o The parity generator generates required parity.
o Then the message transferred to destination.
o At destination the parity checker checks the proper parity adopted.
o An error is detected if the checked parity doesn’t confirm to the adopted
parity.
 The parity generator & checker network are logic circuits constructs with Exclusive
or gate.