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Mid Senior Level Interview Questions

The document outlines a comprehensive interview preparation guide for VLSI, covering topics such as UVM and SystemVerilog concepts, PCIe and AXI protocols, debugging strategies, formal verification, and architectural thinking. It includes specific questions designed to assess knowledge and problem-solving skills in these areas. The guide aims to prepare candidates for technical interviews in VLSI verification roles.

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manojgk0011
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23 views2 pages

Mid Senior Level Interview Questions

The document outlines a comprehensive interview preparation guide for VLSI, covering topics such as UVM and SystemVerilog concepts, PCIe and AXI protocols, debugging strategies, formal verification, and architectural thinking. It includes specific questions designed to assess knowledge and problem-solving skills in these areas. The guide aims to prepare candidates for technical interviews in VLSI verification roles.

Uploaded by

manojgk0011
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

VLSI FOR ALL Interview Preparation

A) UVM & SystemVerilog Deep Questions


1. Explain the UVM Phase flow. Why are build, connect, end_of_elab, start_of_sim, run phases
required?
2. What is UVM factory override? Static vs dynamic override. Example scenario where it saves
time.
3. In UVM, what is the purpose of: uvm_config_db and analysis_port / analysis_export.
4. Difference between TLM blocking vs non-blocking communication. When would you choose
each?
5. How do you synchronize sequences running on multiple sequencers?
6. You have a scoreboard mismatch. How will you debug if the root cause is driver, monitor or
DUT?
7. What is the objection mechanism in UVM? Why is it necessary?
8. Explain UVM phases jump and whether you ever used phase jumping intentionally.
9. How do you achieve functional coverage closure? If a coverpoint bin is not hitting, what do you
do?

B) SystemVerilog Coding / Concepts


10. Explain virtual interface. Why we need it in UVM?
11. Always_ff vs always_comb vs always_latch.
12. What is race condition in simulation? How do non-blocking assignments help?
13. Constraint soft vs hard constraint. rand vs randc.
14. Deep copy vs shallow copy in SystemVerilog classes.
15. How do you detect X-propagation and ensure it does not hide real bugs?

C) PCIe / AXI Protocol Questions


16. Explain LTSSM states briefly.
17. What happens during PCIe Enumeration?
18. Explain PF vs VF (SR-IOV).
19. What is Lane reversal and Link speed change?
20. What happens when link goes down? How does retraining occur?
21. How do you verify DLLP, TLP integrity?
22. AXI Write transaction steps. How do you handle out-of-order completion?
23. Explain burst types – FIXED, INCR, WRAP.
24. What is AXI exclusive access?

D) Debug / Real-World Scenarios


25. Your test is passing at block-level but failing at subsystem-level. How do you isolate the issue?
26. A coverpoint is 100% but bugs still exist. What does this mean?
27. Your simulation is hanging. How do you debug?
28. You see intermittent failures. What is your debugging approach?
29. Explain a tough bug you solved in PCIe verification.

E) Formal Verification
30. What is the difference between bounded proof vs unbounded proof?
31. What is a cover property vs assert property?
32. How do you write a connectivity check using SVA?
33. What is vacuous proof and why is it dangerous?

F) Architecture & System Thinking


34. How would you verify a Memory Controller with refresh logic and ECC?
35. If you need to scale your UVM environment for 8 PCIe ports, how do you make components
reusable?
36. What happens in a multi-clock domain design? How do you avoid CDC metastability in
verification?

G) Behavioral & Ownership Questions


37. Tell one time where you drove verification closure on your own.
38. Describe how you create a VPlan from a spec.
39. Explain a situation where the designer disagreed with your bug.

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