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VHDL Coding

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Ms.P.Sivagamasundhari ECE Department
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12 views11 pages

VHDL Coding

Uploaded by

Ms.P.Sivagamasundhari ECE Department
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SR FLIP FLOP VHDL CODING BEHAVIOR MODEL

library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity SR_FF is
PORT( S,R,CLOCK: in std_logic;
Q, QBAR: out std_logic);
end SR_FF;

Architecture behavioral of SR_FF is


begin
PROCESS(CLOCK)
variable tmp: std_logic;
begin
if(CLOCK='1' and CLOCK'EVENT) then
if(S='0' and R='0')then
tmp:=tmp;
elsif(S='1' and R='1')then
tmp:='Z';
elsif(S='0' and R='1')then
tmp:='0';
else
tmp:='1';
end if;
end if;
Q <= tmp;
QBAR <= not tmp;
end PROCESS;
end behavioral;
D FLIP FLOP VHDL CODING BEHAVIOR MODEL

library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity D_FF is
PORT( D,CLOCK: in std_logic;
Q: out std_logic);
end D_FF;

architecture behavioral of D_FF is


begin
process(CLOCK)
begin
if(CLOCK='1' and CLOCK'EVENT) then
Q <= D;
end if;
end process;
end behavioral;
JK FLIP FLOP VHDL CODING BEHAVIOR MODEL

library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity JK_FF is
PORT( J,K,CLOCK: in std_logic;
Q, QB: out std_logic);
end JK_FF;

Architecture behavioral of JK_FF is


begin
PROCESS(CLOCK)
variable TMP: std_logic;
begin
if(CLOCK='1' and CLOCK'EVENT) then
if(J='0' and K='0')then
TMP:=TMP;
elsif(J='1' and K='1')then
TMP:= not TMP;
elsif(J='0' and K='1')then
TMP:='0';
else
TMP:='1';
end if;
end if;
Q<=TMP;
Q <=not TMP;
end PROCESS;
end behavioral;
T FlipFlop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity T_FF is
port( T: in std_logic;
Clock: in std_logic;
Q: out std_logic);
end T_FF;

architecture Behavioral of T_FF is


signal tmp: std_logic;
begin
process (Clock)
begin
if Clock'event and Clock='1' then

if T='0' then
tmp <= tmp;
elsif T='1' then
tmp <= not (tmp);
end if;
end if;
end process;
Q <= tmp;
end Behavioral;
VHDL code for up counter:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SOURCE is
Port ( CLK,RST : in STD_LOGIC;
COUNT : inout STD_LOGIC_VECTOR (3 downto 0));
end SOURCE;

architecture Behavioral of SOURCE is

begin
process (CLK,RST)
begin

if (RST = '1')then
COUNT <= "0000";
elsif(rising_edge(CLK))then
COUNT <= COUNT+1;

end if;
end process;
end Behavioral;

VHDL code for Down counter


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity down_count is
Port ( clk,rst : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end down_count;

architecture Behavioral of down_count is

signal temp:std_logic_vector(3 downto 0);


begin
process(clk,rst)
begin

if(rst='1')then
temp<="1111";
elsif(rising_edge(clk))then
temp<=temp-1;
end if;
end process;

count<=temp;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Decade counter or MOD 10 counter asynchronous using


structural model

CODE FOR JK FF
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity JK_FF is
-- Port Declaration
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
clk : in STD_LOGIC;
preset : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC);
end JK_FF;

architecture RTL of JK_FF is

--Signal Declaration
signal FF_input : STD_LOGIC_VECTOR (1 downto 0);
signal Def_Val : STD_LOGIC := '0';

begin

FF_input <= J & K;

process(clk, preset, reset)


begin

if (preset = '1') then

if (reset = '0') then


Def_Val <= '0';

-- Making our counter as negative-edge triggered


elsif (falling_edge (clk)) then
case(FF_input) is

when "00" => Def_Val <= Def_Val;


when "01" => Def_Val <= '0';
when "10" => Def_Val <= '1';

when others => Def_Val <= not(Def_Val);


end case;

end if;
end if;
end process;

Q <= Def_Val;

end RTL;

CODE FOR DECADE COUNTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Counter is
-- Port Declaration
Port (clk : in STD_LOGIC;
preset : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Counter;

architecture RTL of Counter is

-- Component Declaration
component JK_FF is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
clk : in STD_LOGIC;
preset : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC);
end component;

-- Signal Declaration
signal temp : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal JK_output : STD_LOGIC_VECTOR (2 downto 0);

begin

-- Component Instantiation

FF1 : JK_FF Port map (J => '1', K => '1', clk => clk, preset => preset,
reset => reset, Q => temp(0));

JK_output(0) <= not(temp(3)) and temp(0);


FF2 : JK_FF Port map (J => JK_output(0), K => JK_output(0), clk => clk,
preset => preset, reset => reset, Q => temp(1));

JK_output(1) <= temp(0) and temp(1);


FF3 : JK_FF Port map (J => JK_output(1), K => JK_output(1), clk => clk,
preset => preset, reset => reset, Q => temp(2));

JK_output(2) <= (temp(0) and temp(3)) or (temp(2) and JK_output(1));


FF4 : JK_FF Port map (J => JK_output(2), K => JK_output(2), clk => clk,
preset => preset, reset => reset, Q => temp(3));
Q <= temp;

end RTL;
4 bit ripple carry adder or 4 bit binary parallel adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Ripple_Adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Ripple_Adder;

architecture Behavioral of Ripple_Adder is

-- Full Adder VHDL Code Component Decalaration


component full_adder_vhdl_code
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;

-- Intermediate Carry declaration


signal c1,c2,c3: STD_LOGIC;

begin

-- Port Mapping Full Adder 4 times


FA1: full_adder_vhdl_code port map( A(0), B(0), Cin, S(0), c1);
FA2: full_adder_vhdl_code port map( A(1), B(1), c1, S(1), c2);
FA3: full_adder_vhdl_code port map( A(2), B(2), c2, S(2), c3);
FA4: full_adder_vhdl_code port map( A(3), B(3), c3, S(3), Cout);

end Behavioral;

VHDL coding for 8 × 1 MUX


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer is
Port ( x:in STD_LOGIC_VECTOR (7 downto 0);
sel:in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC);
end multiplexer;
architecture Behavioral of multiplexer is
begin
process (x,sel)
begin
case sel is
when "000"=>y<=x(0);
when "001"=>y<=x(1);
when "010"=>y<=x(2);
when "011"=>y<=x(3);
when "100"=>y<=x(4);
when "101"=>y<=x(5);
when "110"=>y<=x(6);
when "111"=>y<=x(7);
when others=> null;
end case;
end process;
nd Behavioral;

TEST BENCH VHDL coding for 8 × 1 MUX

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_multiplexer_vhd IS
END tb_multiplexer_vhd;

ARCHITECTURE behavior OF tb_multiplexer_vhd IS

-- Component Declaration for the Unit Under Test (UUT)


COMPONENT multiplexer
PORT(
x:IN std_logic_vector(7 downto 0);
sel:IN std_logic_vector(2 downto 0);
y:OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL x : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL sel : std_logic_vector(2 downto 0) := (others=>'0');

--Outputs
SIGNAL y : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: multiplexer PORT MAP(x => x,
sel => sel,
y => y
);
x<= "01010101" after 10ns;
sel<= "001" after 10ns,"010" after 20ns,"011" after 30ns,"100" after 40ns,"101" after 50ns,"110"
after 60ns, "111" after 70ns;

END;

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