KIET Group of Institutions, Ghaziabad

Department of Computer Science & Engineering

(An ISO – 9001: 2015 Certified & ‘A’ Grade accredited Institution by NAAC)
Computer Organization and Architecture
KCS-302: Session 2020-21
Question Bank-2

1) Draw the circuit diagram of D Flip Flop.

2) Write the difference between RAM & ROM.
3) Write short note on pipelining process.
4) Write the difference between serial & parallel communication.
5) Perform the following operation on signed numbers using 2’s compliment method: (56)10
+ (-27)10
6) Differentiate between Horizontal & Vertical microprogramming.
7) Draw the block diagram for a small Accumulator based CPU.
8) How floating-point numbers are represented in computer, also give IEEE 754 standard 32-
bit floating point number format.
9) Draw the data path of sequential n bit binary divider. Give the non restoring division
algorithm for unsigned integers. Also illustrate algorithm for unsigned integer with a
suitable example.
10) What is micro programmed control unit? Give the basic structure of micro programmed
control unit. Also discuss the microinstruction format and the control unit organization for
a typical micro programmed controller using suitable diagram.
11) What do you mean by locality of reference? Explain with suitable example.
12) Differentiate between RISC & CISC based microprocessor.
13) Explain Booths multiplication algorithm in detail.
14) What is hardwired control? List various design methods for hardwired control.
15) Discuss in detail using diagram any one of the methods for designing GCD processor.
16) How pipeline performance can be measured? Discuss. Give a space time diagram for
visualizing the pipeline behavior for a four-stage pipeline.
17) Discuss the various types of address mapping used in cache memory.
18) A moving arm disc storage device has the following specifications:
a. Number of Tracks per recording surface 200
b. Disc rotation speed 2400 revolution/minute
c. Track-storage capacity 62500 bits
d. Estimate the average latency and data transfer rate of this device.
19) Convert the following pairs of decimal numbers to 5-bit 2’s-complement numbers, then
perform addition and subtraction on each pair. Indicate whether or not overflow occurs for
each case.
(a) 7 and 13
(b) −12 and 9
20) Convert the following pairs of decimal numbers to 5-bit 2’s-complement numbers, then
add them. State whether or not overflow occurs in each case.
(a) 4 and 11
(b) 6 and 14
(c) −13 and 12
(d) −4 and 8
 (e) −2 and −9
(f) −9 and −14
21) Convert the following pairs of decimal numbers to 5-bit 2’s-complement numbers, then
perform subtraction. State whether or not overflow occurs in each case.
(a) 4 and 11
(b) 6 and 14
(c) −13 and 12
(d) −4 and 8
(e) −2 and −9
(f) −9 and −14
22) A computer has a 256 KByte, 4-way set associative, write back data cache with the block
size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Each cache
tag directory entry contains, in addition, to address tag, 2 valid bits, 1 modified bit and 1
replacement bit. Find the number of bits in the tag field of an address.
23) Find the size of the cache tag directory. A computer has a 256 KByte, 4-way set associative,
write back data cache with the block size of 32 Bytes. The processor sends 32-bit addresses
to the cache controller. Each cache tag directory entry contains, in addition, to address tag,
2 valid bits, 1 modified bit and 1 replacement bit.
24) As many bits as the minimum needed to identify the memory block mapped in the cache.
What is the total size of memory needed at the cache controller to store meta-data (tags) for
the cache?
25) Consider a direct mapped cache of size 16 KB with block size 256 bytes. The size of main
memory is 128 KB. Find- Number of bits in tag, Tag directory size. consider that the
memory is byte addressable.
26) Consider a direct mapped cache of size 512 KB with block size 1 KB. There are 7 bits in
the tag. Find- Size of main memory, Tag directory size. consider that the memory is byte
addressable.
27) Consider a direct mapped cache with block size 4 KB. The size of main memory is 16 GB
and there are 10 bits in the tag. Find- Size of cache memory, Tag directory size. consider
that the memory is byte addressable.
28) Consider a 2-way set associative mapped cache of size 16 KB with block size 256 bytes.
The size of main memory is 128 KB. Find- Number of bits in tag, Tag directory size.
Consider that the memory is byte addressable.
29) Consider a 8-way set associative mapped cache of size 512 KB with block size 1 KB. There
are 7 bits in the tag. Find- Size of main memory, Tag directory size.
30) Consider a 4-way set associative mapped cache with block size 4 KB. The size of main
memory is 16 GB and there are 10 bits in the tag. Find- Size of cache memory, Tag directory
size.
31) Consider a 8-way set associative mapped cache. The size of cache memory is 512 KB and
there are 10 bits in the tag. Find the size of main memory.
32) Consider a 4-way set associative mapped cache. The size of main memory is 64 MB and
there are 10 bits in the tag. Find the size of cache memory.
33) Assume a program consists of 8 pages and a computer has 16 frames of memory. A page
consists of 4096 words and memory is word addressable. Currently, page 0 is in frame 2,
page 4 is in frame 15, page 6 is in frame 5 and page 7 is in frame 9. No other pages are in
memory. Translate the memory addresses below.
a. 111000011110000
b. 000000000000000
34) Effective Access Time example: A computer has a single cache (off-chip) with a 2 ns hit
time and a 98% hit rate. Main memory has a 40 ns access time. What is the computer’s
effective access time? If we add an on-chip cache with a .5 ns hit time and a 94% hit rate,
what is the computer’s effective access time? How much of a speedup does the on-chip
cache give the computer?
35) Assume a computer has 32-bit addresses. Each block stores 16 words. A direct-mapped
cache has 256 blocks. In which block (line) of the cache would we look for each of the
following addresses? Addresses are given in hexadecimal for convenience.
36) What do you understand by Locality of reference?
37) Differentiate between RAM and DRAM.
38) Differentiate between Horizontal and vertical micro codes.
39) Describe cycle stealing in DMA.
40) List three types of control signals.
41) Evaluate the arithmetic statement X=(A+B) *(C+D) using a general register computer with
three address, two address and one address instruction format a program to evaluate the
expression.
42) Perform the division process of 00001111 by 0011 (use a dividend of 8 bits).
43) What is associative memory? Explain with the help of a block diagram. Also mention the
situation in which associative memory can be effectively utilized.
44) Write a short note on instruction pipeline.
45) Explain the difference between vectored and non-vectored interrupt.
46) Draw the flow chart of booth’s algorithm for multiplication and show the multiplication
process using booth’s algorithm for (-7) x (+3).
47) What is a microprogram sequencer? With block diagram, explain the working of a
microprogram sequencer.
48) Draw the flow chart for adding and subtracting two fixed point binary numbers where
negative numbers are signed 1’s complement representation.
49) Give the block diagram of DMA Controller. Why are the read and write control lines in a
DMA controller bidirectional.
50) Explain all the phases of instruction cycle.
51) Explain the basic concept of Hardwired and software control unit with neat diagrams.
52) Consider page reference string 1, 3, 0, 3, 5, 6 with 3-page frames. Find number of page
faults.
53) Consider the page references 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, with 4-page frame. Find
number of page fault.
54) Consider the page reference string 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2 with 4-page frames. Find
number of page faults.
55) Consider a reference string: 4, 7, 6, 1, 7, 6, 1, 2, 7, 2. the number of frames in the memory
is 3. Find out the number of page faults respective to: Optimal Page Replacement
Algorithm, FIFO Page Replacement Algorithm, LRU Page Replacement Algorithm