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The document explains the differences between blocking and non-blocking assignments in hardware description languages, highlighting their respective uses in combinational and sequential logic. It also describes the syntax and functionality of case, casex, and casez statements in behavioral modeling. Additionally, it illustrates how different assignment attempts can affect circuit behavior and synthesis outcomes, emphasizing the importance of order in blocking assignments.

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W 8

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Prob 1:

1. Blocking assignment (=):

- Executes immediately, in sequential order inside the always
block.
- Used for combinational logic or when you need intermediate
results in the same block.

Non-blocking assignment (<=):

- Does not update immediately — schedules the new value to be

assigned after all right-hand sides (RHS) are evaluated (in the
same simulation time step).
- Used for sequential logic (flip-flops) that update on a clock edge.

2. case, casex, casez in Behavioral model:

- general form:
case (expression)
alternative1 : statement1; // any of these statements could
alternative2 : statement2; // be a compound statement
using
alternative3 : statement3; // begin/end
default : statement4; // always use default for
synth stuff
endcase
- case: can detect x and z! (good for testbenches)
- casez: uses z and ? as “don’t care” bits in case items and
expressions
- casex: uses x, z, and ? as “don’t care” bits in case items and
expressions

3. The circuit’s intended function is simple: store a & b into a D flip-flop

on the rising clock (q <= a & b). = (blocking) updates immediately
and in textual order; <= (non-blocking) schedules updates to occur
after the block (simultaneous register updates). This difference
changes both behavior and inferred hardware:
- Attempt 0 (correct form)
ab0 = a & b; q0 <= ab0; — blocking computes the temporary
immediately, non-blocking schedules q0 to receive that value this
cycle. Synthesis can fold away the temporary, producing the
desired single D-FF.
- Attempt 1 (unwanted pipeline)
ab1 <= a & b; q1 <= ab1; — both non-blocking, so q1 gets the
old ab1. Result: two registers in series (an extra clock delay).
- Attempt 2 (blocking in clocked block — risky)
ab2 = a & b; q2 = ab2; — may synthesize like Attempt 0, but
blocking in a clocked always is order-dependent and can cause
race conditions; it is not recommended for reliable RTL.
- Order effects (Attempts 3–5)
Changing the statement order can alter behavior when blocking
assignments are used: using a temporary variable before it’s
assigned reads the old value and introduces a delay—order
matters.

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W 8

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Prob 1:

1. Blocking assignment (=):

Non-blocking assignment (<=):

- Does not update immediately — schedules the new value to be

2. case, casex, casez in Behavioral model:

3. The circuit’s intended function is simple: store a & b into a D flip-flop

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