M OD U L E 5 : STAT E MACH INE S :

STAT E T RA N S IT IO N DI AG R AM
M OOR E AND MEA LY M AC HI NE S
State Machine
A state machine is a sequential circuit having a limited (finite) number of
states occurring in a prescribed order.
A counter is an example of a state machine; the number of states is called the
modulus.
Two basic types of state machines are the Moore and the Mealy.
The Moore state machine is one where the outputs depend only on the
internal present state.
The Mealy state machine is one where the outputs depend on both the
internal present state and on the inputs.
Both types have a timing input (clock) that is not considered a controlling
input.
General Models of Finite State Machines

Two types of sequential logic

In the Moore machine, the combinational logic is a gate array with outputs that determine the next state
of the flip-flops in the memory. There may or may not be inputs to the combinational logic. There may
also be output combinational logic, such as a decoder. If there is an input(s), it does not affect the
outputs because they always correspond to and are dependent only on the present state of the memory.
For the Mealy machine, the present state affects the outputs, just as in the Moore machine; but in
addition, the inputs also affect the outputs. The outputs come directly from the combinational logic and
not the memory.
Example of a Moore Machine

Modulus-26 binary counter with states 0 through 25 that is used to control the number of tablets (25) that go into
each bottle in an assembly line.
When the binary number in the memory (flip-flops) reaches binary twenty-five (11001), the counter recycles to 0
and the tablet flow and clock are cut off until the next bottle is in place.
There is no input in this case, other than the clock, so the next state is determined only by the present state, which
makes this a Moore machine. One tablet is bottled for each clock pulse. Once a bottle is in place, the first tablet is
inserted at binary state 1, the second at binary state 2, and the twenty-fifth tablet when the binary state is 25.
Count 25 is decoded and used to stop the flow of tablets and the clock. The counter stays in the 0 state until the
next bottle is in position (indicated by a 1). Then the clock resumes, the count goes to 1, and the cycle repeats
Example of a Mealy Machine
Let’s assume that the tablet-bottling system uses three different sizes of bottles: a 25-tablet bottle, a 50-tablet
bottle, and a 100-tablet bottle. This operation requires a state machine with three different terminal counts: 25,
50, and 100.

The combinational logic sets the modulus of the counter depending on the modulus-select inputs. The output of
the counter depends on both the present state and the modulus-select inputs, making this a Mealy machine.
MODULE 5: ADC AND DAC
Analog to Digital Conversion
In order to process signals using digital techniques, the incoming analog signal must be
converted into digital form.
After completing this section, you should be able to
◆ Explain the basic process of converting an analog signal to digital
◆ Describe the purpose of the sample-and-hold function
◆ Define the Nyquist frequency
◆ Define the reason for aliasing and discuss how it is eliminated
◆ Describe the purpose of an ADC
Sampling and Filtering
An anti-aliasing filter and a sample-and-hold
circuit are two functions typically found in a
digital signal processing system.
The sample-and-hold function does two
operations, the first of which is sampling.
Sampling
Sampling is the process of taking a sufficient
number of discrete values at points on a
waveform that will define the its shape.
The more samples you take, the more accurately
you can define a waveform.
Sampling converts an analog signal into a series
of impulses, each representing the amplitude of
the signal at a given instant in time.
The Sampling Theorem
The sampling theorem states that, in order to represent an
analog signal, the sampling frequency, fsample, must be at least
twice the highest frequency component fa(max) of the analog signal

Another way to say this is that the highest analog frequency can
be no greater than one-half the sampling frequency
The frequency fa(max) is known as the Nyquist frequency
Need for anti aliasing filter
When an analog signal is to be sampled, there are certain criteria that must be met in order
to accurately represent the original signal.
All analog signals (except a pure sine wave) contain a spectrum of component frequencies.
For a pure sine wave, these frequencies appear in multiples called harmonics.
The harmonics of an analog signal are sine waves of different frequencies and amplitudes.
When the harmonics of a given periodic waveform are added, the result is the original
signal.
Before a signal can be sampled, it must be passed through a low-pass filter (anti-aliasing
filter) to eliminate harmonic frequencies above a certain value as determined by the Nyquist
frequency defined by sampling theorem.
Need for anti aliasing filter
Low-pass filtering is necessary to remove all frequency components (harmonics) of
the analog signal that exceed the Nyquist frequency
If there are any frequency components in the analog signal that exceed the Nyquist
frequency, an unwanted condition known as aliasing will occur.
An alias is a signal produced when the sampling frequency is not at least twice the
signal frequency.
An alias signal has a frequency that is less than the highest frequency in the analog
signal being sampled and therefore falls within the spectrum or frequency band of
the input analog signal causing distortion.
Such a signal is actually “posing” as part of the analog signal when it really isn’t,
thus the term alias.
Holding the Sampled Value
The holding operation is the second part of the sample-and-hold function.
After filtering and sampling, the sampled level must be held constant until the next sample
occurs.
This is necessary for the ADC to have time to process the sampled value.
This sample-and-hold operation results in a “stairstep” waveform that approximates the
analog input waveform
Analog-to-Digital Conversion
Analog-to-digital conversion is the process of converting the output of the
sample and- hold circuit to a series of binary codes that represent the
amplitude of the analog input at each of the sample times.

Basic function of an analog-to-digital converter (ADC) (The binary codes and number of bits are
arbitrarily chosen for illustration only). The ADC output waveform that represents the binary
codes is also shown.
Quantization
The process of converting an analog value to a code is called
quantization.
During the quantization process, the ADC converts each sampled
value of the analog signal to a binary code.
The more bits that are used to represent a sampled value, the
more accurate is the representation.
To illustrate, let’s quantize a reproduction of the analog waveform
into four levels (0–3). Two bits are required for four levels
Quantization

Sample-and-hold output waveform with four quantization

levels. The original analog waveform is shown in light gray for
reference.
Quantization

Sample-and-hold output waveform with sixteen quantization

levels. The original analog waveform is shown in light gray for
reference.
If the resulting digital codes are used to reconstruct the original waveform, you
would get the waveforms shown below using 2 bit and 4 bit respectively. This operation is done
by digital-to analog converters (DACs), which are circuits that perform digital-to-analog
conversions.

This shows that greater accuracy is achieved with more quantization bits. Typical integrated
circuit ADCs use from 12 to 24 bits, and the sample-and-hold function is sometimes contained
on the ADC chip.
Analog-to-Digital Converters
Analog-to-digital conversion is the process by which an analog
quantity is converted to digital form.
It is necessary when measured quantities must be in digital form
for processing or for display or storage.
Two important ADC parameters are resolution, which is the
number of bits, and throughput, which is the sampling rate an
ADC can handle in units of samples per second (sps).
Flash (Simultaneous) Analog-to-Digital
Converter
The flash method utilizes special high-speed comparators that compare reference voltages
with the analog input voltage.
When the input voltage exceeds the reference voltage for a given comparator, a HIGH is
generated
A 3-bit converter uses seven comparator circuits; a comparator is not needed for the all-0s
condition. A 4-bit converter of this type requires fifteen comparators.
In general, 2n − 1 comparators are required for conversion to an n-bit binary code.
The number of bits used in an ADC is its resolution.
The large number of comparators necessary for a reasonable-sized binary number is one of
the disadvantages of the flash ADC.
Its chief advantage is that it provides a fast conversion time because of a high throughput,
measured in samples per second (sps).
A 3-bit flash ADC.
Flash (Simultaneous) Analog-to-Digital
Converter
The reference voltage for each comparator is set by the resistive voltage-
divider circuit.
The output of each comparator is connected to an input of the priority
encoder.
The encoder is enabled by a pulse on the EN input, and a 3-bit code
representing the value of the input appears on the encoder’s outputs.
The binary code is determined by the highest-order input having a HIGH
level.
The frequency of the enable pulses and the number of bits in the binary
code determine the accuracy with which the sequence of binary codes
represents the input of the ADC.
The signal is sampled each time the enable pulse is active.
 Successive-Approximation Analog-to-Digital
Converter
 The input bits of the DAC are enabled (made equal to
a 1) one at a time, starting with the most significant
bit (MSB) using a control circuitry inside SAR.
 As each bit is enabled, the comparator produces an
output that indicates whether the input signal
voltage is greater or less than the output of the DAC.
 If the DAC output is greater than the input signal, the
comparator’s output is LOW, causing the bit in the
register to reset.
 If the DAC output is less than the input signal, the 1
bit is retained in the register.
 The system does this with the MSB first, then the
next most significant bit, then the next, and so on for
the subsequent clock pulses.
 After all the bits of the DAC have been tried, the Basic block diagram of a 4-bit successive
conversion cycle is complete. approximation ADC
Successive-Approximation Analog-to-
Digital Converter - Example
4-bit conversion
Step-by-step conversion of a constant input voltage (5.1 V in this case)
Let’s assume that the DAC has the following output characteristics: Vout = 8 V for the 23 bit
(MSB), Vout = 4 V for the 22 bit, Vout = 2 V for the 21 bit, and Vout = 1 V for the 20 bit (LSB).

Figure (a) shows the first step in the conversion

cycle with the MSB = 1.
The output of the DAC is 8 V.
Since this is greater than the input of 5.1 V, the
output of the comparator is LOW, causing the
MSB in the SAR to be reset to a 0.
Figure (b) shows the second step in the conversion cycle
with the 22 bit equal to a 1.
The output of the DAC is 4 V.
Since this is less than the input of 5.1 V, the output of the
comparator switches to a HIGH, causing this bit to be
retained in the SAR.

Figure (c) shows the third step in the conversion cycle with
the 21 bit equal to a 1.
The output of the DAC is 6 V because there is a 1 on the 22
bit input and on the 21 bit input;
4 V + 2 V = 6 V.
Since this is greater than the input of 5.1 V, the output of the
comparator switches to a LOW, causing this bit to be reset to
a 0.
 Figure (d) shows the fourth and final step in the
conversion cycle with the 20 bit equal to a 1.
The output of the DAC is 5 V because there is a 1
on the 22 bit input and on the 20 bit input;
4V+1V=5V

The four bits have all been tried, thus completing

the conversion cycle.
At this point the binary code in the register is
0101, which is approximately the binary value of
the input of 5.1 V.

Additional bits will produce an even more accurate result.

Another conversion cycle now begins, and the basic process is repeated.
The SAR is cleared at the beginning of each cycle.
Digital to Analog Converters (DAC)
Digital-to-analog conversion is an important part of a digital
processing system.
Once the digital data has been processed, it is converted back to
analog form.
Binary-Weighted-Input DAC/Weighted
Resistor type DAC
It uses a resistor network with resistance values that represent the binary weights of the
input bits of the digital code.
Each of the input resistors
will either have current or
have no current, depending
on the input voltage level.
If the input voltage is zero
(binary 0), the current is also
zero.
If the input voltage is HIGH
(binary 1), the amount of
current depends on the input
resistor value and is different
for each input resistor
Binary-Weighted-Input DAC/Weighted
Resistor type DAC
Since there is practically no current into the op-amp inverting (-) input, all of the input
currents sum together and go through Rf.
Since the inverting input is at 0 V (virtual ground), the drop across Rf is equal to the output
voltage, so Vout = IfRf.
The R/2R Ladder Digital-to-Analog Converter
Another method of digital-to-analog conversion is the R/2R ladder, as shown in Figure for
four bits.
It overcomes one of the problems in the binary-weighted-input DAC in that it requires only
two resistor values.
The R/2R Ladder Digital-to-Analog Converter

Start by assuming that the D3 input is HIGH (+5 V) and the others are LOW (ground, 0 V).
This condition represents the binary number 1000. A circuit analysis will show that this
reduces to the equivalent form shown in Figure (a). Essentially no current goes through the
2R equivalent resistance because the inverting input is at virtual ground.
Figure (b) shows the equivalent circuit when the D2 input is at +5 V and the others are at ground.
This condition represents 0100. If we thevenize* looking from R8, we get 2.5 V in series with R, as
shown.
This results in a current through Rf of I = 2.5 V/2R, which gives an output voltage of -2.5 V. Keep
in mind that there is no current into the opamp inverting input and that there is no current
through the equivalent resistance to ground because it has 0 V across it, due to the virtual
ground.
Figure (c) shows the equivalent circuit when the D1 input is at +5 V and the others are at ground.
This condition represents 0010.
Again thevenizing looking from R8, you get 1.25 V in series with R as shown.
This results in a current through Rf of I = 1.25 V/2R, which gives an output voltage of -1.25 V.
In part (d) of Figure, the equivalent circuit representing the case where D0 is at +5 V and the
other inputs are at ground is shown. This condition represents 0001.
Thevenizing from R8 gives an equivalent of 0.625 V in series with R as shown. The resulting
current through Rf is I = 0.625 V/2R, which gives an output voltage of -0.625 V.
Notice that each successively lower-weighted input produces an output voltage that is halved, so
that the output voltage is proportional to the binary weight of the input bits.
Performance Characteristics of Digital-to-Analog
Converters
Resolution (Step size)
The resolution of a DAC is the reciprocal of the number of discrete steps in the output.
 This, of course, is dependent on the number of input bits.
 For example, a 4-bit DAC has a resolution of one part in 24 - 1 (one part in fifteen).
Expressed as a percentage, this is (1/15)100 = 6.67%.
The total number of discrete steps equals 2n - 1, where n is the number of bits.
Resolution can also be expressed as the number of bits that are converted.
By increasing the number of input bits, the number of possible output values can be
increased and also the step size (difference between two successive output values) can be
reduced, thereby producing an output more like an analog quantity.
Accuracy
Accuracy is derived from a comparison of the actual output of a DAC with the expected
output.
It is expressed as a percentage of a full-scale, or maximum, output voltage.
For example, if a converter has a full-scale output of 10 V and the accuracy is ;0.1%, then the
maximum error for any output voltage is (10 V)(0.001) = 10 mV.
Ideally, the accuracy should be no worse than ;1/2 of a least significant bit.
For an 8-bit converter, the least significant bit is 0.39% of full scale.
The accuracy should be approximately ;0.2%.
Linearity. A linear error is a deviation from the ideal straight-line output of a DAC. A special
case is an offset error, which is the amount of output voltage when the input bits are all
zeros.
Monotonicity. A DAC is monotonic if it does not take any reverse steps when it is sequenced
over its entire range of input bits.
Settling time. Settling time is normally defined as the time it takes a DAC to settle within ;1/2
LSB of its final value when a change occurs in the input code.
MODULE 5: PROGRAMMABLE LOGIC DEVICES
Introduction
Fixed-function logic Ics (Mux, demux, adder, decoder etc.) perform a fixed digital operation.
To implement small segments of logic, it may be more efficient to use fixed-function logic.
Disadvantages:
Large board space requirements
Large power requirements
Lack of security
Additional cost, space, power requirement etc. to modify the design

Programmable logic requires both hardware and software.

Programmable logic devices can be programmed to perform specified logic functions and
operations by the manufacturer or by the user. (user configurable)
Advantages of programmable logic
The devices use much less board space for an equivalent amount of logic.
Designs can be readily changed without rewiring or replacing components.
A logic design can generally be implemented faster and with less cost with programmable
logic than with fixed-function logic.
Less power requirement
High reliability
Easy circuit testing
Programmable Logic
Many types of programmable logic are available, ranging from small devices that can replace
a few fixed-function devices to complex high-density devices that can replace thousands of
fixed-function devices.

PLD (Programmable logic device)

SPLDs (simple PLDs)
CPLDs (complex PLDs).

FPGA (field-programmable gate array)

Programmable logic hierarchy.

Simple Programmable Logic Device (SPLD)
Block diagrams of simple programmable logic devices (SPLDs).

PAL (programmable array logic) GAL (generic array logic)

A device that can be programmed one A device that is basically a PAL that can be
time. It consists of a programmable array reprogrammed many times. It consists of a
of AND gates and a fixed array of OR gates reprogrammable array of AND gates and a fixed
array of OR gates with programmable ouputs
PAL (programmable array logic)
Consists of a programmable array of AND gates that connects to a fixed array of OR gates.
Generally, PALs are implemented with fuse process technology and are, therefore, one-time
programmable (OTP).
Fuse process technology uses high voltage pulse which is applied into the fuse to blow it
and thus, the connection between two points can be opened.
The PAL structure allows any sum-of-products (SOP) logic expression with a defined
number of variables to be implemented.
PAL (programmable array logic)
A simple PAL structure is shown in Figure for two
input variables and one output; most PALs have
many inputs and many outputs.
A programmable array is essentially a grid or
matrix of conductors that form rows and columns
with a programmable link at each cross point.
Each programmable link, which is a fuse in the
case of a PAL, is called a cell.
Each row is connected to the input of an AND gate,
and each column is connected to an input variable
or its complement.
By programming the presence or absence of a fuse
connection, any combination of input variables or
complements can be applied to an AND gate to
form any desired product term. Basic AND/OR structure of a PAL
The AND gates are connected to an OR gate,
creating a sum-of-products (SOP) output.
PAL (programmable array logic)
Implementing a Sum-of-Products Expression
An example of a simple PAL is programmed as
shown in Figure so that the product term AB is
produced by the top AND gate, is produced
by the middle AND gate, and is produced by
the bottom AND gate.
The fuses are left intact to connect the desired
variables or their complements to the
appropriate AND gate inputs.
The fuses are opened where a variable or its
complement is not used in a given product
term.
PAL implementation of a sum-of-products expression
The final output from the OR gate is the SOP
expression,
PLA (Programmable Logic Array)
The PLA has a programmable AND
array followed by a programmable OR
array
L4: FPGA AND INTRODUCTION TO HDL
Field-Programmable Gate Arrays (FPGAs)
The classic CPLD architecture consists of PAL/GAL or PLA-type
logic blocks with programmable interconnections.
Basically, the FPGA (field-programmable gate array) differs in
architecture, does not use PAL/PLA type arrays, and has much
greater densities than CPLDs.
A typical FPGA has many times more equivalent gates than a typical
CPLD.
The logic-producing elements in FPGAs are generally much smaller
than in CPLDs, and there are many more of them.
Also, the programmable interconnections are generally organized
in a row and column arrangement in FPGAs.
 The three basic elements in an FPGA
are the configurable logic block (CLB),
the interconnections, and the
input/output (I/O) blocks

CLB is configurable logic block,

also known as logic array block
(LAB)

When the CLBs are relatively

Basic structure of an FPGA simple, the FPGA architecture is
called fine grained.
When the CLBs are larger and
more complex, the architecture
is called coarse grained.
Field-Programmable Gate Arrays (FPGAs)
The I/O blocks around the perimeter of the structure provide individually
selectable input, output, or bidirectional access to the outside world.
The distributed matrix of programmable interconnections provide for
interconnection of the CLBs and connection to inputs and outputs.
Large FPGAs can have tens of thousands of CLBs in addition to memory and
other resources.
Field-Programmable Gate Arrays (FPGAs)
Most programmable logic manufacturers make a series of FPGAs that range
in density, power consumption, supply voltage, speed, and to some degree
vary in architecture.
FPGAs are reprogrammable and use SRAM or antifuse process technology
for the programmable links.
Densities can range from hundreds of logic modules to hundreds of
thousands of logic modules in packages with up to over 1,000 pins.
DC supply voltages are typically 1.8 V to 5 V, depending on the specific
device.
Programming
To define the behavior of the FPGA, the user provides a design in a hardware description
language (HDL) or as a schematic design.
The HDL form is more suited to work with large structures because it's possible to specify high-
level functional behavior rather than drawing every piece by hand.
However, schematic entry can allow for easier visualization of a design and its
component modules.
Using an electronic design automation tool, a technology-mapped netlist is generated.
The netlist can then be fit to the actual FPGA architecture using a process called place-and-route,
usually performed by the FPGA company's proprietary place-and-route software. The user will
validate the map, place and route results via timing analysis, simulation, and other verification
and validation methodologies. Once the design and validation process is complete, the binary file
generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the
FPGA. This file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external
memory device like an EEPROM.
How is HDL different from C/C++?
Hardware Description Language
(HDL)
Digital circuits consist of interconnected transistors.
A central processing unit (CPU) can be considered as a vast sea of transistors, but
it is much easier to organize transistors into logic gates, logic gates into adders or
registers or timing modules, registers into memory banks, and so forth.
This hierarchical structure allows us to effectively represent a digital circuit by
means of interconnected diagrams. We call this a schematic. This visual approach to
describing a digital circuit becomes impractical as complexity increases.
Another way to describe digital circuits is to use a textual language that is
specifically intended to clearly and concisely capture the defining features of
digital design.
Such languages exist, and they are called hardware description languages (HDLs).
Structure of an HDL code (Verilog
example)
Structure of an HDL code (Verilog
example)
Structure of an HDL code (Verilog
example)
Final design example
Verilog modelling
Three modeling styles in Verilog.
Gate Level modeling
Dataflow modeling
Behavioral modeling
Gate level modelling
Eg: AND is the operation performed on A, B, to get output Y.
endmodule terminates the module.
Verilog has this functionality to describe the circuit at the gate level.
The compiler understands that the AND operation means that it has to get a product of the
inputs.
Dataflow modeling
Compared to gate-level modeling, dataflow modeling in Verilog is a higher
level of abstraction.
What this means is, you don’t really need to know the circuit design.
That’s really helpful because gate-level modeling becomes very complicated
for a complex circuit.
All you need to know is the boolean logic equation of the output of the circuit
in terms of its inputs.
We use continuous assignments in dataflow modeling in most of the designs.
The continuous assignments are made using the keyword assign
Behavioral Modelling
Behavioral modeling is the highest level of abstraction in
the Verilog HDL.
All that a designer need is the algorithm of the design, which is
the basic information for any design.
This level simulates the behavior of the circuits; the details are
not specified.
That’s helpful because the designer does not have to deal with
complicated circuitry or equations.
Just a simple truth table would suffice
Examples in verilog
Half Adder

module half_adder(input a, b, output s, Cout);

assign S = a ^ b; –This is same as xor(sum,a,b)
assign Cout = a & b; –This is same as and(carry,a,b)
endmodule
VHDL
Configuration
Entity
Architecture
Sample Program

Declaration of entity

Set of input and output pins declaration

End of entity
Declaration of architecture

End of architecture
Sample Program
Libraries and Packages
Models in VHDL
Data Flow Model
Structural Model
Behavioural Model
Dataflow model
Half adder
Structural Model
Behavioral Model
Behavioural Model: architecure
Behavioural Model
Behavioural Model
Sequential Statements used in PROCESS statement
(Behavioral model)
Behavioral model: example
4 bit magnitude comparator
4 bit magnitude comparator contd..
Example: Full adder using dataflow model
NB: (Kindly do not misunderstand this
as behavioral model…its dataflow model
itself. Just the name of architecture is
given as behavioral since its so, by
default in the software)
Example: Full adder in structural model
Example: Full adder in structural
model