1.

Consider a cache consisting of 256 blocks of 16 words each for a total of 4096 words
and assume that the main memory is addressable by a 16 bits address and it consists of
4K blocks. How many bits are there in each of TAG, SET, WORD field for 2-way set
associative technique?

[Link] the steps involved in an instruction cycle.

3. How memory read and write operations are performed in computer system?

4. Define HIT and MISS ratio in memory with an example.

5. Define instruction cycle.

6. Di erentiate between RISC and CISC.

7. List the di erence between static RAM and dynamic RAM.

8. Define Virtual memory.

9. List down the functions performed by an Input/Output unit.

10 Why does the DMA get priority over CPU when both request memory transfer?
Explain functional units of computer system in detail.

11. Explain IEEE-754 standard for floating point representation. Express (314.175)10 in
all the IEEE-754 models.

11. Explain the concept of pipelining and also explain types of pipelining technique?

12. Define interrupt. Also discuss di erent types of interrupt.

13 Solve (15) × (-16) using Booth’s Algorithm.

14. Write a program to evaluate the arithmetic statement. P = ((X − 𝑌 + 𝑍) ∗ (A ^ B))/( C ^

D ∗ E) By using (i) three and Two address instructions (ii) One address instructions (iii)
Zero address instructions

15. What are the di erences between hardwired and micro-programmed control unit?

16. Discuss the Memory Hierarchy in computer system with regard to Speed, Size and
Cost.

16. Write a short notes on magnetic disk, magnetic tape and optical disk.

17.a. With a neat schematic diagram, explain about DMA controller and its mode of
data transfer.

(b) Discuss the design of a typical input or output interface

[Link]fine Restoring and non restoring division Method . Solve 19/7 by both the
methods.
19. What do you mean by page fault.

[Link] the term cycle stealing.

[Link] do you mean by Vector Interrupt.

[Link] X=A+B*[C*D+E*(F+G)] by using 3,2,1 and zero address operations

instructions.

[Link] the flow chart for instruction cycle with suitable diagram and Explain.

[Link] 2D and 2.5 D RAM with suitable diagram.

[Link] and explain the block diagram of typical DMA controller.

Represent the no 1460.125 in single and double precision format.

[Link] is micro program sequencer ? With block diagram explain the working of Micro
program sequence.

27. What is vertical and Horizontal Microprograming.

[Link] the page fault for a given string with the help of LRU and FIFO page
replacement algorithm , Sizes of frames =4 and string
1,2,3,4,2,1,5,6,2,1,2,3,7,6,3,2,1,2,3,6.

29.A computer uses Ram chips of 1024 *1 capacity .

a. How many chips are needed & how should their address lines be connected to
provide a memory capacity of 1024*8.

[Link] many chips are needed to provide a memory capacity of 16KB.

30 What is the asynchrous data transfer. Explain Strobe and hand shaking mechanism.

[Link] the di erent modes of Data Transfer.

32. What are the di erent phases of an instruction cycle?

33. How does control unit of a computer works?

34. Write a short not on locality of reference.

35. In what way synchronous and asynchronous serial modes of data transfer di er?
36. What is pipelining? What are the di erent stages of pipelining? Explain in detail.

37. Give classification of memory based on the method of access. Also discuss
construction and working of magnetic disk and various components of disk access
time.

38. What are the basic di erences between interrupt initiated I/O and programmed I/O?
Explain in detail.

[Link] the following decimal number in IEEE standard floating-point format in a

single precision method (32 bit) representation method. (i) (85.125) base 10 (ii) (-
307.1875) base 10

40. Di erentiate between hardwired and micro programmed control unit. Explain each
component of hardwired control unit organization.

41. Consider a cache (M1) and memory (M2) hierarchy with following characteristics: -
M1 : 16K word, 50 ns Access time M2 : 1M word, 400 ns Access time Assume 8-word
cache blocks and set size 256 words with set associative mapping. (i) Show and explain
the mapping between M2 and M1. (ii) b. Calculate the e ective memory access time
with cache hit ratio=0.95.

[Link] the direct mapping technique. Consider a digital computer has a memory
unit of 64k*16 and cache memory of 1k words. The cache uses direct mapping with 4
block size of four words. (i) How many bits are there in the tag, block and word fields of
the address format? (ii)How many blocks can the cache accommodate?

[Link] how DMA is superior to other modes.

44. Di erentiate between horizontal and vertical microprogramming.

[Link] is the transfer rate of an eight-track magnetic tape whose speed is 120 inches
per second and whose density is 1600 bits per inch?

[Link] A holds the binary values [Link] is the register value after
arithmetic shift right? Starting from the initial number 10011101, determine the register
value after arithmetic shift left, and state whether there is an overflow.

47. What is an Associative memory. Direct and Set associative memory mapping? What
are their advantages and disadvantages?

48. Di erentiate between static RAM and Dynamic RAM.

49 What are the di erent types of instruction formats?

50. What is FIFO. LRU and optimal page replacement algorithm.

51. A digital computer has a common bus system for 8 registers of 16 bit each. The bus
is constructed using multiplexers. I. How many select input are there in each
multiplexer? II. What is the size of multiplexers needed? III. How many multiplexers are
there in the bus?

52. Explain destination-initiated transfer using handshaking method.

53. A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words.
The cache uses direct mapping with a block size of four words. I. How many bits are
there in the tag, index, block, and word fields of the address format? II. How many bits
are there in each word of cache, and how they are divided into functions? Include a valid
bit. III. How many blocks can the cache accommodate?

[Link] with neat diagram, the address selection for control memory.

55. Draw a diagram of a Bus system in which it uses 3 state bu ers and a decoder
instead of the multiplexers.

[Link] logical address space in a computer system consists of 128 segments. Each
segment can have up to 32 pages of 4K words each. Physical memory consists of 4K
blocks of 4K words each. Formulate the logical and physical address formats.

57. How is the Virtual address mapped into physical address? What are the di erent
methods of writing into cache?

58. Explain how the computer buses can be used to communicate with memory and
I/O. Also draw the block diagram for CPU-IOP communication.

59. Write a program to evaluate arithmetic expression using stack organized computer
with 3 address and 0-address instructions. X = (A-B) * (((C - D * E) / F) / G) and state what
is di erence between np of instructions are there.

[Link] the di erences between hardwired and micro programmed control in tabular
format. Write the sequence of control steps for the following instruction for single bus
architecture. R1 R2 * (R3).

61. Discuss the micro-operations in computer architecture?

62. Explain the purpose and state the di erence between RAM,ROM ,Static and
Dynamic RAM, PROM,EPROM and EEPROM memories in computer systems?

[Link] the concept of horizontal and vertical microprogramming in control unit

design?

63. Discuss the characteristics and functionalities of auxiliary memories such as

magnetic disks, magnetic tapes, and optical disks?
[Link] the functions and characteristics of I/O ports and their significance in
facilitating data exchange between the CPU and external devices?

[Link] the di erence between RISC and CISC.

[Link] the concept of microprogram sequencing and how it enables the execution
of complex instructions through a sequence of microinstructions?

67. Design and explain the fundamental concept of computer memory hierarchy?
[Link] the architecture and operation of semiconductor RAM (Random Access
Memory) memories such as DRAM (Dynamic RAM) and SRAM (Static RAM)?

69. Describe the role of peripheral devices in a computer system and explain how they
interact with the CPU through I/O interfaces and ports?

[Link] the Direct Memory Access (DMA) techniques for data transfer?

71. what is program control. Explain the Program control commands.

[Link] the execution of a complete instruction by neat and clean diagram.

[Link] is cache memory. Define the Cache memory usage, its types and design.

[Link]fine the Pipelining concept its type and define the Performance parameters of
pipelining.

[Link] are interrupts. Define the Interrupts type.