RF FRONT END TRANSMITTER

Project Group 17
Amarnath K R : LTCR22EC069
Melvin K V : TCR22EC035
Ragendu Menon : TCR22EC050
Ronia Ann Francis : TCR22EC053

Under the Guidance of

Dr. Roy Francis

Department of Electronics and Communication Engineering

Government Engineering College, Thrissur

October 18, 2025

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Introduction

RF (Radio Frequency) transmitters generate and send electromagnetic signals through

antennas.

Converts baseband signals (audio/data) into high-frequency RF signals.

Used in wireless communication: mobile phones, Wi-Fi, satellite, radar, and 6G.

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Objective

To design, simulate, and analyze an RF front-end transmitter operating in the 2.4 GHz
ISM band using Cadence Virtuoso.

To model key blocks such as the preamplifier, mixer, voltage amplifier, power amplifier,
and voltage-controlled oscillator (VCO).

To ensure optimal output power, frequency accuracy, and impedance matching for
Bluetooth communication.

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Background

Wireless communication systems depend on efficient and low-power RF transmitters.

Bluetooth technology operates in the 2.4 GHz ISM band using Gaussian Frequency Shift
Keying (GFSK).

Cadence Virtuoso enables accurate schematic design, simulation, and physical verification
for analog/RF ICs.

Optimized front-end design is essential for modern IoT and low-energy Bluetooth devices.

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Problem Statement

Achieving stable frequency generation with low phase noise in the VCO.

Ensuring signal integrity and power efficiency in amplifier stages.

Maintaining proper 50 Ω impedance matching to minimize reflections.

Reducing power consumption while maintaining sufficient transmission power.

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Scope of the Project

Design and simulation of transmitter blocks (VCO, amplifiers, mixer) using Cadence
Virtuoso.

Integration of all functional blocks to form a complete RF front-end transmitter.

Layout design and verification using Calibre (DRC, LVS, PEX).

Evaluation of transmitter performance parameters such as output power, frequency

stability, and modulation quality.

Applicable to Bluetooth and IoT devices operating in the 2.4 GHz band.

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BLOCK DIAGRAM OF RF TRANSMITTER

Antenna

Voltage Power
Pre Amplifier Mixer
Amplifier Amplifier

VCO

Figure 1: General Block Diagram of RF Transmitter

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Specifications
System-Level Specifications

1. Frequency Band:
Bluetooth operates in 2.4 GHz ISM band
2400 MHz to 2483.5 MHz
Width: ∼83.5 MHz wide
40 channels, each 2 MHz wide
“ISM” = Industrial, Scientific, and Medical — a license-free band

2. Modulation Scheme
Gaussian Frequency Shift Keying (GFSK) is used
Modulation index: ∼0.5 (frequency deviation ≈ ±250 kHz)

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Specifications (continued)
FSK (Frequency Shift Keying):
Digital data is sent by shifting the carrier frequency between two values:
1 → transmit at fc + ∆f
0 → transmit at fc − ∆f

Gaussian Filtering → GFSK

Gaussian filter smooths transitions and reduces spectral splatter.
Bluetooth applies this before frequency modulation.

3. Data Rate
BLE: 1 Mbps (mandatory), 2 Mbps (optional in 5.x)

4. Output Power
+4 dBm typical
Regulatory limit: +20 dBm
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Specifications (continued)

4. Channel Bandwidth / Spacing

Channel spacing: 2 MHz → center frequencies 2 MHz apart.
Occupied bandwidth: ≈1 MHz.
Total channels: 40 (37 data + 3 advertising).
Guard gap between channels reduces interference.

5. Transmit Current
Transmit current target: 5–20 mA.

6. Output Impedance
Normally 50 Ω for antenna matching.

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IMPLEMENTATION : UNBALANCED MIXER CIRCUIT

VLO

VRF VIF
The unbalanced mixer is the
simplest mixer topology.
RL
Conversion gain = −10.6 dB.

Figure 2: Circuit of Unbalanced Mixer

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IMPLEMENTATION : SINGLE BALANCED MIXER CIRCUIT

VLO

RL

Vout1
The single balanced mixer uses
VRF
one balanced input LO and one
Vout2
unbalanced input RF.
RL Conversion gain = −4.7 dB.

VLO

Figure 3: Circuit of Single Balanced Mixer

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IMPLEMENTATION : DOUBLE BALANCED MIXER CIRCUIT

VLO

RL

Vout1

VRF

A double-balanced mixer
VLO suppresses both the LO and RF
feedthrough components at the
VRF IF port.
Vout2

RL
Conversion gain = −1.83 dB.
VLO

Figure 4: Circuit of Double Balanced Mixer

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IMPLEMENTATION : TEST BENCH OF DOUBLE BALANCED
MIXER

+ 2.4GHz 2.4GHz +
− 900mV −
0mV
0mV 900mV

VLO VLO

VRF − Vout1

VRF + Vout2

+
− 1MHz GND
-200mV

+
− 1MHz
200mV

Figure 5: Test Bench of Double Balanced Mixer

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IMPLEMENTATION : UNBALANCED MIXER VIRTUOSO
SCHEMATIC

Figure 6: Unbalanced Mixer Virtuoso Schematic

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IMPLEMENTATION : SINGLE BALANCED MIXER VIRTUOSO
SCHEMATIC

Figure 7: Single Balanced Mixer Virtuoso Schematic

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IMPLEMENTATION : DOUBLE BALANCED MIXER
VIRTUOSO SCHEMATIC

Figure 8: Double Balanced Mixer Virtuoso Schematic

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IMPLEMENTATION : DOUBLE BALANCED MIXER TEST
BENCH VIRTUOSO SCHEMATIC

Figure 9: Double Balanced Mixer Test Bench Virtuoso Schematic

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IMPLEMENTATION : PRELAYOUT TRANSIENT RESPONSE

Figure 10: Prelayout Transient Response

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IMPLEMENTATION : LAYOUT OF DOUBLE BALANCED
MIXER

Figure 11: Layout of Double Balanced Mixer

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IMPLEMENTATION : POSTLAYOUT TRANSIENT RESPONSE

Figure 12: Postlayout Transient Response

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Project Timeline
Phase – 1 (Overview)

The project spanned four months, following a structured workflow from concept to layout
implementation. The summary of activities is shown below:
gray!30 Month Phase Key Activities
July Planning & Research Selected Bluetooth Low Energy (BLE) as
the target application. Studied RF transmit-
ter basics and finalized system-level specifi-
cations and modulation scheme.
August Literature Survey Explored mixer topologies — unbalanced,
balanced, and double-balanced. Compared
conversion gain, linearity, and isolation to
identify optimal architectures.

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Project Timeline (continued)
Phase – 1 (Design and Implementation)

gray!30 Month Phase Key Activities

September Mixer Design Implemented schematic-level designs of un-
balanced, balanced, and double-balanced
mixers in Cadence Virtuoso. Verified con-
version gain and power consumption through
simulation.
October Layout Design Designed mixer layout using UMC 28 nm
process. Performed DRC and LVS checks,
minimized parasitics, and compared post-
layout and schematic results.

Outcome: Completed schematic-to-layout implementation of BLE mixer topologies.

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Future Work
Phase – 2: VCO Design

Objective: Extend the BLE transmitter by adding key RF building blocks for enhanced
performance.
VCO Design Goals:
Design a low phase-noise VCO for 2.4 GHz BLE operation.
Explore LC-tank and ring oscillator topologies for optimal tuning range and stability.
Integrate the VCO with the mixer to analyze frequency stability and signal purity.
Verify output frequency accuracy, tuning linearity, and phase noise through simulations.
Expected Result: A stable, tunable frequency source compatible with BLE specifications.

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Future Work (continued)
Power Amplifier Design and Expected Outcome

Power Amplifier (PA) Design Goals:

Develop a high-efficiency PA to amplify the RF output signal.
Compare Class AB, Class C, and CMOS PA topologies.
Optimize for gain, linearity, power-added efficiency (PAE), and low power
consumption.
Integrate PA with mixer and VCO to form a complete RF transmitter chain.
Expected Outcome:
Fully integrated BLE-compatible RF transmitter chain.
Improved signal quality, reduced phase noise, and efficient power delivery.
Insights into VCO–PA–Mixer integration challenges in modern CMOS design.

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Tools Used

Schematic Design and Entry: Virtuoso Schematic Editor

Simulation and Characterisation: Virtuoso ADE (Analogue Design Environment)

Layout Design: Virtuoso Layout Suite

Physical Verification (DRC, LVS, PEX): Calibre

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Conclusion

The RF front-end transmitter was designed and simulated using Cadence Virtuoso.

The system meets Bluetooth 2.4 GHz ISM band specifications.

Future work includes receiver design and complete transceiver integration.

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Bibliography

[1] T. L. Vivek, ”Analog front end design and layout of Bluetooth transmitter,” [Link]. thesis, Dept. Elect.
Eng., Indian Institute of Technology Madras, Chennai, India, June 2015.
[2] B. Razavi, “RF transmitter architectures and circuits,” Proc. IEEE Custom Integrated Circuits, no. 11, pp.
197–204, Nov. 1999.
[3] H. Zarei, “An analysis of voltage-driven passive-mixer based SAW-less transmitters,” Circuits and Systems
for Communications (ECCSC), no. 3, pp. 177–180, Oct. 2010.
[4] K. Lee and B. Razavi, “Design of high-speed, low-power frequency dividers and phase-locked loops in deep
submicron CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, no. 1, pp. 101–109, Jan. 1995.
[5] D. Miyashita, H. Ishikuro, T. Shimada, T. Tanzawa, S. Kousai, H. Kobayashi, H. Majima, K. Agawa, M.
Hamada, and F. Hatori, “A low-IF CMOS single-chip Bluetooth EDR transmitter with digital I/Q mismatch
trimming circuit,” VLSI Circuits, pp. 298–300, 2005.

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Bibliography (continued)

[6] W. Si, D. Weber, S. Abdollahi-Alibeik, M. Lee, R. Chang, H. Dogan, H. Gan, Y. Rajavi, S. Luschas, S.
Ozgur, P. Husted, and M. Zargari, “A Single-Chip CMOS Bluetooth v2.1 Radio SoC,” IEEE Journal of
Solid-State Circuits, vol. 43, pp. 2896–2904, 2008.
[7] W.-Y. Hu, J.-W. Lin, K.-C. Tien, Y.-H. Hsieh, C.-L. Chen, H.-T. Tso, Y.-S. Shih, S.-C. Hu, and S.-J. Chen,
“A 0.18–µm CMOS RF transceiver with self-detection and calibration functions for Bluetooth v2.1 + EDR
applications,” IEEE Trans. Microwave Theory Tech., vol. 58, pp. 1367–1374, 2010.
[8] M. Ashida, H. Majima, Y. Yoshihara, M. Nozawa, S. Oda, Y. Suzuki, J. Deguchi, H. Kobayashi, S. Kousai,
R. Fujimoto, S. Ishizuka, T. Terada, S. Kawaguchi, Y. Unekawa, and M. Hamada, “A 65nm CMOS, 1.5-mm
Bluetooth transceiver with integrated antenna filter for co-existence with a WCDMA transmitter,” in Proc.
Solid-State Circuits Conf. (A-SSCC), no. 12, pp. 81–84, Dec. 2012.
[9] T. M. Wang, P. Jiang, and J. Zhou, “A low-noise WCDMA transmitter with 25%-duty-cycle LO generator in
65nm CMOS,” in Proc. IEEE 9th Int. Conf. ASIC (ASICON), pp. 1034–1037, Oct. 2011.

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Thank You!