Digital System Slides
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goodboy1292004Digital System Slides
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goodboy1292004EE 224 - Digital Systems
Course Instructor: Dr. Nagaveni S
Email: [email protected]
Note: The information provided in the slides are taken form text/ref. books Digital Electronics (including Mano &
Ciletti), and various other resources from internet, for teaching/academic use only.
Course Content
▪ Introduction to Digital Systems
▪ Number systems and Logic:
▪ Number Systems
▪ Different Codes
▪ Boolean logic
▪ Basic gates, truth tables
▪ Introduction to Logic families: TTL, CMOS etc.
▪ Boolean Algebra:
▪ Laws of Boolean Algebra
▪ Logic minimization using K-maps
▪ Combinational Logic Circuits: Adders, Subtractors, Multipliers, MSI components like Comparators,
Decoders, Encoders, MUXs, DEMUXs
▪ Sequential circuits: Latches, Flipflops, Analysis of clocked sequential circuits, Registers and Counters
(Synchronous and Asynchronous), State Machines
▪ Introduction to Hardware Description Languages
▪ Array based logic elements: Memory, PLA, PLD, FPGA
▪ Special Topics: Asynchronous State machines, Testing and Verification of Digital Systems
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Text/Reference Books
▪ Text book:
▪ M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
▪ Reference books:
▪ J. F. Wakerly: Digital Design, Principles and Practices,4th Edition, Pearson
Education, 2005.
▪ Ronald J. Tocci; Digital System, Principles and Applications, 10th Edition,
Pearson, 2009.
▪ H. Taub and D. Schilling; Digital Integrated Electronics, McGraw Hill, 1977.
▪ Charles H. Roth; Digital Systems Design using VHDL, Thomson Learning, 1998.
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Tentative evaluation pattern
Evaluation Components for Theory
S. Evaluation Component Weightage Date
No
th
1. Quiz - 1 10% 6 Feb. 2024 (in the
special slot)
2. Midsem 25% TBA
3. Assignment 10% --
nd
4. Quiz - 2 10% 2 Apr. 2024 (in the
class hours)
5. Class Participation 5% Continuous
6. End-Sem 40% TBA
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Analog vs. Digital
Before Electronics Era After Electronics Revolution
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Analog vs. Digital Systems
There are two way of representing the numerical value of quantities:
▪ Analog
▪ Digital
▪ Analog vs. Digital Electronics
▪ Advantage of Digital Electronics
▪ Designing of Digital System
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Analog representation
▪ A quantity is represented by a voltage, current or meter movement
that is proportional to the value of that quantity
Example :
▪ Automobile speedometer
▪ Audio microphone
▪ Analog quantities can vary over a continuous range of values
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Digital representation
▪ The quantities are represented not by proportional quantities but by symbols
called digits (after analogue to digital conversion)
Example :
▪ Digital speedometer, digital watch
▪ It provides the time of day in the form of decimal digits which represent hours
and minutes (and sometimes seconds)
▪ The digital representation of the time of day changes in discrete steps
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Advantage of Digital Electronics
▪ Digital systems are easier to design as circuits used are only switching circuits having
only HIGH and LOW range.
▪ Information storage is easy.
▪ Accuracy and precision are greater.
▪ Operation can be programmed.
▪ Digital circuits are less affected by noise, as the spurious fluctuation in voltage
(noise) are not as critical in digital systems became the exact value of a voltage is not
important.
Limitation of Digital Techniques
▪ The real world is mainly analog
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Impact of Noise on Analog and Digital Systems
▪ Digital circuits are less affected by noise, the spurious fluctuation in voltage (noise)
are not as critical in digital systems
▪ It is easy to detect the Digital signal as it is in 1 or 0 (binary or discrete values) as the
signal strength is not much deteriorated by the noise
▪ Whereas, it is difficult to detect the Analog signal in the presence of Nosie as the signal
strength is highly deteriorated by the noise
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Digital Number System
▪ Many number systems are in use in digital technology
▪ The most common are
▪ Binary [Base (B) = Radix (R) = 2], Number of unique digits – 2 (0 & 1)
▪ Decimal [B = R = 10], Number of unique digits – 10 (0 to 9)
▪ Octal [B = R = 8], Number of unique digits – 8 (0 to 7)
▪ Hexadecimal [B = R = 16], Number of unique digits – 16 (0 to 9 & A to F)
▪ Base (B) or Radix (R) is defined as how many unique digits present in that
number system.
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Digital Number System
Decimal [B = R = 10], Octal [B = R = 8], Binary [Base (B) = Radix (R) = 2],
Number of unique digits – 10 Number of unique digits – 8 Number of unique digits – 2
(0 to 9) (0 to 7) (0 & 1)
…… …… 0 10 100 1000
0 10 20 … 90 100 0 10 20 … 70 100 1 11 101 1001
1 11 21 91 101 1 11 21 71 101 110 1010
2 12 22 92 102 2 12 22 72 102 111 1011
3 13 23 93 103 3 13 23 73 103 1100
4 14 24 94 104 4 14 24 74 104 1101
5 15 25 95 105 5 15 25 75 105 1110
6 16 26 96 106 6 16 26 76 106 1111
7 17 27 97 107 7 17 27 77 107
8 18 28 98 108
9 19 29 99 109
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Digital Number System
Hexadecimal [B = R = 16],
Number of unique digits – 16 (0 to 9 & A to F)
0 10 . . 90 A0 . F0 100
1 11 . . 91 A1 . F1 101
2 12 . . 92 A2 . F2 103
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
9 19 . . 99 A9 . F9 109
A 1A . . 9A AA . FA 10A
B 1B . . 9B AB . FB 10B
C 1C . . 9C AC . FC 10C
D 1D . . 9D AD . FD 10D
E 1E . . 9E AE . FE 10E
F 1F . . 9F AF . FF 10F
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Numbers with Different Bases
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Binary numbers
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Number system conversion
▪ Exercise: Convert any number system to Decimal
▪ Binary to Decimal conversion
▪ A Binary system has a base 2 and uses only two symbols 0, 1 to represent all
the numbers
= ( ? )10
▪ What decimal number does it represent?
= (13)10
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Number system conversion
▪ Exercise: Convert any number system to Decimal
▪ Octal to Decimal
▪ An octal number system has a base 8 and uses symbols (0,1,2,3,4,5,6,7)
= ( ? )10
▪ What decimal number does it represent?
= (1033)10
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Number system conversion
▪ Every number system is associated with a base or radix
▪ A positional notation is commonly used to express numbers
▪ The decimal system has a base of 10 and uses symbols (0,1,2,3,4,5,6,7,8,9)
to represent numbers
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Number system conversion
▪ Exercise: Binary to Decimal conversion
(1101.1001)2 = ( ? )10
▪ What decimal number does it represent?
(1101.1001)₂ = (1 × 2³) + (1 × 2²) + (0 × 2¹) + (1 × 2⁰) + (1 × 2⁻¹) + (0 × 2⁻²) + (0 × 2⁻³) + (1 × 2⁻⁴)
(1101.1001)2 = (13.5625)10
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Hexadecimal to Decimal Conversion
▪ Practice problem
(C7.5B)16 = ( ? )10
▪ A hexadecimal system has a base of 16
(C7.5B)₁₆ = (C × 16¹) + (7 × 16⁰) + (5 × 16⁻¹) + (B × 16⁻²)
(C7.5B)₁₆ = (12 × 16¹) + (7 × 16⁰) + (5 × 16⁻¹) + (11 × 16⁻²)
(C7.5B)₁₆ = (199.355)₁₀
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Number system conversion
▪ Home work: (52.34)6 = ( ? )10
(52.34)6 = (5 × 6¹) + (2 × 6⁰) + (3 × 6⁻¹) + (4 × 6⁻²)
3 4
(52.34)6 = (5 × 6) + (2 × 1) + +
6 36
(52.34)6 = (32.611)10
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Decimal to Octal Conversion
▪ Practice problem: Convert following number from Decimal to Octal
(139.2)10 = ( ? )8
▪ Method of successive division by 8 ▪ Method of successive multiplication by 8
Divisor Dividend Remainder 0.2x8 1.6
8 139 3 0.6x8 4.8
8 17 1 0.8x8 6.4
2 0.4x8 3.2
0.2x8 1.6
(139)10 = (213)8 (0.2)10 = (0.14631)8
(139.2)10 = (213.14631)8
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Decimal to Radix 5 oriented Number System
▪ Practice problem: Convert following number from Decimal to a number system
with Radix = 5
(139.2)10 = ( ? )5
▪ Method of successive division by 5 ▪ Method of successive multiplication by 5
Divisor Dividend Remainder 0.2 x 5 1.0
5 139 4 0.0 x 5 0.0
5 27 2
5 5 0 (0.2)10 = (0.10)5
1
(139)10 = (1024)5
(139.2)10 = (1024.10)5
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Decimal to Radix 6 oriented Number System
▪ Home work: Convert following number from Decimal to a number system with
Radix = 6
(139.2)10 = ( ? )6
▪ Method of successive division by 6 ▪ Method of successive multiplication by 6
Divisor Dividend Remainder 0.2 x 6 1.2
6 139 1 0.2 x 6 1.2
6 23 5
3 (0.2)10 = (0.11)6
(139)10 = (351)6
(139.2)10 = (351.11)6
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Decimal to Binary Number System
▪ Home work: Convert following number from Decimal to Binary
(139.2)10 = ( ? )2
Any to Any Number System Conversion
▪ Practice problem:
(342.41)5 = ( ? )7
(342.41)5 → ( ? )10 → ( ? )7
(342.41)5 = (3 × 52) + (4 × 51) + (2 × 50) + (4 × 5-1) + (1 × 5-2)
(342.41)5 → (97.84)10 → ( ? )7
▪ Method of successive division by 7 ▪ Method of successive multiplication by 7
Divisor Dividend Remainder 0.84 x 7 5 . 88
7 97 6 0.88 x 7 6 . 16
7 13 6 0.16 x 7 1 . 12
1
(0.87)10 = (0.561)7
(97)10 = (166)7
(342.41)5 = (166.561)7
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Converting Binary to Hex and Hex to Binary
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Binary to Hexadecimal Conversion
▪ Practice problem: (10011.11011)2 = ( ? )16
▪ Make a group of four binary digits
(0001 0011.1101 1000)2 = (13.D8)16
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Binary to Octal Conversion
▪ Practice problem: (1011.1001)2 = ( ? )8
▪ Make a group of three binary digits
(001 011.100 100)2 = (13.44)8
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Octal to Binary Conversion
▪ Home work: (73.52)8 = ( ? )2
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Hexadecimal to Binary Conversion
▪ Home work: (B8.CE)16 = ( ? )2
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Hexadecimal to Binary Conversion
▪ Home work: Hexa Decimal value 0.25 = ( ? )2
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Octal to Hexadecimal Conversion
▪ Practice problem: (657)8 = ( ? )16
(657)8 → ( ? )2 → ( ? )16
▪ Make a group of three binary digits
(657)8 = (110 101 111)2
(110101111)2 → ( ? )16
(0001 1010 1111)2 → (1AF)16
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Find the number of 1’s in the given Binary representation
▪ How many number of 1’s are present in the given Binary representation?
(3 × 4096) + (15 × 256) + (5 × 16) + 3
(3 × 163) + (15 × 162) + (5 × 161) + (3 × 160)
(3F53)16
(3F53)16 → ( ? )2 → (0011 1111 0101 0011)2
Ans. = 10
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Home work
▪ How many number of 1’s are present in the Binary representation?
(163 × 9) + (162 × 7) + (161 × 5) + 3
(9753)16
(9753)16 → ( ? )2 → (1001 0111 0101 0011)2
Ans. = 9
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Find out the value of the Radix “r”
▪ Practice problem: (224)𝑟 = (13)𝑟
▪ The value of the radix “r” is
▪ A) 10
▪ B) 8 2𝑟 2 + 2𝑟1 + 4𝑟 0 = 1𝑟1 + 3𝑟 0
▪ C) 5
▪ D) 6 2𝑟 2 + 2𝑟 + 4 = 𝑟 + 3
2𝑟 2 + 2𝑟 + 4 = (𝑟 + 3)2
2𝑟 2 + 2𝑟 + 4 = 𝑟 2 + 6𝑟 + 9
𝒓 = −𝟏 𝒂𝒏𝒅 𝟓 Ans. = 5
▪ Any number system can not have a negative radix “r”.
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Find out the number of possible solutions
(43)𝑋 = (𝑌3)8 (43)𝑋 = (𝑌3)8
X Y
(4 × X1) + (3 × X0)=(Y × 81) + (3 × 80) Min (X) = 5 2 1
4 2
6 3
4X + 3 = 8Y + 3 8 4
10 5
12 6
X = 2Y Max (X) = 14 14 7
16 8
18 9
Number of possible solutions = 5
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Home work
▪ Find out the number of possible solutions
(123)5 = (𝑋8)𝑌
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Assignment
▪ Find out the base (radix) of the number system such that the following equation
holds true.
312
= 13.1
20
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Binary Addition/Subtraction
▪ Practice problem:
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Complement of a number
▪ 9’s complement of n‐digit number x is 10n ‐1 ‐x
▪ 10’s complement of n‐digit number x is 10n ‐x
▪ 9’s complement of 123 ?
9’s complement of 123 = (103 – 1 – 123)
9’s complement of 123 = 999 – 123
9’s complement of 123 = 876
10's complement of 123 = 9's complement of 123+1= 877
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Complement of a Binary number
▪ 1’s complement of n‐bit number x is 2n ‐1 ‐x
▪ 2’s complement of n‐bit number x is 2n ‐x
▪ 1’s complement of 1101100 ?
1’s complement of 1101100 = (27 – 1 – 1101100)
1’s complement of 1101100 = 0010011
1’s complement is simply obtained by flipping a bit (changing 1 to 0 and 0 to 1)
2's complement of 1101100 = 1's complement of 1101100 +1= 0010100
2's complement of 1101100 = 0010100
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Signed Binary Numbers
▪ In ordinary arithmetic, a negative number is indicated by a minus sign and a positive
number by a plus sign. Because of hardware limitations, computers must represent
everything with binary digits. It is customary to represent the sign with a bit placed in
the leftmost position of the number. The convention is to make the sign bit 0 for
positive and 1 for negative.
▪ If the binary number is signed, then the leftmost bit represents the sign and the rest
of the bits represent the number. If the binary number is assumed to be unsigned,
then the leftmost bit is the most significant bit (MSB) of the number.
Unsigned MSB Rest Combined Signed Sign ( 0 -> Positive, Rest bits Combined
Number bits Binary Number 1-> Negative) Binary
representation representation
9 0 1001 01001 +9 0 1001 01001
25 1 1001 11001 -9 1 1001 11001
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Signed Binary Numbers
▪ The representation of the signed numbers in the last example is referred to as the signed‐magnitude
convention. In this notation, the number consists of a magnitude and a symbol ( + or - ) or a bit (0 or
1) indicating the sign. This is the representation of signed numbers used in ordinary arithmetic. When
arithmetic operations are implemented in a computer, it is more convenient to use a different system,
referred to as the signed complement system, for representing negative numbers. In this system, a
negative number is indicated by its complement. Whereas the signed‐magnitude system negates a
number by changing its sign, the signed‐complement system negates a number by taking its
complement. Since positive numbers always start with 0 (plus) in the leftmost position, the
complement will always start with a 1, indicating a negative number. The signed‐complement system
can use either the 1’s or the 2’s complement, but the 2’s complement is the most common.
▪ As an example, consider the number 9, represented in binary with eight bits. +9 is represented with a
sign bit of 0 in the leftmost position, followed by the binary equivalent of 9, which gives 00001001.
Note that all eight bits must have a value; therefore, 0’s are inserted following the sign bit up to the
first 1. Although there is only one way to represent +9, there are three different ways to represent -9
with eight bits:
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Signed Binary Numbers
Signed‐magnitude representation: 10001001
Signed‐1’s‐complement representation: 11110110
Signed‐2’s‐complement representation: 11110111
▪ The signed‐magnitude system is used in ordinary arithmetic, but is awkward when
employed in computer arithmetic because of the separate handling of the sign and
the magnitude. Therefore, the signed‐complement system is normally used.
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Signed Binary Numbers
More number of bits are
required as the left most
bit is reserved for a sign
representation
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Advantages of using 2’s complement
Can we carry out Y = X1 – X2 using such an adder?
▪ Computers need only one common hardware circuit to handle both
types of arithmetic.
▪ This consideration has resulted in the signed‐complement system being used
in virtually all arithmetic units of computer systems.
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Advantages of using 2’s complement
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Adder as a subtractor
▪ Practice problem: 10-6=4
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Adder as a subtractor
▪ Practice problem: 6-10=-4
▪ It makes sense to use adder as a subtractor as well provided additional circuit required for carrying
out 2’s complement is simple
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Home work
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Codes
▪ When numbers, letters or words are represented by a special group of
symbols, we say that they are being encoded and the group of
symbols is called code.
▪ Binary‐ Coded‐ Decimal Code (BCD)
▪ If each digit of a decimal number is represented by its binary
equivalent, the result is a code called binary coded‐decimal.
▪ Since a decimal digit can be as large as 9, 4 bits are required to code
each digit.
▪ Ex. 874 = 1000 0111 0100 (BCD)
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Different Binary Codes for the Decimal Digits
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Gray code
▪ It belongs to a class of codes called
minimum‐change codes, in which only one bit in the
code groups changes when going from one stage to
the next. The Gray code is an unweighted code.
▪ So, this code is not suited for arithmetic operation
but finds application in input/output devices and
some types of Analog to Digital Converters (ADCs).
RJEs: Remote job entry points M. Moris Mano; Digital Design, 6th Edition, Pearson, 2018.
Alphanumeric Codes
An alphanumeric code
represents all of the various
characters and functions that
are found in a standard
computer keyboard.
ASCII Code: The most
widely used alphanumeric
code, the American standard
code for Information
Interchange as is used in
most micro computers and
minicomputers and in many
mainframes. The ASCII code
is a 7 bit code and so it has
27 =128 possible code
groups.
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Alphanumeric Codes
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Digital Electronics Fundamentals
Boolean Algebra
▪ Algebra on Binary numbers Signal levels for binary logic values
▪ A variable x can take two values {0,1}
5V
4V
2V
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Logic families: noise margin
HI state noise margin:
VNH = VOH(min) – VIH(min)
LO state noise margin:
VNL = VIL(max) – VOL(max)
VNH
Noise margin:
VN = min(VNH,VNL)
VNL
58
Logic Gates
▪ Logic gate is the minimal building block of any digital system
▪ Elementary/Basic Gates:
▪ AND
▪ OR
▪ NOT
▪ Universal Gates:
▪ NAND
▪ NOR
▪ Special purpose gates:
▪ XOR
▪ XNOR
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Basic Gates
▪ NOT Gate:
▪ It is the only Gate that has a single input.
Truth Table:
▪ NOT Gate is a logic gate in which the output is always at the
complement logic of the input.
▪ The bubble in the symbol represents the inversion or complement;
that is why it is also called an inverter.
NOT Gate / Inverter vs. Buffer
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Nmos and Pmos
61
MOSFET Symbols
62
CMOS NOT gate
63
Universal Gates
▪ NADN gate
NAND = AND + NOT
▪ NAND gate is a logic gate whose
output is at a logic high when any of
the inputs is at a logic low
▪ NAND gate is a logic gate whose
output is at logic low only when all the Truth Table:
inputs are at logic high
X1 X2 Output
0 0 1
0 1 1
1 0 1
1 1 0
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NAND Gate
65
Universal Gates
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Universal Gates
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Elementary/Basic Gates
AND Gate:
▪ AND gate is a logic gate in which output is at logic low Truth Table:
(“0”) when any of the input is at logic low (“0”)
▪ AND gate is a logic gate whose output is at logic high
(“1”) only when all the inputs are at logic high (“1”)
AND Gate with more than 2 inputs
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AND gate
69
Universal Gates
▪ NOR gate
NOR = OR + NOT
▪ NOR gate is a logic gate whose
output is at a logic high only when
both the inputs are at a logic low
▪ NOR gate is a logic gate whose
output is at logic low when any of the
the inputs is at logic high Truth Table:
X1 X2 Output
0 0 1
0 1 0
1 0 0
1 1 0
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71
Elementary/Basic Gates
OR Gate:
▪ OR gate is a logic gate in which output is at ▪ Y is 1 if either x1 and x2 is 1. Or y= 0 if
logic low (“0”) only when all the inputs are at and only if both variables are zero.
logic low (“0”) Truth Table:
▪ OR gate is a logic gate whose output is at logic
high (“1”) when any of the inputs is at logic high
(“1”)
OR Gate with more than 2 inputs
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OR gate
73
Special purpose gates
▪ XOR gate Truth Table:
Inequality
Detector
Inequality Detector: Whenever odd number of 1’s is in the inputs,
output becomes 1. Therefore, it is also called odd no. of 1’s detector
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XOR gate
75
76
Special purpose gates
▪ XNOR gate
Truth Table:
X1 X2 Output
0 0 1
𝑦 = 𝑥1 ⊙ 𝑥2 𝑦 = 𝑥1 ⊙ 𝑥2 0 1 0
1 0 0
1 1 1
Equality Detector: XNOR gate detects the equal
▪ Y is 1 if only both variables are either 0 or 1 inputs by producing the logic high at the output.
Therefore, it is called equality detector.
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Laws of Boolean Algebra
AND Lows OR Lows NOT Lows
0+0=0 0*0=0 A*0=0 A+0=A 𝐼𝑓 𝐴 = 0 ⇒ 𝐴ҧ = 1
0+1=1 0*1=0 A*1=A A+1=1
1+0=1 1*0=0 A*A=A A+A=A 𝐼𝑓 𝐴 = 1 ⇒ 𝐴ҧ = 0
1+1=1 1*1=1 𝐴 + 𝐴ҧ =1
𝐴 ∗ 𝐴ҧ = 0
𝐴ҧ = 𝐴
0ത = 1 1ത = 0
Associative Laws
Commutative Laws
𝐴 + 𝐵 + 𝐶 = 𝐴 + (𝐵 + 𝐶)
A+B=B+A 𝐴 + 𝐵 + 𝐶 = 𝐴 + (𝐵 + 𝐶)
A B
=
B A
A*B=B*A 𝐴𝐵 𝐶 = 𝐴(𝐵𝐶)
𝐴+𝐵 =𝐵+𝐴 𝐴⊕𝐵 =𝐵⊕𝐴 𝐴 ⊕ 𝐵 ⊕ 𝐶 = 𝐴 ⊕ (𝐵 ⊕ 𝐶)
𝐴𝐵 = 𝐵𝐴 𝐴⊙𝐵 =𝐵⊙𝐴 𝐴 ⊙ 𝐵 ⊙ 𝐶 = 𝐴 ⊙ (𝐵 ⊙ 𝐶)
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Laws of Boolean Algebra
▪ Associative Law is not valid for the
NAND Gate with more than two inputs
▪ Similar, associative Law is not valid for
the NOR Gate with more than two
inputs
▪ Associative Law is valid for AND, OR,
XOR, XNOR, but associative low is not
valid for universal gates
▪ Universal Gates (NAND and NOR) do
not follow the associative low
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Laws of Boolean Algebra
Distributive Law Absorption Law
▪ Highly used in minimizing a Boolean function 𝐴 + 𝐴𝐵 = 𝐴
𝐴(𝐴 + 𝐵) = 𝐴
𝐴 𝐵 + 𝐶 = 𝐴𝐵 + 𝐴𝐶
𝐴 + 𝐵𝐶 = (𝐴 + 𝐵)(𝐴 + 𝐶)
𝑝 + 𝑞𝑟 = (𝑝 + 𝑞)(𝑝 + 𝑟)
𝑤 + 𝑥𝑦𝑧 = (𝑤 + 𝑥)(𝑤 + 𝑦)(𝑤 + 𝑧)
𝐴 + 𝐵 𝐴 + 𝐶 = 𝐴 + 𝐵𝐶
𝑥 + 𝑦 𝑥 + 𝑧 = 𝑥 + 𝑦𝑧
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Boolean Algebra
Summary: Lows of Boolean Algebra
Basic Postulates
Basic Theorems
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Proving the theorems
Proof
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Proving the theorems
Proof
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DE Morgan's theorem
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Exercise
▪ Simplify the following Boolean expression
▪ Apply the DE Morgan's theorem
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Obtaining the Boolean expression from a Truth Table
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Obtaining the Boolean expression from a Truth Table
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Obtaining the Boolean expression from a Truth Table
▪ Instead of writing expressions as sum of products (SOP) that make y equal to 1, we can also write
expressions using product of sums (POS) that make y equal to 0.
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Obtaining the Boolean expression from a Truth Table
Sum of Product (SOP)
Product of Sum (POS)
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Universality of NAND and NOR gates
▪ We can design a given Boolean function of any complexity with the
combination of AND, OR, and NOT gates, so these gates are called basic
gates.
▪ Now, all three basic gates can be designed using only a NAND gate.
▪ Therefore, we can conclude that it is possible to design a given Boolean
function of any complexity using only NAND gates.
▪ Hence, the NAND gate is called the universal gate.
▪ Note: All the above discussion for a NAND gate is also valid for a NOR gate.
Therefore, NAND and NOR gates are called universal gates.
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Exercise - Using NAND Gates
▪ Design the following functions using minimum number of 2 input NAND gates
1) 𝑓 = 𝐴ҧ (NOT)
▪ Min. No. of required 2 input NAND gates = Ans. = 1
2) 𝑓 = 𝐴𝐵 (AND)
▪ Min. No. of required 2 input NAND gates = Ans. = 2
3) 𝑓 = 𝐴 + 𝐵 (OR)
▪ Min. No. of required 2 input NAND gates = Ans. = 3
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Exercise - Using NAND Gates
▪ Design the following functions using minimum number of 2 input NAND gates
4) 𝑓 = 𝐴𝐵 + 𝐶𝐷
▪ Min. No. of required 2 input NAND gates = Ans. = 3
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Exercise - Using NAND Gates
▪ Design the following functions using minimum number of 2 input NAND gates
5) 𝑓 = 𝐴𝐵 + 𝐶
▪ Min. No. of required 2 input NAND gates = Ans. = 3
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Exercise - Using NAND Gates
▪ Whenever there is a following generic pattern in the Boolean function, the minimum
number of required two input NAND gates is 3.
▪ Therefore, we can identify the minimum number of required gates just by looking at
the Boolean function without drawing the logic design.
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Exercise - Using NAND Gates
▪ Design the following functions using minimum number of 2 input NAND gates
6) 𝑓 = 𝐴𝐵 + 𝐶𝐷 + 𝐸𝐹
In correct answer (As it is directed to design with 2 input
NAND gates, we can not use 3 input NAND gate.)
▪ Min. No. of required 2 input NAND gates = Ans. = 4
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Exercise - Using NAND Gates
▪ Design the following functions using minimum number of 2 input NAND gates
6) 𝑓 = 𝐴𝐵 + 𝐶𝐷 + 𝐸𝐹 ▪ Can you Identify the no. of required 2 input NAND
gates just by looking at the function?
▪ Min. No. of required 2 input NAND gates = Ans. = 6
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Homework
▪ Design the following function using minimum number of 2 input NAND gates
7) 𝑓 = 𝐴𝐵 + 𝐶𝐷 + 𝐸𝐹 + 𝐷𝐴
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Exercise - Using NAND Gates
▪ Design the following function using minimum number of 2 input NAND gates
8) 𝑓 = 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐷 + 𝐷𝐴
▪ Identify the minimum number of required gates just by looking at the Boolean function
without drawing the logic design.
▪ When the variables are repeating, simplify the Boolean expression.
In correct answer (Suboptimal- No. of NAND gates can be
𝑓 = 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐷 + 𝐷𝐴 optimized or reduced further)
𝑓 = 𝐵(𝐴 + 𝐶) + 𝐷(𝐴 + C)
𝑓 = (𝐴 + 𝐶)(𝐵 + D)
𝑓 = 𝐴𝐴 + 𝐶𝐶 𝐵𝐵 + DD = 𝑥𝑦
3-NANDs 3-NANDs 2-NANDs
Total = 8 NAND gates
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Correct answer
𝑓 = 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐷 + 𝐷𝐴
𝑓 = 𝐵(𝐴 + 𝐶) + 𝐷(𝐴 + C)
3-NANDs 0-NANDs
Assume 𝑥 = (𝐴 + 𝐶)
𝑓 = 𝐵𝑥 + 𝐷𝑥
3-NANDs
Total = 6 NAND gates
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Exercise - Using NAND Gates
ത
8) 𝑓 = 𝐴𝐵𝐶
Total = 5 NAND gates
Total = 5 NAND gates
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Home work
9) 𝑓 = 𝐴𝐵ത + 𝐶
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Exercise - Using NOR Gates
▪ Design the following functions using minimum number of 2 input NOR gates
1) 𝑓 = 𝐴ҧ (NOT)
▪ Min. No. of required 2 input NOR gates = Ans. = 1
2) 𝑓 = 𝐴𝐵 (AND)
▪ Min. No. of required 2 input NOR gates = Ans. = 3
3) 𝑓 = 𝐴 + 𝐵 (OR)
▪ Min. No. of required 2 input NOR gates = Ans. = 2
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Bubbled AND Gate
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Exercise - Using NOR Gates
▪ Design the following functions using minimum number of 2 input NOR gates
1) 𝑓 = 𝐴ҧ (NOT) → 1 (NAND) 1) 𝑓 = 𝐴ҧ (NOT) → 1 (NOR)
2) 𝑓 = 𝐴𝐵 (AND) → 2 (NAND) 2) 𝑓 = 𝐴𝐵 (AND) → 3 (NOR)
3) 𝑓 = 𝐴𝐵 + 𝐶𝐷 → 3 (NAND) 3) 𝑓 = (𝐴 + 𝐵)(𝐶 + 𝐷) → 3 (NOR)
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Home work exercise - Using NOR Gates
▪ Design the following functions using minimum number of 2 input NOR gates
𝑓 = 𝐴(𝐵 + 𝐶)
𝑓 = (𝐴 + 𝐴)(𝐵 + 𝐶)
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Exercise - Using NOR Gates
▪ Design the following functions using minimum number of 2 input NOR gates
𝑓 = (𝐴 + 𝐵)(𝐶 + 𝐷)(𝐸 + 𝐹)
▪ Identify the minimum number of required gates just by looking at the Boolean function
without drawing the logic design.
𝑓 = (𝐴 + 𝐵)(𝐶 + 𝐷)(𝐸 + 𝐹)
3-NORs
Assume 𝑥 = (𝐴 + 𝐵)(𝐶 + 𝐷)
𝑓 = 𝑥(𝐸 + 𝐹)
𝑓 = (𝑥 + 𝑥)(𝐸 + 𝐹)
3-NORs Ans. Total = 6 NOR gates
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Homework
▪ Design the following function using minimum number of 2 input NOR gates
𝑓 = 𝐴𝐷 + 𝐵𝐸 + 𝐶𝐷 + 𝐵𝐷 + 𝐴𝐸 + 𝐶𝐸
Ans. Total = 5 NOR gates
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Homework
▪ Design the following function using minimum number of 2 input NOR gates
𝑓 = (𝑎 + 𝑏)(𝑐 + 𝑑)ҧ
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Exercise
▪ Design the following function using 2 input gates of only one type
𝑓 = 𝐴 + 𝐵𝐶
Solution-2
Solution-1 𝑓 = 𝐴 + 𝐵𝐶
𝑓 = 𝐴𝐴 + 𝐵𝐶 Apply the distributive law
3 NANDs 𝑓 = (𝐴 + 𝐵)(𝐴 + 𝐶)
3 NORs
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Exercise
Identify the gates g1 and g2 𝑓 = 𝐴𝐵 + 𝐶ҧ 𝐷
ഥ
A) NOR, OR
B) NAND, OR NOR 𝐴ҧ + 𝐵ത = 𝐴ҧ𝐵ത = 𝐴𝐵
C) OR, NAND
D) AND, NAND
𝐴𝐵
OR
𝐴𝐵 + 𝐶ҧ 𝐷
ഥ
𝐶 + 𝐷 = 𝐶ҧ 𝐷
ഥ
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-Ve Logic Digital System
Digital System
+Ve Logic Digital -Ve Logic
System Digital System
Logic Low → “0” Logic Low → “1”
Logic high → “1” Logic high → “0”
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Basic Gates
"+Ve Logic AND Gate" "-Ve Logic AND Gate"
X1 X2 Output X1 X2 Output
0 0 0 1 1 1
0 1 0 1 0 1
1 0 0 0 1 1
1 1 1 0 0 0
+Ve Logic AND Gate ≡ -Ve Logic OR Gate
+Ve Logic OR Gate ≡ -Ve Logic AND Gate
"+Ve Logic OR Gate" "-Ve Logic OR Gate"
X1 X2 Output X1 X2 Output
0 0 0 1 1 1
0 1 1 1 0 0
1 0 1 0 1 0
1 1 1 0 0 0
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Implementing gates using Switches
A B Output
0 0 0
0 1 0
1 0 0
1 1 1
AND Gate
• Switches are connected in the series
• Switches are also connected in the series with an LED or Bulb
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Implementing gates using Switches
A B Output
0 0 0
0 1 1
1 0 1
1 1 1
OR Gate
• Switches are connected in the parallel; however, the parallel combination of the
switches is in the series with an LED/Bulb.
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Implementing gates using Switches
NOT Gate
• Switch is connected in parallel combination with an LED/Bulb.
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Implementing gates using Switches
A B Output
0 0 1
0 1 1
1 0 1
1 1 0
NAND = AND + NOT
• Switches are connected in the series; however, the series combination of the
switches is in the parallel with an LED/Bulb.
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Implementing gates using Switches
A B Output
0 0 1
0 1 0
1 0 0
1 1 0
NAND = OR + NOT
• Switches are connected in the parallel combination; moreover, they are aslo in the
parallel with an LED/Bulb.
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Exercise
• Find out the output function “Y”.
ABC
Y = ABC+DE
DE
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Exercise
• Find out the output function “Y”.
Switches are in the parallel with an
LED/Bulb
A+B
= 𝐴+𝐵 𝐶+𝐷 𝐸
C+D
Series combination of three switches gives (A+C)(C+D)E
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Exercise
• To achieve X = 1, what are the inputs A, B, & C?
• a) 1, 0, 1
• b) 0, 0, 1
• c) 1, 1, 1 Ans. d) 0, 1, 1
• d) 0, 1, 1
0 1
1
1
1
1 1
1
X=1
=1 1
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Homework
• To achieve F = 1, what are the inputs A, B, & C?
• a) 1, 1, 0
• b) 1, 0, 0
• c) 0, 1, 0
• d) 0, 0, 1
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Homework Exercise - Match the following
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Homework
• Which one of the following does not represent the exclusive NOR of x and y?
A) 𝑥𝑦 ⊕ 𝑥 ′ 𝑦 ′
B) 𝑥 ⊕ 𝑦′
C) 𝑥′ ⊕ 𝑦
D) 𝑥′ ⊕ 𝑦′
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Exercise - Special purpose gate (XOR)
• Find the output Y for the cascaded stage of 20 XOR gates.
𝑋ത 1 𝑋ത =1
19th XOR 20th XOR
1st XOR 2nd XOR
Ans. Y = 1
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Homework exercise - Special purpose gate (XOR)
• Find the output Y for the cascaded stage of 20 XNOR gates.
Hint
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Special case - XOR
• Special case for minimum number of 2 inputs NAND gates to design XOR
𝐴⊕𝐵
1-NANDs 1-NANDs
ҧ + 𝐴𝐵ത
𝐴 ⊕ 𝐵 = 𝐴𝐵
3-NANDs
Total = 5-NANDs
In correct answer (Suboptimal- No.
of NAND gates can be optimized or Total = 4-NANDs
reduced further)
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Home exercise Special case - XNOR
• Special case for minimum number of 2 inputs NOR gates to design XNOR
𝐴⊙𝐵
Total = 4-NORs
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Exercise
Total = 4-NANDs for
XOR and 5 NANDs
for XNOR
Total = 4-NORs for
XNOR and 5 NORs
for XOR
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COMBINATIONAL LOGIC CIRCUITS
▪ The circuits made up of combination of logic gates/Boolean circuits.
▪ At any time, the logic level at the output depends on the combination of logic
levels present at the inputs.
▪ A combinational circuit has no memory characteristics, so its output depends
only on the current value of its inputs.
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Forms For Logical Expressions
For Logic circuit simplification and design, the logic expression is to be
expressed in two standard forms Sum of Product (SOP)
(1) Sum-of-Products Form
(2) Product-of-Sums Form
Product of Sum (POS)
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Sum-of-Products (SOP)
▪ Each of this expression consists of two or more AND terms that are ORed
together.
▪ Product term Sum-of-Products (SOP)
𝐹1 = 𝐴𝐵𝐶ത
ҧ
𝐹2 = 𝐴𝐵𝐶 ത + ഥ𝐴𝐵𝐶 + 𝐴𝐶ҧ
𝐹 = 𝐴𝐵𝐶
𝐹3 = 𝐴𝐶ҧ
▪ Note :-
▪ (i) The same variable used never appears twice in a product. We can use A.A=A
▪ (ii) One complement sign can not cover more than one variable in a term (e.g.
we can not have 𝐴𝐵𝐶. In that case use De Morgan’s Law)
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Standard Sum-of-Products (SSOP) Form
▪ A Standard SOP Form in which each product term involves all the variables
(Complemented or Un-complemented). Each individual term is referred to as a
minterm.
ത + ഥ𝐴𝐵𝐶 + 𝐴𝐶ҧ
𝐹 = 𝐴𝐵𝐶
▪ Above SOP is not in a Standard (SSOP) form.
▪ Converting the above SOP into a Standard SSOP form.
ത + ഥ𝐴𝐵𝐶 + 𝐴𝐶(𝐵
𝐹 = 𝐴𝐵𝐶 ҧ + 𝐵)
ത
ത + ഥ𝐴𝐵𝐶 + 𝐴𝐵𝐶ҧ + 𝐴𝐵ത 𝐶ҧ
𝐹 = 𝐴𝐵𝐶
Standard/Cononical (SOP)
▪ In SSOP, organize all the variable in the order such as A, B, C, D. (e.g. ACBD in any
minterm is not possible)
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Standard Sum-of-Products (SSOP) Form
ത + ഥ𝐴𝐵𝐶 + 𝐴𝐵𝐶ҧ + 𝐴𝐵ത 𝐶ҧ
𝐹 = 𝐴𝐵𝐶
Standard/Canonical (SOP)
𝐹 = 𝑚5 + 𝑚3 + 𝑚6 + 𝑚4
𝐹 = (5, 3, 6, 4)
𝑚
▪ Arrange in the increasing order such as 1, 2, 3, 4..
𝐹 = (3, 4, 5, 6)
𝑚
▪ We can write down from the SSOP directly, by
converting the minterms in to binary equivalent.
𝐹 = 𝐴𝐵𝐶ത + ഥ𝐴𝐵𝐶 + 𝐴𝐵 𝐶ҧ + 𝐴𝐵ത 𝐶ҧ
𝐹 = (101, 011, 110, 100) = 5, 3, 6, 4 = (3, 4, 5, 6)
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points 𝑚 𝑚
Standard Sum-of-Products (SSOP) Form
ത + ഥ𝐴𝐵𝐶 + 𝐴𝐵𝐶ҧ + 𝐴𝐵ത 𝐶ҧ
𝐹 = 𝐴𝐵𝐶
Standard/Canonical (SOP)
𝐹(𝐴, 𝐵, 𝐶) = (101, 011, 110, 100) = 5, 3, 6, 4 = (3, 4, 5, 6)
𝑚 𝑚 𝑚
LSB – Least Significant Bit
MSB – Most Significant Bit
In correct answer (In SSOP, all the
variable must be in the order such as A,
B, C, D. (e.g. ACBD in any
minterm is not possible)
ത
𝐹 = 𝐵𝐶𝐴 +𝐵𝐶 𝐴ҧ + 𝐵𝐶𝐴
ҧ + 𝐵ത 𝐶𝐴
ҧ
𝐹 = (011, 110, 101, 001) = 3, 6, 5, 1 = (1, 3, 5, 6)
𝑚 𝑚 𝑚
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Standard Sum-of-Products (SSOP) Form
ത + ഥ𝐴𝐵𝐶 + 𝐴𝐶ҧ
𝐹 = 𝐴𝐵𝐶
ത + ഥ𝐴𝐵𝐶 + 𝐴𝐵𝐶ҧ + 𝐴𝐵ത 𝐶ҧ
𝐹 = 𝐴𝐵𝐶
Standard/Canonical (SOP)
𝐹 = (101, 011, 110, 100) = 5, 3, 6, 4 = (3, 4, 5, 6)
𝑚 𝑚 𝑚
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Exercise
▪ Identify the minterm numbers in a simplified way.
ത + ഥ𝐴𝐵𝐶 + 𝐴𝐶ҧ
𝐹 = 𝐴𝐵𝐶
ത + ഥ𝐴𝐵𝐶 + 𝐴𝐶(𝐵
𝐹 = 𝐴𝐵𝐶 ҧ + 𝐵)
ത
ത + ഥ𝐴𝐵𝐶 + 𝐴𝐵𝐶ҧ + 𝐴𝐵ത 𝐶ҧ
𝐹 = 𝐴𝐵𝐶
Standard/Cononical (SOP)
A B C F minterm no.
𝐹 = (101, 011, 110, 100)
𝑚 0 0 0 0 0
0 0 1 0 1
= 5, 3, 6, 4 = (3, 4, 5, 6) 0 1 0 0 2
𝑚 𝑚
ҧ
𝐴𝐵𝐶 0 1 1 1 3
𝐴𝐵ത 𝐶ҧ 1 0 0 1 4
𝐴𝐵𝐶ത 1 0 1 1 5
𝐴𝐵𝐶ҧ 1 1 0 1 6
1 1 1 0 7
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Standard Sum-of-Products (SOP) Form
▪ A Standard SOP Form in which each product term involves all the variables
(Complemented or Un-complemented). Each individual term is referred to as a
minterm.
Exercise: Express in the standard SOP form
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Exercise
▪ Express the following function as sum of products (SOP) form.
▪ Solution
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Homework-Exercise
▪ Express the following function as sum of products (SOP) form.
▪ Solution
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Homework - Standard Sum-of-Products (SOP) Form
Exercise: Express in the standard SOP form
ҧ
𝑍 = 𝐴𝐵 + 𝐴𝐶𝐷
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Product of Sum (POS)
▪ It consists of two or more OR terms (Sums) that are ANDed together. Each OR
term contains one or more variables in complemented or un-complemented form.
▪ Sum term Product of Sum (POS)
𝐹1 = 𝐴 + 𝐵ത + 𝐶
𝐹2 = 𝐴ҧ + 𝐵 + 𝐶ҧ 𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵)
𝐹3 = 𝐴ҧ + 𝐵
▪ Standard POS (SPOS) : When a function is expressed as a POS, where each term
consists of a sum, the sum involving all of the variables in either complemented or
un-complemented form.
𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵)
𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵 + 𝐶 𝐶)ҧ
𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵 + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)ҧ
Standard POS (SPOS) 𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵 + 𝐶)
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Standard Product of Sum (POS)
▪ Standard POS (SPOS) : When a function is expressed as a POS, where each term
consists of a sum, the sum involving all of the variables in either complemented or
un-complemented form.
𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵 + 𝐶)
𝐹 = 𝑀2 ∙ 𝑀5 ∙ 𝑀4
𝐹 = ෑ (2, 5, 4)
𝑀
▪ Arrange in the increasing order such as 1, 2, 3, 4..
𝐹 = ෑ (2, 4, 5)
𝑀
▪ We can write down from the SPOS directly, by
converting the maxterms in to binary equivalent.
𝐹 = ෑ (010, 101, 100) = ෑ (2, 5, 4) = ෑ (2, 4, 5)
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Standard Product of Sum (POS)
𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵 + 𝐶)
Standard/Canonical (POS)
𝐹 = ෑ (010, 101, 100) = ෑ (2, 5, 4) = ෑ (2, 4, 5)
𝑀 𝑀 𝑀
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Exercise
▪ Identify the Maxterm numbers in a simplified way.
𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵)
𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵 + 𝐶 𝐶)ҧ
𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵 + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)ҧ
Standard POS (SPOS) 𝐹 = (𝐴 + 𝐵ത + 𝐶)(𝐴ҧ + 𝐵 + 𝐶)(
ҧ 𝐴ҧ + 𝐵 + 𝐶)
𝐹 = ෑ (010, 101, 100) = ෑ (2, 5, 4) = ෑ (2, 4, 5)
𝑀 𝑀 𝑀
A B C F Minterm no.
0 0 0 1 0
0 0 1 1 1
𝐴 + 𝐵ത + 𝐶ҧ 0 1 0 0 2
0 1 1 1 3
𝐴ҧ + 𝐵 + 𝐶 1 0 0 0 4
𝐴ҧ + 𝐵 + 𝐶ҧ 1 0 1 0 5
1 1 0 1 6
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SOP and POS
Exercise: Convert the following function in SOP and POS
SOP
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SOP and POS
Exercise: Convert the following function in SOP and POS
POS
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SOP and POS
Exercise: Convert the following function in SOP and POS
SOP
POS
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SOP and POS
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SOP and POS
Exercise: Find the minterms and maxterms without going into a complex
method
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SOP and POS
Exercise: Find F(A, B).
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SOP and POS
Exercise: Find the output function in terms of minterms
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Homework Exercise - Simplifying Logic Circuits
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The Karnaugh map Representation of logical functions
▪ The Karnaugh map (K-map) is a diagram used to simplify a logic equation or to
convert a truth table to its corresponding logic circuit in a simple, orderly process.
Two variables K-Map Format
▪ No. of cells = 2n = 22 = 4
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Exercise - Two variables K-map
▪ Find out the reduced Boolean function in SOP form for a given truth table using a
two variable K-map
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Exercise - Two variables K-map
▪ Find out the reduced Boolean function in POS form for a given truth table using a
two variable K-map
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Three variables K-map
▪ The Grey code is used to
number the rows and
columns in K-map
▪ POS
▪ SOP
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Exercise - Three variables K-map
▪ Exercise: Find out the SOP expression for the following function using the K-map
▪ Adjoining boxes, horizontally and
vertically (but not diagonally) correspond
to minterms , or maxterms ,which differ in
only a single variable, this variable
appearing complemented in one term
and un-complemented in the other.
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Exercise - Three variables K-map
▪ Exercise: Find out the SOP expression for the following function using the K-map
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Exercise - Three variables K-map
▪ Exercise: Find out the POS expression for the following function using the K-map
▪ Adjoining boxes, horizontally and
vertically (but not diagonally)
correspond to minterms , or
maxterms ,which differ in only a
single variable, this variable
appearing complemented in one
term and un-complemented in the
other.
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Exercise - Three variables K-map
▪ Exercise: Find out the POS expression for the following function using the K-map
▪ Adjoining boxes, horizontally and
vertically (but not diagonally) correspond
to minterms , or maxterms ,which differ in
only a single variable, this variable
appearing complemented in one term
and un-complemented in the other.
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Four variables K-map
▪ SOP representation
▪ Practice K-map to fill the cell numbers
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Exercise - Four variables K-map
▪ POS representation
▪ Practice K-map to fill the cell numbers
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Exercise - Four variables K-map
▪ Find the Boolean expression in SOP form for a given K-map
▪ Start forming the largest possible
groups
▪ Check the variables (complemented
or un-complemented) which are
common across the entire group.
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Exercise - Four variables K-map
▪ Find the Boolean expression in SOP form for a given K-map
▪ Start forming the largest possible
groups
▪ Check the variables (complemented
or un-complemented) which are
common across the entire group.
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Exercise - Four variables K-map
▪ Find the Boolean expression in POS form for a given K-map
▪ Start forming the largest possible
groups
▪ Check the variables (complemented
or un-complemented) which are
common across the entire group.
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Exercise - Four variables K-map
▪ Find the Boolean expression in POS form for a given K-map
▪ Start forming the largest possible
groups
▪ Check the variables (complemented
or un-complemented) which are
common across the entire group.
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Definitions
▪ Implicant: a product term that implies F=1
▪ Prime Implicant: an implicant that cannot be combined into another implicant that
has fewer terms
▪ Cannot be further minimized
▪ Essential Prime Implicant: a prime implicant that covers a minterm uniquely.
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Exercise
▪ Which are the implicants, prime implicants, and essential prime implicants?
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Exercise
▪ Which are the implicants, prime implicants, and essential prime implicants?
▪ Implicant: a product term that implies F=1
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Exercise - Two variables K-map
▪ Prime Implicant: an implicant that cannot be combined into another implicant that has fewer terms
▪ Cannot be further minimized
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Exercise - Two variables K-map
▪ Essential Prime Implicant: a prime implicant that covers a minterm uniquely.
▪ If it is restricted to form any of the following groups, the corresponding minterms
will be uncovered. Therefore, those groups are essential, and they are known
as essential prime implicants.
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Exercise
▪ Design a logic circuit that produces a 1 when the 4-bit BCD input code translates to
a decimal number that uses the upper right segment of a 7-segment display
Decimal numbers that use upper right corner
of 7-segment display
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Exercise
▪ Design a logic circuit that produces a 1 when the 4-bit BCD input code translates to
a decimal number that uses the upper right segment of a 7-segment display
Decimal numbers that use upper right corner
of 7-segment display
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Exercise
▪ Logic circuit
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Homework Exercise
▪ Given the following Canonical SOP expression
1. Write out the expression in terms of the minterms.
2. Minimize the SOP expression using a K-Map
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Homework Exercise
▪ Given the following Canonical POS expression
1. Write out the expression in terms of the minterms.
2. Minimize the POS expression using a K-Map.
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Adders
177
Adders
▪ Single-bit Adder Circuits
▪ The Half Adder (HA)
▪ Binary Addition
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The Half Adder (HA)
▪ Two bit adder is known as half adder
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Homework exercises
▪ How many 2 i/p NAND gates needed to design Half adder?
▪ How many 2 i/p NOR gates needed to design Half adder?
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The Half Adder (HA)
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Multiple-bit Addition
▪ Consider single-bit adder for each bit position.
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Multiple-bit Addition
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Full Adder
▪ Three bit adder is known as Full adder.
▪ In Full adder includes (carry in) Ci
▪ Notice interesting pattern in Karnaugh map.
Cin = z
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Multiple-bit Addition
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Multiple-bit Addition
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XOR and XNOR K-map patterns
XOR XNOR
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The Full Adder
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Full adder made of several half adders
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Full Adder
▪ Putting it all together : Single-bit full adder
▪ Common piece of computer hardware
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Half Subtractor
▪ Two bit Subtractor is known as Half Substractor
D = Difference
B = Borrow
D = Difference
B = Borrow
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Full Subtractor
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Full Subtractor
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Full Subtractor
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Negative Numbers – 2’s Complement
▪ Problem statement: Design the Full subtractor using the Full adder
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4-bit Subtractor: E = 1
▪ XOR executes the complement
▪ Adding E=1
to the
complemented
number gives 2’s
complement
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Implementations of Multi-bit Adders:
▪ 1. Ripple Carry Adder
▪ 2. Carry Look-ahead Adder
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Implementations of Multi-bit Adders:
▪ 1. Ripple Carry Adder
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Ripple Carry Adder
▪ Chain single-bit adders together.
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Ripple Carry Adder
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Multiple-bit Addition
▪ The Ripple Carry Adder is slow!
▪ Why?
▪ How can the speed of the adder be increased?
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Increasing the speed of the Adder
▪ Method B: Manipulate the Boolean Algebra
▪ Results in the design of the Carry Looka-head Adder
▪ Carry Look-ahead Adder
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The Full Adder in terms of Pi and Gi
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The Full Adder in terms of Pi and Gi
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The Full Adder in terms of Pi and Gi
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Logic diagram of carry lookahead generator
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Four-bit adder with carry lookahead
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Carry Skip Adder
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Two-bit by two-bit binary multiplier
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Two-bit by two-bit binary multiplier
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Four-bit by three-bit binary multiplier
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BCD Adder
In binary numbering scheme,
whenever the number or sum is
greater Then “9” or whenever there is
carry, we Have to add “0110” (6). After
the addition, the output will be in
BCD.
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BCD Adder
𝐶 = 𝐾 + 𝑍8 𝑍4 + 𝑍2 + 𝑍8 𝑍2
𝐶 = 𝐾 + 𝑍8 𝑍4 + 𝑍8 𝑍2 + 𝑍8 𝑍2
𝐶 = 𝐾 + 𝑍8 𝑍4 + 𝑍8 𝑍2
𝐶 = 𝐾 + 𝑍8 𝑍4 + 𝑍2 + 𝑍8 𝑍2
𝑍8 𝑍2
𝑍8 𝑍4 + 𝑍2
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BCD Adder
𝐶 = 𝐾 + 𝑍8 𝑍4 + 𝑍8 𝑍2
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Addition cases and overflow:
▪ Find the condition when result is not representable.
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Multiple-bit Adder/Subtractor
Build separate binary adder and subtractor
Not common.
⚫ Use 2's Complement representation
Addition uses binary adder
Subtraction uses binary adder with 2's Complement representation for subtrahend
⚫ Issues
Cannot represent a positive number with the same magnitude as the most negative
n-bit number
Must detect overflow
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Overflow
General rule for detecting overflow when performing 2's Complement or 1's
Complement
Addition:
An overflow occurs when the addition of two positive numbers results in a negative
number.
An overflow occurs when the addition of two negative numbers results in a positive
number.
Overflow cannot occur when adding a positive number to a negative number.
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Detecting Overflow for Addition
Overflow occurs if the result is out of range.
Overflow cannot occur when adding a positive number and a negative number.
Overflow occurs when adding two numbers with the same sign.
Two positive numbers → negative number
Two negative numbers → positive number
Can you write a Boolean expression to detect overflow?
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Detecting Overflow for Subtraction
Overflow occurs if the result is out of range.
Overflow cannot occur when subtracting two numbers with the same sign.
Overflow occurs when subtracting a positive number from a negative number or a
negative number from a positive number.
positive # - negative # → negative #
negative # - positive # → positive #
Can you write a Boolean expression to detect overflow?
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Detecting Overflow
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Four-bit adder–subtractor
(with overflow detection)
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Thank you
222
Magnitude Comparator
Designing a magnitude comparator using a Truth Table is too cumbersome.
▪ The magnitude comparator has a certain amount of regularity.
▪ Take advantage of the regularity.
▪ Design the circuit using an algorithm.
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Magnitude Comparator
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Magnitude Comparator
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Magnitude Comparator
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Four-bit magnitude comparator
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Decoders / Encoders
• Binary decoders
• Converts an n-bit code to a single active output
• Can be developed using AND/OR gates
• Can be used to implement logic circuits.
• Binary encoders
• Converts one of 2n inputs to an n-bit output
• Useful for compressing data
• Can be developed using AND/OR gates
• Both encoders and decoders are extensively used in digital systems
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Binary Decoder
• Black box with n input lines and 2n output lines
• Only one output is a 1 for any given input
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2-to-4 Binary Decoder
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3-to-8 Binary Decoder
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Implementing Functions Using Decoders
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Implementing Functions Using Decoders
E = Enabler, E=1 (enabled), E=0 (disabled)
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Implementing Functions Using Decoders
Homework-Exercise:
• Design a circuit, using a 3-to-8 Decoder to realize the Boolean expression given below.
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Implementing Functions Using Decoders
Exercise:
• Design a Full Adder using a 3-to-8 Decoder.
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Building a Binary Decoder with NAND Gates
Active Low
E=0 (Enabled)
E=1 (Disabled)
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Use two 3 to 8 decoders to make 4 to 16 decoder
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Encoders
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4-to-2 Binary Encoder
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8-to-3 Binary Encoder
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Priority Encoder
• Higher-order input has higher priority than of lower-order input
• Order of the input determined by its binary value
• I0 has binary value 000 (0)
• I1 has binary value 001 (1)
• I2 has binary value 010 (2)
• I3 has binary value 011 (3)
• etc.
• So,
• I1 selected over I0
• I2 selected over I1 and I0
• I3 selected over I2, I1, and I0
• Etc.
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Priority Encoder
• Valid indicator
• Output signal of the (priority) encoder that indicates the validity of the
encoded output
• Encoded output is invalid when no inputs are selected
• or when the encoder is disabled
• V = 0 (indicates invalid encoded output; active high)
• Encoded output when one, or more, input(s) is (are) selected, and encoder
is enabled
• V = 1 (indicates valid encoded output; active high)
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4-to-2 Priority Encoder
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8-to-3 Priority Encoder
• What if more than one input line has a value of 1?
• Ignore “lower priority” inputs.
• Idle indicates that no input is a 1.
• Note that polarity of Idle is opposite from Table 4-8 in Mano
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Multiplexers
• A multiplexer switches (or routes) data from 2N inputs to one output, where
N is the number of select (or control) inputs.
• A multiplexer (mux) is a digital switch.
• Select an input value with one or more select bits
• Use for transmitting data
• Allows for conditional transfer of data
• Sometimes called a mux
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4– to– 1- Line Multiplexer
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Quadruple 2–to–1-Line Multiplexer
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Implementing a Function with a Multiplexer
Each row in a Truth Table corresponds to a minterm
– N-input Truth Table
• Each minterm can be mapped to a multiplexer input
– N-input Multiplexer
• For each row in the Truth Table, where the output of the function is one (F = 1),
– Set the corresponding input of the multiplexer to 1
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Implementing a Function with a Multiplexer
Exercise:
Design a circuit, using a 4-to-1 Mux to realize the Boolean expression given below.
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Designing Logic Circuits Efficiently with a Multiplexer
Each row in a Truth Table corresponds to a minterm
– N-input Truth Table
• A product term of N-1 variables can be mapped to each of the
multiplexer inputs
– (N-1)-input Multiplexer
• For the rows in the Truth Table,
– Group N-1 highest order inputs into pairs
– Define the output of each pair using the Nth input
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Implementing a Boolean function with a multiplexer
• Connect input variables to Exercise:
Design a circuit, using a 4-to-1 Mux to realize the Boolean
select inputs of expression given below.
multiplexer (n-1 for n
variables) Selects (Sn)
Inputs
• Set data inputs to
multiplexer equal to
values of function for
corresponding assignment
of select variables
• Using a variable at data
inputs reduces size of the
multiplexer
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Implementing a Boolean function with a multiplexer
Exercise:
Design a circuit,
using a 8-to-1 Mux to
realize the given
Boolean expression.
Selects (Sn) Inputs
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Three-State Gates
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Demultiplexer
• A demultiplexer switches (or routes) data from one input to 2N
outputs, where N is the number of select inputs.
• A demultiplexer (DMUX) is also a digital switch.
• A demultiplexer performs the opposite function of a multiplexer.
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1:4 Demultiplexer
Exercise: Design the logic circuit for 1:4 Demultiplxer
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1:8 Demultiplexer
Exercise: Design the logic circuit for 1:8 Demultiplxer
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Sequential Circuits
• Sequential logic is a type of
logic circuit whose output
depends not only on the
present value of its input
signals but on the sequence
of past inputs, the input
history as well.
• This is in contrast to
combinational logic, whose Combinational Circuits Vs. Sequential Circuits
output is a function of only the
present input. That is,
sequential logic has state
(memory) while combinational
logic does not.
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Sequential Circuits
° Circuits require memory to store intermediate data
° Sequential circuits use a periodic signal to determine when to store values.
• A clock signal can determine storage times
• Clock signals are periodic
• Single bit storage element is a flip flop
• A basic type of flip flop is a latch
• Latches are made from logic gates
• NAND, NOR, AND, OR, Inverter
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Sequential Circuits
• Logical operations which respond to combinations of inputs to produce an output.
• Call these combinational logic circuits.
• For example, can add two numbers. But:
• No way of adding two numbers, then adding a third (a sequential operation);
• No way of remembering or storing information after inputs have been removed.
• To handle this, we need sequential logic capable of storing intermediate (and final)
results.
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Sequential Circuits
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Cross-coupled Inverters
• A stable value can be stored at inverter outputs
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S-R Latch with NORs
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S-R Latch with NORs
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S-R Latch with NANDs
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S-R Latches
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SR latch with control input
• Occasionally, desirable to avoid latch changes
• En = 0 disables all latch state changes
• Control signal enables data change when En = 1
• Right side of circuit same as ordinary S-R latch.
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D Latch
• A D latch is like an S-
R latch with only one
input: the “D” input.
Activating the D input sets
the circuit, and de-
activating the D input
resets the circuit.
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D Latch
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D Latch
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D Latch
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D Latch
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Symbols for Latches
• SR latch is based on NOR gates
• S’R’ latch based on NAND gates
• D latch can be based on either.
• D latch sometimes called transparent latch
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Latches
• Latches are based on combinational gates (e.g. NAND, NOR)
• Latches store data even after data input has been removed
• S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset)
• With additional gates, an S-R latch can be converted to a D latch (D stands for data)
• D latch is simple to understand conceptually
• When C = 1, data input D stored in latch and output as Q
• When C = 0, data input D ignored and previous latch value output at Q
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Gated SR Latch: characteristic/state equation
State Equation:
• Q is the present (or current) state.
• Q+ is the next state.
• After the transition of the output Q.
• The next state is a function of the inputs and the present state.
• Inputs: S and R
• Present State: Q
• Note: Q is also denoted as Q(t) and Q+ is also denoted as Q(t+1).
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Gated SR Latch: characteristic/state equation
State Equation: Write the truth table and solve
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Gated D Latch
If En = Clock = 1
Q=D
Else (En = Clock = 0)
Q = Previous state
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Gated D Latch: Clk = 0
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Gated D Latch: Clk = 1
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Gated D Latch
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Gated D Latch
If En = Clock = 1
Q+ = D
Else (En = Clock = 0)
Q+ = Q
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Basic Memory Elements
• Basic Latch
• A feedback connection of two NOR gates or two NAND gates, which can
store one bit of information.
• Can be set to 1 or reset to 0.
• Gated Latch
• A basic latch that also includes input gating and a control input signal (i.e.
the clock).
• Flip-Flop
• A storage element based on the gated latch principle, which can have its
output state changed only on the edge of the controlling clock signal.
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Overview
• Latches respond to trigger levels on control inputs
• Example: If G = 1, input reflected at output
• Difficult to precisely time when to store data with latches
• Flip flips store data on a rising or falling trigger edge.
• Example: control input transitions from 0 -> 1, data input appears at output
• Data remains stable in the flip flop until until next rising edge
• Different types of flip flops serve different functions
• Flip flops can be defined with characteristic equations
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Latches vs Flipflops
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Clocking Event
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Clocking Event
• Negative edge trigger
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Master-Slave D Flip Flop
• Consider two latches combined together
• Only one Clk value active at a time
• Output changes on rising/falling edge of the clock
• Glitches are removed employing the slave
• Slave’s output signal is same as negative edge triggered flip flop’s output
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Master-Slave D Flip Flop
If En = Clock = 1
Output = D
Else (En = Clock = 0)
Output = Previous state
• We should not change the input
Signal when clock is – that will
cause the glitches.
To remove glitches
We use Master Slave FlipFlip
• Glitches: Sudden changes in Y
• Glitches are removed in the slave’s output
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D-type positive-edge-triggered flip-flop: Operation
En = Clock = Clk = C
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Yp
D-type Negative-edge-triggered flip-flop: Operation
En = Clock = Clk = C
Yn
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Master-Slave D Flip Flop
• Consider two latches combined together
• Only one Clk value active at a time
• Output changes on rising/falling edge of the
clock
• Glitches are removed employing the slave
• Slave’s output signal is same as negative
edge triggered flip flop’s output
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D-type positive-edge-triggered flip-flop
Homework: Process all the inputs and check the outputs
Q(t) → Q(t+1)
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J-K Flip-Flop
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J-K Flip-Flop
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JK Flip Flop: Race around condition / Latch Race Problem
• When J=K=1, output toggles recursively during active period of clock pulse
• This leads to unpredictable output state after active period of clock pulse
• This condition is know as race around condition
Solution to race around condition
• Master slave FF: that gives a single trigger at slave output. How ever race around condition
occurs in Master.
•Edge triggered FF: flip-flop triggers the ‘edge’ of clock pulse
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Edge Triggered Flip Flop
•Edge triggered FF considers input values at the edge of the clock
pulse (either positive or negative)
• Timing diagram of typical positive edge triggered JK FF
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Positive Edge-Triggered J-K Flip-Flop
• Created from D flop
• J sets
• K resets
• J=K=1 -> invert output
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T Flip-Flop
• Created from D flop
• T=0 -> keep current
• K resets
• T=1 -> invert current
Positive Edge-Triggered T-Flip Flop
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Flip-Flop Characteristic Table Summary
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Asynchronous Inputs
• Pre-set and Clear are the overriding
inputs or asynchronous inputs
• Synchronous inputs are S, R, J, K, D &
T
• If Preset = 0 → Q=1
• If Clear = 0 → Q=0
• When Pre-set or Clear is given, it will
ignore the S, R, J, K, D, & T, and
override the outputs as per the above
condition.
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Asynchronous Inputs (JK-FF)
• If Preset = 0 → Q=1
• If Clear = 0 → Q=0
• Async inputs over-ride the clk also
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Asynchronous Inputs (D-FF)
• Note reset signal (R) for D flip flop
• If R = 0, the output Q is cleared
•This event can occur at any time, regardless of
the value of the CLK
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Parallel Data Transfer
• Flip flops store outputs from
combinational logic
• Multiple flops can store a collection
of data
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Summary
• Flip flops are powerful storage elements
• They can be constructed from gates and latches!
• D flip flop is simplest and most widely used
• Asynchronous inputs allow for clearing and pre-setting the flip flop output
• Multiple flops allow for data storage
• The basis of computer memory!
• Combine storage and logic to make a computation circuit
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Shift Registers and Counters
Registers Overview
• Multiple flip flops can be combined to form a data register
• Shift registers allow data to be transported one bit at a time
• Registers also allow for parallel transfer
• Many bits transferred at the same time
• Shift registers can be used with adders to build arithmetic units
• Remember: most digital hardware can be built from arithmetic units
• Most digital hardware can be built from combinational logic and, or, invert) and
flip flops
• Basic components of most computers
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Registers
• Register
• Consists of N Flip-Flops
• Stores N bits
• Common clock used for all Flip-Flops
• Shift Register
• A register that provides the ability to shift its contents (either left or right).
• Must use Flip-Flops
• Either edge-triggered or master-slave
• Cannot use Level-sensitive Gated Latches
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Register with Parallel (data) Loading
• Register: Group of Flip-Flops
• Ex: D Flip-Flops
• Holds a Word (Nibble) of Data
• Loads in Parallel on Clock Transition
• Asynchronous Clear (Reset)
Four‐bit register
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Register with Load Control
• Load Control = 1
• New data loaded on next positive
clock edge
• Load Control = 0
• Old data reloaded on next positive
clock edge
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Shift Registers
• Cascade chain of Flip-Flops
• Bits travel on Clock edges
• Serial in – Serial out, can also have parallel load / read
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Parallel Data Transfer
• All data transfers on rising clock edge
• Data clocked into register Y
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Parallel versus Serial
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Shift register application
• Parallel-to-serial conversion for serial transmission
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Serial Transfer
• Data transfer one bit at a time
• Data loopback for register A
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Serial Transfer of Data
• Transfer from register X to register Y (negative clock edges for this
example)
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Serial Addition
• Slower than parallel
• Low cost
• Share fast hardware on slow data
• Good for multiplexed data
• Only one full adder
• Reused for each bit
• Start with lower order bit addition
• Note that carry (Q) is saved
• Add multiple values
• New values
• placed in shift register B
• Shift control used to stop addition
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Universal Shift Register
• Clear
• Clock
• Shift
• Right
• Left
• Load
• Read
• Control
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Universal Sift register
• Unidirectional shift register:
• It can shift the data only in one direction S1 S0 Register output
• Bidirectional shift register: 0 0 No change
• It can shift the date in both the direction 0 1 Shift Right
1 0 Shift Left
• Universal Sift register:
• Bidirectional + Parallel Loading 1 1 Parallel load
• Data I0, I1, I2, and I3 are stored in the D-FF Clk D Q(t+1)
0 X Q(t)
• Parallel input Parallel Output
1 0 0
• Clear is used for resetting 1 1 1
• S0 and S1 are selectors
• They are also used to select the mode of the register, Left shifting, right shifting or parallel loading
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No change
1 0 1 1
S1 S0 Register output 1 0 1 1
0 0 No change
0
0 1 Shift Right
1 0 Shift Left 0
1 1 Parallel load A3 A2 A1 A0
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Shift Right
1
S1 S0 Register output 1
0 0 No change
0
0 1 Shift Right
1 0 Shift Left 1
1 1 Parallel load 1 1
1
• I1 is connected to the output 1011
• Serial input 1011
• First clock pulse
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Shift Right
1 1
S1 S0 Register output 1 1
0 0 No change
0
0 1 Shift Right
1 0 Shift Left 1
1 1 Parallel load 1 1 1 1
1
• I1 is connected to the output
• Serial input 1011
1011
• Second clock pulse
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Shift Left
1
S1 S0 Register output
1
0 0 No change
1
0 1 Shift Right
1 0 Shift Left 0 1
1 1 Parallel load 1
1
• I1 is connected to the output
• Serial input 1011
• First clock 1011
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Shift Left
1 1
S1 S0 Register output 1 1
0 0 No change
1
0 1 Shift Right
1 0 Shift Left 0 1
1 1 Parallel load 1 1
1
• I1 is connected to the output
• Serial input 1011
• Second clock 1011
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Parallel loading
1 1 0 0
1 1 0 0
S1 S0 Register output 1 1 0 0
0 0 No change
1
0 1 Shift Right
1 0 Shift Left 1
1 1 Parallel load 1 1 0 0
• I1 is connected to the output
• Parallel inputs 1100
1 1 0 0
• All the bits are loaded at a
single clock pulse
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Shift Register Summary
• Shift registers can be combined together to allow for data transfer
• Serial transfer used in modems and computer peripherals
• D flip flops allow for a simple design
• Data clocked in during clock transition (rising or falling edge)
• Serial addition takes less chip area but is slow
• Universal shift register allows for many operations
• The register is programmable.
• It allows for different operations at different times
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Counters Overview
• Counters are important components in computers
• The increment or decrement by one in response to input
• Two main types of counters
• Ripple (asynchronous) counters
• Synchronous counters
• Ripple counters
• Flip flop output serves as a source for triggering other flip flops
• Synchronous counters
• All flip flops triggered by a clock signal
• Synchronous counters are more widely used in industry.
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Asynchronous / Ripple counters
• Ripple counters
• External clock is given to the
first flip flop
• Output of the first flip flop act as
a clock for the next flip flop
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Synchronous counters
• External clock is applied to all the
Flip flops simultaneously.
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Asynchronous / Ripple counters
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Asynchronous / Ripple counters
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Binary Ripple Counters with T and D-FF
• Reset signal sets all outputs to 0
• Count signal toggles output of low-order flip flop
• Low-order flip flop provides trigger for adjacent flip flop
• Not all flops change value simultaneously
• Lower-order flops change first
• Focus on D flip flop
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Asynchronous Counters
• Example: 2-bit ripple binary counter.
• Output of one flip-flop is connected to the clock input of the next more-
significant flip-flop.
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Asynchronous Counters
Example: 3-bit ripple binary counter.
Q2 Q1 Q0 Decimal
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
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Asynchronous Counters
• Propagation delays in an asynchronous (ripple clocked) binary counter.
• If the accumulated delay is greater than the clock pulse, some counter states
may be misrepresented!
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Asynchronous Counters
Example: 4-bit ripple binary counter (negative-edge triggered)
Q3 Q2 Q1 Q0 Decimal
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
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BCD Ripple Counter Q0
Q1
Q2
Q3
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Asynchronous Down Counters
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Asynchronous Down Counters
Example: A 3-bit binary (MOD-8) down counter.
Q2 Q1 Q0 Decimal
1 1 1 7
1 1 0 6
1 0 1 5
1 0 0 4
0 1 1 3
0 1 0 2
0 0 1 1
0 0 0 0
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Cascading Asynchronous Counters
• Example: A 6-bit binary counter (counts from 0 to 63) constructed from two 3-
bit counters.
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Ring counter
ORI: Override inputs
PR = 0 → Q=1
CLR = 0 → Q=0
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Ring counter
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Johnson’s counter
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Johnson’s counter
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Synchronous (parallel) counters
• Synchronous (parallel) counters: the flip-flops are clocked at the same time by
a common clock pulse.
• We can design these counters using the sequential logic design process
• Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops
with identical J,K inputs).
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Synchronous (Parallel) Counters
• Example: 3-bit synchronous binary counter (using T flip-flops, or JK flip-flops
with identical J, K inputs).
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Synchronous (Parallel) Counters
• Homework: Example: 4-bit synchronous binary counter
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Synchronous (Parallel) Counters
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Synchronous (Parallel) Counters
Homework
Hint: Design the
logic equations
through K-maps
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Four‐bit synchronous binary counter
• Synchronous(parallel) counters
• All of the FFs are triggered simultaneously by the
clock input pulses.
• All FFs change at same time
• Remember
• If J=K=0, flop maintains value
• If J=K=1, flop toggles
• Most counters are synchronous in computer
systems.
• Can also be made from D flops
• Value increments on positive edge
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Synchronous UP/Down counters
• Up/Down Counter can either count
up or down on each clock cycle
• Up counter counts from 0000 to 1111
and then changes back to 0000
• Down counter counts from 1111 to
0000 and then back to 1111
• Counter counts up or down each
clock cycle
• Output changes occur on clock rising
edge
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Four‐bit binary counter with parallel load
• Counters with parallel load can have a
preset value
• Load signal indicates that data (I3…I0)
should be loaded into the counter
• Clear resets counter to all zeros
• Carry output could be used for higher-order
bits
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Four‐bit binary counter with parallel load
• Counters with parallel load can have a
preset value
• Load signal indicates that data (I3…I0)
should be loaded into the counter
• Clear resets counter to all zeros
• Carry output could be used for higher-order
bits
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Binary Counter with Parallel Load and Preset
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Summary
• Binary counters can be ripple or synchronous
• Ripple counters use flip flop outputs as flop triggers
• Some delay before all flops settle on a final value
• Do no require a clock signal
• Synchronous counters are controlled by a clock
• All flip flops change at the same time
• Up/Down counters can either increment or decrement a stored binary value
• Control signal determines if counter counts up or down
• Counters with parallel load can be set to a known value before counting
begins.
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Serial Addition
Setup Time (tsetup)
It is defined as the minimum time between a Data
(Din) change and the triggering edge of the clock,
also referred to as data-to-clock delay, such that
the output Q out will be guaranteed to change so as
to become equal to the new value of Din. We
denote this parameter as tsetup. The setup time is
defined such that, any change in Data at Din arriving
earlier than the Setup Time, tsetup, should not result
in any changes in the clock-to-out delay time. In
other words, data signal on Din should occur
sufficiently early so that making it appear any
earlier would have no effect on when the output Qout
changes.
Hold time (thold)
Hold time is the minimum time that the data at Din must be held constant after the triggering edge of the clock
signal, assuming that the most recent data change occurred not later than the Setup time tsetup, such the
output Qout will remain stable. This is denoted as thold and this value can be negative.
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Logic Families
Refer the lecture notes: Uploaded on Moodle and Google drive
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Hardware description language (HDL)
▪ A hardware description language (HDL) is a computer-based language that describes the hardware of digital
systems in a textual form.
▪ It resembles an ordinary computer programming language, such as C, but is specifically oriented to describing
hardware structures and the behaviour of logic circuits.
▪ It can be used to represent logic diagrams, truth tables, Boolean expressions, and complex abstractions of the
behaviour of a digital system.
▪ Logic simulation displays the behaviour of a digital system through the use of a computer.
▪ The stimulus (i.e., the logic values of the inputs to a circuit) that tests the functionality of the design is called a
test bench.
▪ Logic synthesis is the process of deriving a list of physical components and their interconnections (called a
netlist) from the model of a digital system described in an HDL.
▪ Timing verification confirms that the fabricated, integrated circuit will operate at a specified speed. Because
each logic gate in a circuit has a propagation delay, a signal transition at the input of a circuit cannot immediately
cause a change in the logic value of the output of a circuit.
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Hardware description language (HDL)
▪ Propagation delays ultimately limit the speed at which a circuit can operate.
▪ Timing verification checks each signal path to verify that it is not compromised by propagation delay. This step is done
after logic synthesis specifies the actual devices that will compose a circuit and before the circuit is released for
production.
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Verilog. Hardware description language (VHDL)
▪ Keywords are predefined lowercase identifiers that define the language constructs.
▪ Examples of keywords are
▪ module,
▪ endmodule,
▪ input,
▪ output,
▪ wire,
▪ or,
▪ not.
▪ Verilog is case sensitive, which means that uppercase and lowercase letters are distinguishable (e.g.,
not is not the same as NOT).
▪ The term module refers to the text enclosed by the keyword pair module . . . endmodule. A module
is the fundamental descriptive unit in the Verilog language. It is declared by the keyword module
and must always be terminated by the keyword endmodule.
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Circuit to demonstrate an HDL
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Summary
▪ The port list of a module is the interface between the module and its environment. In this example, the ports
are the inputs and outputs of the circuit. The logic values of the inputs to a circuit are determined by the
environment; the logic values of the outputs are determined within the circuit and result from the action of
the inputs on the circuit. The port list is enclosed in parentheses, and commas are used to separate
elements of the list. The statement is terminated with a semicolon (;). In our examples, all keywords (which
must be in lowercase) are printed in bold for clarity, but that is not a requirement of the language. Next, the
keywords input and output specify which of the ports are inputs and which are outputs. Internal
connections are declared as wires. The circuit in this example has one internal connection, at terminal w1 ,
and is declared with the keyword wire. The structure of the circuit is specified by a list of (predefined)
primitive gates, each identified by a descriptive keyword ( and, not, or ). The elements of the list are
referred to as instantiations of a gate, each of which is referred to as a gate instance. Each gate
instantiation consists of an optional name (such as G1, G2 , etc.) followed by the gate output and inputs
separated by commas and enclosed within parentheses. The output of a primitive gate is always listed first,
followed by the inputs. For example, the OR gate of the schematic is represented by the or primitive, is
named G3 , and has output D and inputs w1 and E . ( Note : The output of a primitive must be listed first,
but the inputs and outputs of a module may be listed in any order.) The module description ends with the
keyword endmodule. Each statement must be terminated with a semicolon, but there is no semicolon after
endmodule.
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Gate Delays
▪ All physical circuits exhibit a propagation delay between the transition of an input and a resulting
transition of an output.
▪ HDL Example 3.2 repeats the description of the simple circuit of Example 3.1 , but with
propagation delays specified for each gate.
▪ The and, or, and not gates have a time delay of 30, 20, and 10 ns, respectively. If the circuit is
simulated and the inputs change from A , B , C = 0 to A , B , C = 1, the outputs change as shown
in Table 3.5 (calculated by hand or generated by a simulator).
▪ The output of the inverter at E changes from 1 to 0 after a 10-ns delay. The output of the AND
gate at w1 changes from 0 to 1 after a 30-ns delay. The output of the OR gate at D changes from
1 to 0 at t = 30 ns and then changes back to 1 at t = 50 ns. In both cases, the change in the
output of the OR gate results from a change in its inputs 20 ns earlier. It is clear from this result
that although output D eventually returns to a final value of 1 after the input changes, the gate
delays produce a negative spike that lasts 20 ns before the final value is reached.
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Gate Delays
▪ The output of the inverter at E changes from 1 to 0 after a 10-
ns delay. The output of the AND gate at w1 changes from 0 to
1 after a 30-ns delay. The output of the OR gate at D changes
from 1 to 0 at t = 30 ns and then changes back to 1 at t = 50
ns. In both cases, the change in the output of the OR gate
results from a change in its inputs 20 ns earlier. It is clear
from this result that although output D eventually returns to a
final value of 1 after the input changes, the gate delays
produce a negative spike that lasts 20 ns before the final
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Summary
▪ In order to simulate a circuit with an HDL, it is necessary to apply inputs to the circuit so that the
simulator will generate an output response. An HDL description that provides the stimulus to a
design is called a test bench.
▪ HDL Example 3.3 shows a test bench for simulating the circuit with delay. (Note the distinguishing
name Simple_Circuit_prop_delay). In its simplest form, a test bench is a module containing a
signal generator and an instantiation of the model that is to be verified. Note that the test bench (
t_Simple_Circuit_prop_delay ) has no input or output ports, because it does not interact with its
environment. In general, we prefer to name the test bench with the prefix t_concatenated with the
name of the module that is to be tested by the test bench, but that choice is left to the designer.
Within the test bench, the inputs to the circuit are declared with keyword reg and the outputs are
declared with the keyword wire . The module Simple_Circuit_prop_delay is instantiated with the
instance name M1. Every instantiation of a module must include a unique instance name. Note
that using a test bench is similar to testing actual hardware by attaching signal generators to the
inputs of a circuit and attaching.
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Test Bench
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Summary
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VHDL coding- Boolean Expressions through
▪ Boolean equations describing combinational logic are specified in Verilog with a continuous
assignment statement consisting of the keyword assign followed by a Boolean expression. To
distinguish arithmetic operators from logical operators, Verilog uses the symbols (&), (/), and (&) for
AND, OR, and NOT (complement), respectively. Thus, to describe the simple circuit of Fig. 3.35
with a Boolean expression, we use the statement
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User-Defined Primitives
▪ The logic gates used in Verilog descriptions
with keywords and, or, etc., are defined by
the system and are referred to as system
primitives. (Caution: Other languages may
use these words differently.)
▪ The user can create additional primitives by
defining them in tabular form. These types of
circuits are referred to as user-defined
primitives (UDPs). One way of specifying a
digital circuit in tabular form is by means of a
truth table.
▪ UDP descriptions do not use the keyword pair
module . . . endmodule. Instead, they are
declared with the keyword pair primitive . . .
endprimitive. The best way to demonstrate a
UDP declaration is by means of an example.
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User-Defined Primitives
HDL Example 3.5 defines a UDP with a truth table. It
proceeds according to the
following general rules:
• It is declared with the keyword primitive , followed by a
name and port list.
• There can be only one output, and it must be listed first in
the port list and declared with keyword output .
• There can be any number of inputs. The order in which
they are listed in the input declaration must conform to the
order in which they are given values in the table that
follows.
• The truth table is enclosed within the keywords table and
endtable.
• The values of the inputs are listed in order, ending with a
colon (:). The output is always
the last entry in a row and is followed by a semicolon (;).
• The declaration of a UDP ends with the keyword
endprimitive.
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User-Defined Primitives
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VHDL
▪ Gate-level (structural) modeling describes a circuit by specifying its gates
and how they are connected with each other.
▪ Gate-level modeling using instantiations of predefined and user-defined
primitive gates.
▪ Dataflow modeling is used mostly for describing the Boolean equations of
combinational logic.
▪ Dataflow modeling using continuous assignment statements with the keyword
“assign”.
▪ Behavioral modeling using procedural assignment statements with the
keyword “always”
▪ Behavioral modeling that is used to describe combinational and sequential
circuits at a higher level of abstraction.
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Netlist
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Relationship of Verilog constructs to truth tables, Boolean
equations, and schematics
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Exercise: Write a VHDL code for 2:4 line decoder
Gate-level (structural) modeling
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VHDL – Data flow description
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VHDL Operators
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VHDL Dataflow – Four bit Adder
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VHDL Dataflow – Four bit comparator
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D Latch
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Homework: VHDL code of the description of D - Latch
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Homework – Explore a code for synchronous counter
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Basic Design Methodology
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Basic Design Methodology
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Overview: Memory
▪ Memory is a collection of storage cells with associated input and output circuitry
▪ Possible to read and write cells
▪ Random access memory (RAM) contains words of information
▪ Data accessed using a sequence of signals
▪ Leads to timing waveforms
▪ Decoders are an important part of memories
▪ Selects specific data in the RAM
▪ Static RAM loses values when circuit power is removed.
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Preliminaries
▪ RAMs contain a collection of data bytes
▪ A collection of bytes is called a word
▪ A sixteen bit word contains two bytes
▪ C is the Capacity of RAM device is usually described in bytes (e.g. 16MB)
▪ Write operations write data to specific words
▪ Read operations read data from specific words
▪ Note: new notation for OR gate
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RAM Interface Signals
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RAM Size
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Write Operation
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Read Operation
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Memory Timing – write operation
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Timing Waveforms – read operation
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Comments about Memory Access and Timing
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Types of Random Access Memories
° Static random access memory (SRAM)
• Operates like a collection of latches
• Once value is written, it is guaranteed to remain in the memory as long as power is applied
• Generally expensive
• Used inside processors (like the Pentium)
° Dynamic random access memory (DRAM)
• Requires data to be rewritten (refreshed), otherwise data is lost
• Generally, simpler internal design than SRAM
• Often hold larger amount of data than SRAM
• Longer access times than SRAM
• Used as main memory in computer systems
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Inside the RAM Device
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Inside the SRAM Device
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Random Access Memory
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Exercise:
▪ Design a 32K x 32 memory using RAM chips that are 32K x 8.
▪ How many address bits are required?
▪ How many data bits are required?
2^15 = 32768 = 32K
▪ Address bits are A0 to A14
▪ Data bits D0 to D31
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Summary
▪ Memories provide storage for computers
▪ Memories are organized in words
▪ Selected by addresses
▪ SRAMs store data in latches
▪ Accessed by surrounding circuitry
▪ RAM waveforms indicate the control signals needed for access
▪ Words in SRAMs are accessed with decoders
▪ Only one word selected at a time
▪ Can be written to or read from.
▪ Read/Write memory
▪ Reading from RAM is non-destructive.
▪ Access time to read from any memory location is the same.
▪ As compared to serial access memory.
▪ Volatile
▪ Information is lost when power is removed.
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Example Memory Components:
▪ Volatile:
▪ Random Access Memory (RAM):
▪ DRAM "dynamic"
▪ SRAM "static"
▪ Non-volatile:
▪ Read Only Memory (ROM):
▪ Mask ROM "mask programmable"
▪ EPROM "electrically programmable"
▪ EEPROM "erasable electrically programmable"
▪ FLASH memory – similar to EEPROM with programmer integrated on chip
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Read Only Memory (ROM) Overview
▪ Read-only memory can normally only be read
▪ ROM doesn’t lose storage value when power is removed
▪ Internal organization similar to SRAM
▪ ROMs are effective at implementing truth tables
▪ Any logic function can be implemented using ROMs
▪ Multiple single-bit functions embedded in a single ROM
▪ Also used in computer systems for initialization
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Read Only Memory (ROM)
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Read Only Memory (ROM)
▪ Programmable Read Only Memory (PROM)
▪ Can be “programmed”
▪ Erasable PROM (EPROM)
▪ Can be “programmed” and erased
▪ Electrically Erasable PROM (EEPROM)
▪ Can be erased using an electrical signal
▪ UV Erasable PROM (UVEPROM)
▪ Can be erased using Ultraviolet light
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Read-Only Memory (ROM)
▪ An array of semiconductor devices
▪ diodes
▪ transistors
▪ field effect transistors
▪ 2N words by M bits
▪ Data can be read but not changed
▪ (normal operating conditions)
▪ N input bits
▪ 2N words by M bits
▪ Implement M arbitrary functions of N variables
▪ Example 8 words by 5 bits:
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ROM Implementation
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ROM Implementation
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Read-Only Memory (ROM)
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ROM Internal Structure
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Inside the ROM
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ROM Exercise
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Summary
▪ ROMs provide stable storage for data
▪ ROMs have address inputs and data outputs
▪ ROMs directly implement truth tables
▪ In normal use ROMs are read-only
▪ They are only read, not written
▪ ROMs are often used by computers to store critical information
▪ Unlike SRAM, they maintain their storage after the power is turned off
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FLASH Memory
▪ Electrically erasable
▪ In system programmability and erasability (no special system or voltages
needed)
▪ On-chip circuitry (FSM) to control erasure and programming (writing)
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Programmable Logic Devices
▪ Programmable Logic Arrays (PLA)
▪ Programmable Array Logic (PAL)
▪ Simple Programmable Logic Device (SPLD)
▪ Complex Programmable Logic Device (CPLD)
▪ Field Programmable Gate Array (FPGA)
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PLD Summary
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PLA Example
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Programmable Logic Overview
▪ Programmable logic offers designers opportunity to customize chips
▪ Programmable logic devices have a fixed logic structure
▪ Programmable array logic contain AND-OR circuits
▪ First introduced in early 1980’s
▪ Field programmable gate arrays (FPGAs) contain small blocks that
implement truth tables
▪ First introduced in 1985 (Xilinx Corporation)
▪ Software used to convert user designs to programming information
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Programmable Array Logic
• Implements sum-of products expressions
• Four external inputs (and complements)
• Feedback path from output F1
• Product term connections made via switches
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Programmable Array Logic
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Reconfigurable Hardware
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Field-Programmable Gate Array
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Circuit Compilation
Look-up Tables (LUT)
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Basic FPGA Architecture
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FPGA Operation
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Summary
▪ Programmable logic allows for designers to easily create custom designs
▪ Programmable array logic contains AND-OR structures to implement SOP
equations
▪ FPGAs contain small memories and numerous wires for routing
▪ Designers create designs in Verilog
▪ Design translated to the chip via software
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Thank you
422
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