Ppt#06

SUBJECT-EMBEDDED SYSTEMS
BATCH-22CS (6TH SEMESTER THIRD YEAR)

General-Purpose I/0 (GPIO) Assembly

Programming
1
 OUTLINE
 System architecture

 STM32F0x0 peripheral register boundary addresses

 GPIO Registers

 RCC Registers Map

 GPIO assembly Programming Examples

 On-board LED

 On-board LED with pushbutton

 Toggling LED

 Common anode 7-segment Display

2
 System Architecture
The main system consists of:
 Two masters:
 ARM Cortex-M0 core
 General-purpose DMA
 Four slaves:
 Internal SRAM
 Internal Flash memory
 AHB1 with AHB to APB bridge which connects all the APB
peripherals
 AHB2 dedicated to GPIO ports
 These are interconnected using a multilayer AHB bus architecture as
shown in Figure 1:

3
System Architecture

4
 System Architecture
System bus
 This bus connects the system bus of the ARM Cortex-M0 core (peripherals
bus) to a BusMatrix which manages the arbitration between the core and
the DMA.
DMA bus
 This bus connects the AHB master interface of the DMA to the BusMatrix
which manages the access of CPU and DMA to SRAM, Flash memory and
peripherals.
BusMatrix
 The BusMatrix manages the access arbitration between the core system
bus and the DMA master bus.
AHB to APB bridge (APB)
 The AHB to APB bridge provides full synchronous connections between the
AHB and the APB bus.
 After each device reset, all peripheral clocks are disabled (except for the
SRAM and Flash). Before using a peripheral you have to enable its clock in
the RCC_AHBENR, RCC_APB2ENR or RCC_APB1ENR register.

5
STM32F0x0 peripheral register boundary addresses

6
 General Purpose I/Os (GPIO)
 Each general-purpose I/O (GPIO) port has
 Four 32-bit configuration registers
 GPIOx_MODER
 GPIOx_OTYPER
 GPIOx_OSPEEDR
 GPIOx_PUPDR
 Two 32-bit data registers
 GPIOx_IDR
 GPIOx_ODR
 A 32-bit set/reset register
 GPIOx_BSRR
 Ports A and B also have a 32-bit locking register
 GPIOx_LCKR
 Two 32-bit alternate function selection registers
 GPIOx_AFRH
 GPIOx_AFRL.

7
 General Purpose I/Os (GPIO)

Using the HSE or LSE oscillator pins as GPIOs

 When the HSE or LSE oscillator is switched OFF (default state after
reset), the related oscillator pins can be used as normal GPIOs.
 When the HSE or LSE oscillator is switched ON (by setting the
HSEON or LSEON bit in the RCC_CSR register) the oscillator takes
control of its associated pins and the GPIO configuration of these
pins has no effect.
 When the oscillator is configured in a user external clock mode, only
the pin is reserved for clock input and the OSC_OUT or OSC32_OUT
pin can still be used as normal GPIO.

8
 General Purpose I/Os (GPIO) Register
GPIO port mode register (GPIOx_MODER) (x =A..D, F)
 Address offset:0x00
 Reset values:
 0x2800 0000 for port A and
 0x0000 0000 for other ports

 Bits 2y+1:2y MODERy[1:0]: Port x configuration bits (y = 0..15) These bits are
written by software to configure the I/O mode.
 00: Input mode (reset state)
 01: General purpose output mode
 10: Alternate function mode
 11: Analog mode
9
 General Purpose I/Os (GPIO) Register
GPIO port input data register (GPIOx_IDR) (x =A..D, F)
 Address offset:0x10
 Reset values:
 0x 0000 XXXX (where X is undefined)

 Bits 31:16 Reserved, must be kept at reset value.

 Bits 15:0 IDRy: Port input data bit (y = 0..15)
 These bits are read-only and written by software. They contain the input
value of the corresponding I/O port.

10
 General Purpose I/Os (GPIO) Register
GPIO port output data register (GPIOx_ODR) (x =A..D, F)
 Address offset:0x14
 Reset values:
 0x 0000 0000

 Bits 31:16 Reserved, must be kept at reset value.

 Bits 15:0 ODRy: Port input data bit (y = 0..15)
 These bits can be read and written by software.

11
 General Purpose I/Os (GPIO) Register
GPIO alternate function Low register (GPIOx_AFRL) (x =A..D)
 Address offset:0x20
 Reset values:
 0x 0000 0000

 Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 0..7)
 These bits are written by software to configure alternate function I/Os

12
 General Purpose I/Os (GPIO) Register
GPIO alternate function High register (GPIOx_AFRH) (x =A..D)
 Address offset:0x24
 Reset values:
 0x 0000 0000

 Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15)
 These bits are written by software to configure alternate function I/Os
AFSELy selection: for both AFRL and AFRH Register

13
 RCC Register Map

 The following table gives the RCC register map and the reset values.

14
 GPIO Assembly Programming
Example#01: Write an assembly program to turn ON on-board-LED of
stm32f030R8 cortex-M0 ARM (connected to PC9(pin#9 of GPIOC )).
Steps
1. In DATA area declare the variables for BASE address of RCC, and
GPIOs using AHB1 and AHB2 base address from STM32F0x0
peripheral register boundary addresses.
2. In CODE area Enable the clock for GPIOC using RCC_AHBENR Register
(19th bit of the register). Use RCC base address with 0x14 offset value
(RCC_BASE+0x14) .
3. Set the mode in MODER register of PC9(GPIOC,pin#9) as output (01
for output). Use GPIOC base address with 0x00 offset value
(GPIOC_BASE+0x00) .
4. Write HIGH to PC9 in output data register(ODR). Use GPIOC base
address with 0x14 offset value (GPIOC_BASE+0x14) .

15
 GPIO Assembly Programming
Example#01: Write an assembly program to turn ON on-board-LED of
stm32f030R8 cortex-M0 ARM (connected to pin#9 of GPIOC ).

area mydata, DATA

AHB1_BASE EQU 0x40020000
AHB2_BASE EQU 0x48000000
RCC_BASE EQU (AHB1_BASE+0x1000)
GPIOC_BASE EQU (AHB2_BASE+0x800)

area mycode, CODE

export __main
__main
LDR R0, =(RCC_BASE+0x14) ;Enable clock for GPIOC
LDR R1, =(1<<19)
STR R1, [R0]

LDR R0, =(GPIOC_BASE+0x00) ;GPIOC Pin#9 as a output mode

LDR R1, =(1<<9*2)
STR R1, [R0]
16
 GPIO Assembly Programming
LOOP
LDR R0, =(GPIOC_BASE+0x14) ;GPIOC as ODR, set pin#9
LDR R1, =(1<<9)
STR R1, [R0]
B LOOP
END

Home Work:
1. Write an assembly program to turn ON all bits of PORTB.

17
 GPIO Assembly Programming
Example#02: Write an assembly program for stm32f030R8 cortex-M0
ARM to toggle PC8 with a delay of 1sec.
Steps
1. In DATA area declare the variables for BASE address of RCC, and
GPIOs using AHB1 and AHB2 base address from STM32F0x0
peripheral register boundary addresses.
2. In CODE area Enable the clock for GPIOC using RCC_AHBENR Register
(19th bit of the register). Use RCC base address with 0x14 offset value
(RCC_BASE+0x14) .
3. Set the mode in MODER register of PC8(GPIOC,pin#8) as output (01
for output). Use GPIOC base address with 0x00 offset value
(GPIOC_BASE+0x00) .
4. Write HIGH to PC8 in output data register(ODR). Use GPIOC base
address with 0x14 offset value (GPIOC_BASE+0x14) .
5. Call a delay function,
6. write LOW to PC8 in ODR.
7. Call a delay function
8. Repeat step 4 to 7
18
 GPIO Assembly Programming
area mydata, DATA
AHB1_BASE EQU 0x40020000
AHB2_BASE EQU 0x48000000
RCC_BASE EQU (AHB1_BASE+0x1000)
GPIOC_BASE EQU (AHB2_BASE+0x800)

area mycode, CODE

export __main
__main
LDR R0, =(RCC_BASE+0x14) ;Enable clock for GPIOC
LDR R1, =(1<<19)
STR R1, [R0]

LDR R0, =(GPIOC_BASE+0x00) ;GPIOC Pin#8 as a output mode

LDR R1, =(1<<8*2)
STR R1, [R0] 19
 GPIO Assembly Programming
LDR R1, =(1<<8) ; for pin#8 toggle purpose
LDR R2, =(1<<8)
LOOP
LDR R0, =(GPIOC_BASE+0x14)
EORS R1,R1, R2 ;toggle pin#08 by XOR operation
STR R1, [R0]

LDR R0, =1000000 ;to set delay of 1sec

Delay
SUBS R0, R0, #1
BNE Delay
B LOOP
END
Home Work:
2. Write an assembly program to toggle all bits of PORTC. 20
 GPIO Assembly Programming
Example#03: Write an assembly program for stm32f030R8 cortex-M0
ARM to read the switch on PA0(GPIOA, pin#0) and display it on the LED on
PC9.
area mydata, DATA
AHB1_BASE EQU 0x40020000
AHB2_BASE EQU 0x48000000
RCC_BASE EQU (AHB1_BASE+0x1000)
GPIOA_BASE EQU AHB2_BASE
GPIOC_BASE EQU (AHB2_BASE+0x800)

area mycode, CODE

export __main
__main
LDR R0, =(RCC_BASE+0x14) ;enable clock for GPIO A & C
LDR R1, =(5<<17)
STR R1, [R0]
21
 GPIO Assembly Programming
LDR R0, =(GPIOA_BASE+0x00) ;GPIOA as a input mode
LDR R1, =0x28000000
STR R1, [R0]

LDR R0, =(GPIOC_BASE+0x00) ;GPIOC as a output mode pin#9

LDR R1, =(1<<9*2)
STR R1, [R0]
LOOP
LDR R0, =(GPIOA_BASE+0x10)
LDR R2, [R0]
LSRS R2, R2, 1 ;read the status of GPIOA pin#0
BCS LED_ON
LDR R0, =(GPIOC_BASE+0x14)
LDR R1, =(0<<9)
STR R1, [R0]
B LOOP 22
 GPIO Assembly Programming
LED_ON
LDR R0,=(GPIOC_BASE+0x14)
LDR R1, =(1<<9)
STR R1, [R0]
B LOOP
END

23
 GPIO Assembly Programming
Example#04: Write an assembly program for stm32f030R8 cortex-M0
ARM for common-anode 7-segment Display connected to GPIOA(PA7-
PA0). Segment patterns for decimal digits are given in following table.
Segment patterns for the 10 decimal digits for a common anode 7-seg LED Display
Decimal PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Hex value
value . g f e d c b a
0 1 1 0 0 0 0 0 0 0xC0
1 1 1 1 1 1 0 0 1 0xF9
2 1 0 1 0 0 1 0 0 0xA4
3 1 0 1 1 0 0 0 0 0xB0
4 1 0 0 1 1 0 0 1 0x99
5 1 0 0 1 0 0 1 0 0x92
6 1 0 0 0 0 0 1 0 0x82
7 1 1 1 1 1 0 0 0 0xF8
8 1 0 0 0 0 0 0 0 0x80
9 1 0 0 1 0 0 0 0 0x90
24
 GPIO Assembly Programming
area mydata, DATA
AHB1_BASE EQU 0x40020000
AHB2_BASE EQU 0x48000000
RCC_BASE EQU (AHB1_BASE+0x1000)
GPIOA_BASE EQU (AHB2_BASE+0x00)
GPIOB_BASE EQU (AHB2_BASE+0x400)
GPIOC_BASE EQU (AHB2_BASE+0x800)

area mycode, CODE

export __main
__main
BL GPIO_init
BL Display_0
BL Delay
BL Display_1
BL Delay
BL Display_2 25
 GPIO Assembly Programming
BL Delay
BL Display_3
BL Delay
BL Display_4
BL Delay
BL Display_5
BL Delay
BL Display_6
BL Delay
BL Display_7
BL Delay
BL Display_8
BL Delay
BL Display_9
BL Delay
B __main
26
 GPIO Assembly Programming
GPIO_init
LDR R0, =(RCC_BASE+0x14)
LDR R1, =(7<<17)
STR R1, [R0]
LDR R0, =(GPIOA_BASE+0x00)
LDR R1, =0x00005555
STR R1, [R0]
LDR R2, =(GPIOA_BASE+0x14)
BX LR
Display_0
LDR R1, =0xC0
STR R1, [R2]
BX LR
Display_1
LDR R1, =0xF9
STR R1, [R2]
BX LR 27
 GPIO Assembly Programming
Display_2
LDR R1, =0xA4
STR R1, [R2]
BX LR
Display_3
LDR R1, =0xB0
STR R1, [R2]
BX LR
Display_4
LDR R1, =0x99
STR R1, [R2]
BX LR
Display_5
LDR R1, =0x92
STR R1, [R2]
BX LR
28
 GPIO Assembly Programming
Display_6
LDR R1, =0x82
STR R1, [R2]
BX LR
Display_7
LDR R1, =0xF8
STR R1, [R2]
BX LR
Display_8
LDR R1, =0x80
STR R1, [R2]
BX LR
Display_9
LDR R1, =0x90
STR R1, [R2]
BX LR
29
 GPIO Assembly Programming
Delay
LDR R0, =1000000
jump
SUBS R0, R0, #1
BNE jump
BX LR
END

HOME WORK:
3.Write an assembly program for stm32f030R8 cortex-M0 ARM for common-
cathode 7-segment Display.

30
Thanks

31