Computer Organization - Categorized
Exam Questions
Unit 1: Functional Units and Architecture
Exam Source (Q No.) Content of the Question
2024-25 Q1.a, Q1.b Basic functional units of a digital system;
General-purpose registers.
2024-25 Q2.a Data transfer between registers, buses, and
memory units (read/write operations).
2024-25 Q3.a Detailed overview of processor
organization (including cycles, pipelining).
2024-25 Q3.b Compare and contrast address buses, data
buses, and control buses.
2023-24 Q1.a Different types of Buses used in computer
architecture.
2023-24 Q2.a BUS arbitration; implementation in Daisy
chaining scheme.
2023-24 Q4.a Processor organization and various types.
2023-24 Q2.e, Q4.b Differences between Memory Stack and
Register stack.
2022-23 Q1.c Define bus and memory transfer.
2022-23 Q1.f Differentiate between RISC and CISC.
2022-23 Q2.a Explain functional units of computer
system in detail.
2022-23 Q3.a Explain stack organization and register
stack.
2022-23 Q3.b Effective address calculation in different
types of addressing modes.
2021-22 Q1.a Main structural components of a computer.
2021-22 Q1.c Represent conditional control statements
by register transfer statements.
2021-22 Q2.a Common bus system for 8 registers
(multiplexer calculation).
2021-22 Q4.a Draw a diagram of a Bus system using 3
state buffers and a decoder.
2021-22 Q4.b Explain multiple bus organization.
Unit 2: Arithmetic and Logic Unit
Exam Source (Q No.) Content of the Question
2024-25 Q1.c, Q1.d Explain floating point representation;
Discuss the role of ALU.
2024-25 Q2.b Describe Booth's algorithm for signed
binary multiplication.
2024-25 Q4.a Explain look-ahead carry adders; Compare
performance with ripple carry adders.
2024-25 Q4.b Discuss the process of signed operand
multiplication.
2023-24 Q1.b Name the different types of multipliers.
2023-24 Q2.b Show the multiplication process using
Booth's algorithm.
2023-24 Q4.a Explain principle of carry look ahead adder
and design 4-bit CLA Adder.
2023-24 Q4.b (i, ii) Represent decimal numbers in IEEE
standard floating-point format (single
precision).
2022-23 Q2.b Explain IEEE-754 standard for floating
point representation and express
(314.175)₁₀.
2022-23 Q4.a Describe the derivation procedure of look
ahead carry adder.
2022-23 Q4.b Show systematic multiplication of (-15) × (-
16) using Booth’s Algorithm.
2021-22 Q1.d Design a 4-bit combinational incremental
circuit using full adders.
2021-22 Q1.g Register value after arithmetic shift right
and arithmetic shift left.
2021-22 Q2.c Explain 2-bit by 2-bit Array multiplier;
Draw flowchart for divide operation.
2021-22 Q3.a Analysis and calculations related to a
binary floating-point number with biased
exponent.
2021-22 Q3.b Show multiplication of (+13) x (-15) using
Booth algorithm.
Unit 3: Control Unit
Exam Source (Q No.) Content of the Question
2024-25 Q1.e Discuss the micro operations.
2024-25 Q2.c, Q5.a Describe horizontal and vertical
microprogramming in control unit design.
2024-25 Q3.a Processor organization, covering
instruction fetch, decode, execute cycles,
and pipelining.
2024-25 Q5.b Explain the concept of microprogram
sequencing.
2023-24 Q1.c, Q1.d Different phases of an instruction cycle;
How control unit works.
2023-24 Q2.c What is pipelining? What are the different
stages?
2023-24 Q5.a Explain the different cycles of an
instruction execution.
2023-24 Q5.b Differentiate between hardwired and micro
programmed control unit.
2022-23 Q1.a, Q1.e List the steps involved in/Define an
instruction cycle.
2022-23 Q2.c Explain the concept of pipelining and its
types.
2022-23 Q5.a Evaluate arithmetic statement using Two,
One, and Zero address instructions.
2022-23 Q5.b Differences between hardwired and micro-
programmed control unit.
2021-22 Q1.b Differentiate between horizontal and
vertical microprogramming.
2021-22 Q1.j Different types of instruction formats.
2021-22 Q2.e Address selection for control memory.
2021-22 Q7.a Program to evaluate arithmetic expression
using 0-address instructions (stack).
2021-22 Q7.b Differences between hardwired and micro
programmed control; sequence of control
steps for an instruction.
Unit 4: Memory Organization
Exam Source (Q No.) Content of the Question
2024-25 Q1.f Explain the purpose of ROM memories.
2024-25 Q2.d Characteristics and functionalities of
auxiliary memories (magnetic disks, tapes,
optical disks).
2024-25 Q6.a Design and explain the fundamental
concept of computer memory hierarchy.
2024-25 Q6.b Architecture and operation of
semiconductor RAM (DRAM and SRAM).
2023-24 Q1.e, Q1.f Short note on locality of reference; Define 2
1/2 D memory organization.
2023-24 Q2.d Classification of memory;
construction/working of magnetic disk and
disk access time.
2023-24 Q6.a (i, ii) Cache (M1) and memory (M2) hierarchy:
mapping and calculating effective memory
access time.
2023-24 Q6.b (i, ii) Explain the direct mapping technique and
address format bit calculation.
2022-23 Q1.b How memory read and write operations
are performed.
2022-23 Q1.d, Q1.h Define HIT and MISS ratio; Define Virtual
memory.
2022-23 Q1.g Difference between static RAM and
dynamic RAM.
2022-23 Q2.d Cache block calculation for 2-way set
associative technique (fields).
2022-23 Q6.a Discuss the Memory Hierarchy (Speed, Size
and Cost).
2022-23 Q6.b Short notes on magnetic disk, magnetic
tape and optical disk.
2021-22 Q1.f Transfer rate calculation of magnetic tape.
2021-22 Q1.h, Q1.i Associative memory
(advantages/disadvantages); Differentiate
static RAM and Dynamic RAM.
2021-22 Q2.d Direct mapping cache calculations (address
fields, cache blocks).
2021-22 Q5.a Formulate logical and physical address
formats (segmentation/paging).
2021-22 Q5.b Virtual address mapping into physical
address; methods of writing into cache.
Unit 5: Input/Output (I/O)
Exam Source (Q No.) Content of the Question
2024-25 Q1.g Enlist the peripheral devices.
2024-25 Q2.e Functions and characteristics of I/O ports.
2024-25 Q7.a Role of peripheral devices, interaction with
CPU through I/O interfaces and ports.
2024-25 Q7.b Direct Memory Access (DMA) techniques
for data transfer.
2023-24 Q1.g Synchronous and asynchronous serial
modes of data transfer.
2023-24 Q3 Differences between interrupt initiated I/O
and programmed I/O.
2023-24 Q7.a Asynchronous data transfer: Explain strobe
control and handshaking mechanism.
2023-24 Q7.b Various modes of data transfer and discuss
DMA mode.
2022-23 Q1.i Functions performed by an Input/Output
unit.
2022-23 Q1.j Why DMA gets priority over CPU when
both request memory transfer.
2022-23 Q2.e Define interrupt and discuss different types
of interrupt.
2022-23 Q7.a Explain about DMA controller and its mode
of data transfer.
2022-23 Q7.b Discuss the design of a typical input or
output interface.
2021-22 Q1.e Differentiate between Daisy chaining and
centralized parallel arbitration.
2021-22 Q2.b Explain destination-initiated transfer using
handshaking method.
2021-22 Q6.a Explain how computer buses are used to
communicate with memory and I/O; Draw
block diagram for CPU-IOP communication.
2021-22 Q6.b Different methods of asynchronous data
transfer.
