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Third Scmester B.E./B.Tech. Degree Exatnination, June/July
Digital System Design u5ing Verilog
Time: 3 hrs. Max. Marks: 100
Note: I. Answer any FIVE firll questions, choosittg ONE Jitll question Jrom erch module.
2. M : Marks , L: Bloam's level , C: Course outconres.
Module -I M L C
Q.1 a. Design a combinational logic circuit which takes two,2-bit binary nunrbers 6 LI col
as its input and generates an output equal to l, when the sum ol' the two
b. Develop the canoqp$%rms for the following Boolehr equations: 6 LI col
i)
a + b (a * ii) (a + b) (c + d)
{".I&h.&
1;.
c. Find all prime implicants lbr the tt L2 col
fbllor.vi
i) r2, l_1. 14,15)
ii) s- , 14\
OR
Q.2 a. Simplify the fbllowing Boolean lunctions using k*rnap. f)raw tlre logic l0 L2 col
diagrarn {br the sirnplified equation:
i) w = f(a.b,c,d)= I(1,5,7,9,13,15)+Id(8,10,1 l,l4)
ii) :y f(a, b,",{] = n:(0, 2,3,4,5,12,13\ + pd(8,10)
-
b. Solve the folloffiipg Boolean funcX[quffiUV
-
usi ng Quinc-MC@,lusky mcthod. l0 L2 col
Verify uqingfr-mdp \li
r = fS&X,z) = Z(2,3, 4, 5, I }it-i) iT a(t, O. t 0, I I ) "
*{&h" ft t1,,
* P x'uce^Lu'Module*2
----_-
Q.3 ,l NOR Realize the follou,ing funotions using 3:8 decoder along n,ith OR andior
gates. In each **rb th" gates should be selected so as to minimize
,.
7 L2 co2
their total number of inputs.
I i) f,(a,b,c)= trm(1,3,6) and fr(a,b,c) :Im(2,5,7)
i
ii) f,(a,b,c) = IIM(0,3.5,6,7) and {i(a,b,c) = IIM(2,3,4"5,7)
I
b. Desigri a priority encoder fbr a system with three inputs, the nriddle bit with 5 L2 c02
highest priority sncoded as 10, MSB with next priority encoded as 1l and
LSB with least priority encoded as 0i. Write lhnctional table and its logic
diagram.
c. Explain carry look ahead adder with sigma block and necessary equations. 8 L2 co2
.6
& 1 of 3
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ttrrrr I lo OR
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''r,\ Q.4 ,
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lmplenrent tlrc function S = f(a,b,c,d) = I(1,3,4,11,12,13,14,15) using
i) 8:IMUX and ii) 16:l MUX
7 L2 co2
b. Design a single decade decimal adder with 8 L2 co2
c. Explain briefly Programmable Array Logic (PAL). 5 L2 co2
Module * 3
Q.s :1. Construct the logic diagram of master slave JK flipflop and its truth table. 8 L2 co3
Hxplain with necessary tirning diagram.
h. Construct Johnson counter using positive eilge tr iggered fliptlops and 8 L2 c()3
explain with necessary truth table.
l
c. Derive the characteristic equation of SR {iipflop. 4 L2 c03
OR
.10
Q.6 a. I:.xplain universal shift register with the help of logir: rliagram and rnode 1,2 co3
control tablc.
b. Dcsign a mod-6 synchronous counter with the sequence 10 L2 c03
0 * 2 *5 - 6* 4 * 3 using'l' flipflops.
Modulc - 4
Q.7 a. Explain the lbllorving data tlpes in verilog with example: 8 L2 co4
i) Nets ii) I{egisters iii) lnteger iv) Parameter &.
e.B
h. Evaluate the tbllowing if A:001 1, B:0100, E:4 and I;:2 6 L2 c04
i)A*B ii)A+B iii)E*+F iv)A&B yfai<z
vi) {A[3], B]
c. Write a verilog data fiou, model fbr full subtractor. 6 T,2 co4
OR
Q.8 l. E.plalfi th,ree ."yl.s of description availaStc i1 Verilog with halt'adder I L2 CU4
exarnple"
b. REalize 2x I rnultiplexef with active loW enat)le attd also write the Verilog 7 L2 c04
program by considering delay time to signal assignment statemenls Alsrl
draw simulation wdvelbrm.
c. Write a short note on *ig,*l uu.ti in verilog with an example. 4 L2 co4
Module - 5
Q.e a. l*ptarn the following sequential statements in verilog : i) I;or loop 8 L1 co4
ii) While loop iii) Repeat iv) Forever.
t). Write a vcrilog behavioral clescription fbr JK flipflop along with the design 8 L2 c04
and tirning diagram.
? o1'3
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/* )
1
c. F.xplain different case statements itl verilog' 4 c04
+
OR
a. -bit ripple carry adder using structural 8 1,2 co4
Q.10
description.
b. ftrr-1lre Uinary up-ao*n counter using verilog behavioral description. 7 L3 co4
c. Explain if:eise-if statenrent in vcrilog with an examplc. 5 L2 co4
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