SNS COLLEGE OF TECHNOLOGY
Coimbatore-35
An Autonomous Institution
Accredited by NBA – AICTE and Accredited by NAAC – UGC with ‘A++’ Grade
Approved by AICTE, New Delhi & Affiliated to Anna University, Chennai
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
23ITT301 MICROCONTROLLER AND EMBEDDED SYSTEMS
III YEAR/ V SEMESTER
8085 Timing Diagram
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Timing Diagram
• A time diagram is a graphical representation.
• The 8085 instruction timing diagram represents the execution time
of each instruction in graphical format.
• Execution time is given in T-states. The 8085 microprocessor has a
set of control signals and data signals that play an important role in
the execution of instructions.
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•Clock Signal: The time required to execute an instruction is called a clock
cycle.
•Machine Cycle: The time required to access memory or input/output devices
is called a machine cycle. The 8085 has 5 basic machine cycles i.e., load
opcode, read from memory, write to memory, read I/O, and write I/O.
•T-State: A machine cycle and an instruction cycle take several clock periods.
The portion of an operation performed in one system clock period is called a
T-state.
•Control Signals: The control signal controls the operations. Common signals
are ALE (address block enable), RD (read), WR (write), and IO/M
(input/output) memory.
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Machine Cycle of 8085
The 8085 microprocessor has 5 basic machine cycles.
They are :
•Opcode Fetch {4T- state}
•Memory Read {3T- state}
•Memory Write {3T- state}
•I/O Read {3T- state}
•I/O Write {3T- state}
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Each instruction of the 8085 processor consists of one to five machine
cycles, i.e., when the 8085 processor executes an instruction, it will
execute some of the machine cycles in a specific order.
The processor takes a definite time to execute the machine cycles. The
time taken by the processor to execute a machine cycle is expressed in
T-states.
One T-state is equal to the time period of the internal clock signal of
the processor.
The T-state starts at the falling edge of a clock.
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Opcode Fetch Machine Cycle
• Each instruction of the processor has one byte opcode.
• The opcodes are stored in memory. So, the processor executes the
opcode fetch machine cycle to fetch the opcode from memory.
• Hence, every instruction starts with opcode fetch machine cycle.
• The time taken by the processor to execute the opcode fetch cycle
is 4T.
• In this time, the first, 3T-states are used for fetching the opcode
from memory and the remaining T-states are used for decoding. &
execution.
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Opcode Fetch Machine Cycle:
It is the first step in the execution of any instruction. The timing diagram of this cycle is given
below.
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Memory Read Machine Cycle
• The memory read machine cycle is executed by the processor to read a
data byte from memory.
• The processor takes 3T states to execute this cycle.
• The instructions which have more than one byte word size will use the
machine cycle after the opcode fetch machine cycle.
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Figure : Memory Read Machine Cycle
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Memory Write Machine Cycle
• The memory write machine cycle is executed by the processor to write a
data byte in a memory location.
• The processor takes, 3T states to execute this machine cycle.
• The 8085 places the address (2065H) on the address bus
• Identifies the operation as a ‘memory write’ (IO/M=0, s1=0, s0=1).
• Places the contents of the accumulator on the data bus and asserts the signal
WR.
• During the last T-state, the contents of the data bus are saved into the
memory location.
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Figure : Memory write Machine Cycle
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I/O Read Cycle Of 8085
• The I/O Read cycle is executed by the processor to read a data byte
from I/O port or from the peripheral.
• The processor takes 3T states to execute this machine cycle.
• The IN instruction uses this machine cycle during the execution.
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Figure : I/O Read Machine Cycle
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I/O Write Cycle Of 8085
• The I/O write machine cycle is executed by the processor to write a data
byte in the I/O port or to a peripheral, which is I/O, mapped in the system.
• The processor takes, 3T states to execute this machine cycle.
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SUMMARY
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AP/ECE
