Verilog Data Types
In Verilog, there are several data types that you can use to represent different kinds of values
and signals. Here are some of the main data types available in Verilog:
1. Wire (wire): Wires are used to represent continuous signals. They're commonly used for
connecting different modules in a design and for carrying values between different parts
of a circuit.
wire a, b, result;
2. Reg (reg): Despite the name, reg is used to store values that can be changed and used in
sequential logic. It's often used to store state information in sequential circuits.
// 1 bit register
reg flag;
// 4 bit register
reg [3:0] counter;
3. Integer (integer): Integers are used to store whole numbers. They are mainly used for
tasks like counting, indexing, and loop control.
integer count;
4. Real (real): Real data type is used to store floating-point numbers, which include
numbers with fractional parts.
real temperature;
5. Time (time): Time data type is used to store time values, often used for modeling delays
and timing in simulations.
time delay;
Note: The following are not data types; they are data structure elements used as buses,
arrays, or memory constructs in Verilog.
6. Vector ([N:0] or [N: M]): Vectors are used to represent groups of bits. They can be used
to represent multi-bit buses or signals. N and M are the range of indices for the vector.
wire [7:0] data_bus; // 8-bit data bus
wire [2:0] control; // 3-bit control signal
// Splitting a 16-bit data into upper and lower parts
wire [15:8] upper_data, [7:0] lower_data;
7. Arrays ([N]): Arrays are used to store multiple values of the same data type. They can be
used for tasks like storing memory contents.
reg [7:0] memory[0:255]; // 1D Array
reg [7:0] graph[0:31][0:31] // 2D Array
8. Memory (reg [N:0] mem [M];): Used to model memory elements, where N is the bit-
width of each element and M is the number of memory elements.
reg [7:0] memory[255]; // 256-byte memory
These data types allow you to represent a wide range of values and signals within your
Verilog designs.
Verilog Building Blocks
1. Verilog Module:
A Verilog module is a self-contained unit that defines a specific functionality. It
serves as a blueprint for creating instances of that functionality in your design. Modules
encapsulate a set of logic, inputs, outputs, and potentially internal signals.
`module Adder (
input [3:0] A,
input [3:0] B,
output [4:0] Sum
);
// Logic to implement addition
endmodule`
2. Verilog Port:
Ports are the communication interfaces of a Verilog module. They define how
information flows in and out of the module. Ports can be inputs, outputs, or bidirectional.
`module Decoder (
input [2:0] Input,
output reg [7:0] Output
);
// Logic to decode the input signals
endmodule`
3. Verilog Module Instantiations:
Module instantiations are instances of a module created within another module.
They allow you to use the functionality defined in one module within another.
`module topModule;
Adder A1 (.A(inA), .B(inB), .Sum(sum));
Decoder D1 (.Input(selector), .Output(decodedOutput));
endmodule`
4. Verilog Assign Statements:
The assign statement connects a source to a destination, creating a continuous
assignment. It's used to connect wires or signals directly without using a procedural block.
`assign Sum = A + B;`
5. Verilog Always Block:
The always block defines procedural logic that executes whenever the conditions
specified within it are met. It's often used for sequential logic and state machines.
`always @(posedge clock) begin
if (reset) state <= IDLE;
else state <= next_state;
end
// always @(sensitivity list)`
The sensitivity list controls when all statements in the always block will start to be
evaluated. In the above always block the logic statements will be executed at each positive
edge of the clock signal.
6. Verilog Initial Block:
The initial block contains procedural code that's executed only once at the start of
simulation. It's used for setting initial values or performing setup tasks.
`initial begin
clk = 0;
reset = 1;
// Other initialization tasks
end`
These building blocks collectively allow you to create complex digital designs by defining the
structure, behavior, and interactions of different components in your Verilog code.
Blocking & Non-blocking assignment
Blocking and Non-blocking assignments controls the execution order within procedural
block statements. Blocking assignments are assigned using = and Non-blocking
assignments using <=. Both these assignments are used to generate combination or
sequential logic.
1. Blocking assignment
Execution: Blocking assignment statements execute sequentially, one after the other.
Each statement must complete before the next one in the same procedural block begins
execution.
Behavior: In a blocking assignment, the right-hand side is evaluated, and the result is
immediately assigned to the left-hand side variable within the same simulation time step.
In the always block below, blocking assignments are used. Here, the value 1 is
immediately assigned to x, and after a delay of 10 time units, x + 1 is evaluated and assigned
to y.
always @(posedge clk) begin
x = 1; // x is evaluated and assigned immediately.
#10;
y = x + 1; // After 10 time units, y is assigned the value
of x + 1.
end
2. Non-blocking assignment:
Execution: Non-blocking assignments are scheduled to occur at the end of the current
simulation time step. All right-hand side expressions for non-blocking assignments within a
block are evaluated at the beginning of the time step, and the actual assignments to the left-
hand side variables are performed concurrently at the end of that same time step.
Behavior: This two-step process allows for the modeling of concurrent hardware
behavior, where multiple assignments can effectively happen in parallel without one
blocking the others.
In the always block below, non-blocking assignments are used. In this example, the
value 1 is scheduled to be assigned to x at the end of the current time step, and after a delay
of 10 time units, x + 1 is evaluated and scheduled to be assigned to y at the end of that time
step.
`always @(posedge clk) begin
x <= 1; // Schedules x to be updated with 1 at the end
of the current time step.
#10;
y <= x + 1; // After 10 time units, schedules y to be
updated with x+1 at the end of that time step.
end`
Example:
To explain let's take an example of simple SISO (Serial In Serial Out)
always @(posedge clk) begin
q1 = d;
q2 = q1;
q3 = q2;
end
When you synthesized above code it would not result in 3 bit SISO. Instead it will result
in a single Flip Flop where q3 = d
always @(posedge clk) begin
q1 <= d;
q2 <= q1;
q3 <= q2;
end
When you synthesized above code it would result in 3 bit SISO.
Parameters
1. Parameter:
Parameters in verilog is nothing but a way to instantiate constants in the digital design.
Parameter is local to a module, but it can change value when the module is instantiated. It is
used to define a property of the module.
Syntax:
parameter parameter_name = constant_expression;
Example:
• parameter size = 4;
• parameter clk = freq / 2;
This property can be left to default or can be modified at instantiation of the module. For
example,
module adder (a, b, sum);
parameter width = 8;
input [width-1:0] a;
input [width-1:0] b;
output [width-1:0] sum;
assign sum = a + b;
endmodule
By default, the adder is 8-bit (the width parameter use the default assigned value of 8).
However, the instantiator module can change parameter value.
module top;
reg [15:0] a;
reg [15:0] b;
wire [15:0] sum1;
wire [15:0] sum2;
adder add1 (a, b, sum1);
defparam [Link] = 16;
adder #(16) add2 (a, b, sum2);
endmodule
2. Local Parameter:
local parameter localparam is also used to store the constant in the digital design but the
constant defined inside the module cannot be changed. (i.e from where the module is
instantiated).
Syntax:
localparam name = value;
Example:
• localparam len = width/12;
• localparam size = 16;
module adder (a, b, sum);
parameter height = 8;
parameter width = 10;
localparam length = 4;
input [width-1:0] a;
input [height-1:0] b;
input [length-1:0] c;
output [width-1:0] sum;
assign sum = a + b + c;
endmodule
module top;
reg [15:0] a;
reg [15:0] b;
wire [15:0] sum1;
//error as length is not accessible outside the module adder
adder #(.width(16), .height(4), .length(5) add_0 (a, b,
sum2));
endmodule
Verilog Conditional Statements
The conditional statements are used to determine whether particular statement should be
executed or not. Control statements in Verilog is similar to control statements in C.
1. if-else
If the expression in if condition is true then the statements inside the if condition will be
executed or if it is false the statements inside the else condition will be executed. \
Syntax:
if (expression)
[statement]
else
[statement]
if-else for multiple statements should be
if (expression) begin
[multiple statements]
end
else begin
[multiple statements]
end
Example:
always @(posedge clock) begin
if (reset) state <= IDLE;
else state <= next_state;
end
Similar to C, it is possible to have nested if statements in Verilog.
2. Conditional Operator
You can assign a value based on a condition by using the conditional operator.
Syntax:
variable = <condition> ? <expression1> : <expression2>
If the condition is true expression1 is assigned to the variable or else expression2 is
assigned to the variable.
