Features of RISC
Feature 1
RISC processors have a fixed instruction size.
In a CISC microcontroller such as the 8051, instructions can be 1, 2, or even 3 bytes.
For example, look at the following instructions in the 8051:
CLR C ;Clear Carry flag ;a 1-byte instruction
ADD Accumulator, #mybyte ;a 2-byte instruction
LJMP target_address ;a 3-byte instruction
This variable instruction size makes the task of the instruction decoder very difficult
because the size of the incoming instruction is never known.
In a RISC architecture, the size of all instructions is fixed.
Therefore, the CPU can decode the instructions quickly.
This is like a bricklayer working with bricks of the same size as opposed to using bricks
of variable sizes.
Of course, it is much more efficient to use bricks of the same size.
In the last section we saw how the PIC18 uses 2-byte instructions with very few 4-byte
instructions.
Feature 2
One of the major characteristics of RISC architecture is a large number of registers.
All RISC architectures have at least 32 registers.
Of these 32 registers, only a few are assigned to a dedicated function.
One advantage of a large number of registers is that it avoids the need for a large stack
to store parameters.
Although a stack can be implemented on a RISC processor, it is not as essential as in
CISC because so many registers are available.
In the PIC microcontrollers the use of a 256-byte bank for the file register satisfies this
RISC feature.
The stack for the PIC18 is covered in the next chapter.
Feature 3
RISC processors have a small instruction set.
RISC processors have only the basic instructions such as ADD, SUB, MUL, LOAD, STORE,
AND, OR, EXOR, CALL, JUMP, and so on.
The limited number of instructions is one of the criticisms leveled at the RISC processor
because it makes the job of Assembly language programmers much more tedious and
difficult compared to CISC Assembly language programming.
This is one reason that RISC is used more commonly in high-level language
environments such as the C programming language rather than Assembly language
environments.
It is interesting to note that some defenders of CISC have called it “complete instruction
set computer” instead of “complex instruction set computer” because it has a complete
set of every kind of instruction.
How many of these instructions are used and how often is another matter.
The limited number of instructions in RISC leads to programs that are large.
Although these programs can use more memory, this is not a problem because memory
is cheap.
Before the advent of semiconductor memory in the 1960s, however, CISC designers had
to pack as much action as possible into a single instruction to get the maximum bang for
their buck.
In the PIC16 we have around 35 instructions, while the PIC18 has 75 instructions.
We will examine more of the instruction set for the PIC18 in future chapters.
Feature 4
At this point, one might ask, with all the difficulties associated with RISC programming,
what is the gain?
The most important characteristic of the RISC processor is that more than 95% of
instructions are executed with only one clock cycle, in contrast to CISC instructions.
Even some of the 5% of the RISC instructions that are executed with two clock cycles
can be executed with one clock cycle by juggling instructions around (code scheduling).
Code scheduling is most often the job of the compiler.
We will examine the instruction cycle time and pipelining of the PIC18 in Chapter 3.
Feature 5
RISC processors have separate buses for data and code.
In all the x86 processors, like all other CISC computers, there is one set of buses for the
address (e.g., A0–A24 in the 80286) and another set of buses for data (e.g., D0–D15 in
the 80286) carrying opcodes and operands in and out of the CPU.
To access any section of memory, regardless of whether it contains code or data
operands, the same address bus and data bus are used.
In RISC processors, there are four sets of buses:
1) a set of data buses for carrying data (operands) in and out of the CPU,
2) a set of address buses for accessing the data,
3) a set of buses to carry the opcodes, and
4) a set of address buses to access the opcodes.
The use of separate buses for code and data operations is commonly referred to as
Harvard architecture.
In the last section we examined the Harvard architecture of the PIC18.
Feature 6
Because CISC has such a large number of instructions, each with so many different
addressing modes, microinstructions (microcode) are used to implement them.
The implementation of microinstructions inside the CPU takes more than 40–60% of
transistors in many CISC processors.
In the case of RISC, however, due to the small set of instructions, they are implemented
using the hardware method.
Hardwiring of RISC instructions takes no more than 10% of the transistors.
Feature 7
RISC uses load/store architecture.
In CISC microprocessors, data can be manipulated while it is still in memory.
For example, in instructions such as “ADD Reg, Memory”, the microprocessor must
bring the contents of the external memory location into the CPU, add it to the contents
of the register, then move the result back to the external memory location.
The problem is there might be a delay in accessing the data from external memory.
Then the whole process would be stalled, preventing other instructions from
proceeding in the pipeline.
In RISC, designers did away with these kinds of instructions.
In RISC, instructions can only load from external memory into registers or store
registers into external memory locations.
There is no direct way of doing arithmetic and logic operations between a register and
the contents of external memory locations.
All these instructions must be performed by first bringing both operands into the
registers inside the CPU, then performing the arithmetic or logic operation, and then
sending the result back to memory.
This was first implemented by the Cray 1 supercomputer in 1976 and is commonly
referred to as load/store architecture.
In the last section, we saw that the arithmetic and logic operations are between the
fileReg (an internal memory) and WREG but none involve a ROM location and a fileReg
location.
For example, there is no “ADDW ROM-Loc” instruction in PIC18.
