Week 2

The Microprocessor and its

Architecture
We are going to look at the
microprocessor as aprogrammable
device by first looking at its internal
programming model and then how its
memory space is addressed.

Real addressing mode will be covered.

Protected and flat modes are beyond
the scope of our course.
Internal MP architecture

Before a program is written In multiple core MP, each

or any instruction is core contains the same
investigated, the internal programming model. The
configuration of the only difference is that each
microprocessor must be core runs a separate task or
known. thread simultaneously.
The Programming Model

The programming model of

Other registers are program
8086 through Core2 is
invisible because they cannot
considered to be program
be addressed directly with
visible, because its registers are
application programming, but
used during applicatiojn
may be indirectly used during
programming and are specified
system programming.
by the instructions.
The programming model contains 8, 16, 32 and 64bit
registers.
• 8 bit registers: AH, AL, BH, BL, CH, CL, DH and DL
• These registers are referred to when an instruction is
formed using these two letter designations.
• ADD AL, AH; adds the 8 bit contents of AH to AL
• 16 bit registers: AX, BX, CX, DX, SP, BP, DI, SI, IP, FLAGS,
CS, DS, ES, SS, FS, GS
• The first four registers contain 2 x 8 bit registers.
• 32 bit registers: EAX, EBX, ECX, EDX, EDI, ESI, ….
• 64 bit registers are designated as RAX, RBX, …
• Some registers are general or multipurpose registers, while
some have special purposes. The multipurpose registers
include AX, BX, CX, DX, DI and SI.
There are also additional 64 bit registers Register Override Bits Example
that are called R8 to R15. Size Accessed
These registers can be addressed as 8 bits B 7-0 MOV R9B,
byte, word, double word or quadword; R10B
but only the rightmost 8bit as a byte. R8
16 bits W 15-0 MOV R10W,
to R15 have no provision for directly
AX
addressing bits 8-15 as a byte.
32 bits D 31-0 MOV R14D,
R15D
64 bits ---- 63-0 MOV R13,
R12
 • AX (Accumulator): 64 bits RAX, 32 bits EAX, 16 bits AX, 8 bits
AH or AL
• If an 8-16 register is addressed, only that portion of the
32 bit is changed without affecting the remaining bits.
• This register is used for instructions such as
multiplication, divsion and some adjustment instructions.
• BX (Base index): BX is addressable as RBX, EBX, BX, BH and BL.
• This register holds the offset address of a location in the
Multipurpose memory system.
• CX (Count): Addressable as RCX, ECX, CX, CH and CL.
Registers • It holds the count for various instructions. Instructions
that yse a count aare the repeated string instructions,
shift, rotate and loop instructions.
• Shift and Rotate CL
• Repeated string CX
• LOOP /LOOPD CX or ECX
• In 64 bit mode LOOP uses RCX register for the loop
counter.
DX (Data): RDX, EDX, DX, BP (Base Pointer): RBP, DI (Destination Index):
DH and DL. EBP or BP. RDI, EDI or DI.
• It holds part of result from a • It points to a moemory location • It addresses the string
multiplication or part of the for memory data transfers. destination data for string
dividend before a division. It can instructions.
also address memory data.

SI (Source Index): RSI, ESI

R8-R15: These registers or SI.
are only found in Pentium • It addresses the source string
4 and Core2 if 64 bit data for string instructions.
extensions are enabled.
 • IP (Instruction Pointer): This register addresses the next
Special instruction in a section of memory defined as code
segment.
Purpose • The instruction pointer can be modified with a jump or
call instruction. (IP, EIP, RIP)
Registers • SP (Stack Pointer): It addresses the stack area of the
memory. The stack memory stores data through this
pointer. (SP, ESP)
 These flags indicate the condition of the MP and control
its operation.

RFLAGS
The rightmost five flags and the overflow flag are changed
by most arithmetic and logic operations, although data
transfers do not affect them.

C (Carry): It holds carry after addition or borrow after

subtraction. It also indicates error conditions.

P (Parity): Parity is logic 0 for odd parity, 1 for even parity.

Parity is the count of 1’s in a number. This was mainly used
for earlier systems. Today parity checking is performed by
data communication equipment rather than the MP.
A (Auxiliary carry): The auxiliary carry holds the carry
(half carry) after addition or the borrow after
subtraction between bit positions 3 and 4 of the result.
• This flag is tested by DAA and DAS instructions to adjust the value of
AL after a BCD addition or subtraction.

Z (Zero): This flag shows that the result of an artihmetic

or logic operation is zero.

• IF Z==1 then the result is zero.

S (Sign): This flag holds the arithmetic sign of the result

after an arithmetic or logic instruction executes.

• If S==1 then sign bit (leftmost bit) is set and negative otherwise the
bit is cleared and positive
 T (Trap): The trap flag enables D (Direction): This flag selects either
I (Interrupt): This flag controls the
trapping through an on-chip the increment or decrement mode
operation of the INTR (interrupt
debugging feature. Visual C++ also for the DI and/or SI registers during
request) input pin.
use trap feature for debugging. string instructions.
•If I==1, interrupt is enabled. •If D=1, the registers are
•The state of this bit is controlled by automatically decremented,
STI and CLI instructions (set and otherwise automatically
clear). incremented.
•Set and cleared by STD and CLD
instructions.
 O (Overflow):
Overflows ocur
• For instance, if 7FH (+127) is added -using
when signed
an 8bit addition- to 01H (+1), the result is
numbers are added 80H (-128). This result represents an
or subtracted. An overflow condition.
overflow indicates
• For unsigned operations, this flag is
that the result
ignored.
exceeds the capacity
of the machine.

• If the current privilege level of the task or

IOPL (I/O Privilege program is lower or more trusted than
Level): IOPL is used the IOPL, I/O executes without hindrance.
in proted mode to • If the IOPL is lower than then program is
select the privilege suspended with an interrupt.
level of I/O devices. • 00 is the highest.
• 11 is the lowest.
NT (Nested Task): The nested task flag indicates that the
current task is nested within another task in the
protected mode.

RF (Resume): This flag is used with debugging to control

the resumptionof execution after the next instruction.

VM (Virtual Mode): It selects the Virtual Mode which

allow multiple DOS memory partitions that are 1Mbyte
in length to coexist in the memory system.
• It allows the system program to execute multiple DOS programs (to
simulate DOS in a modern Windows environment.)

AC (Alignment Checks): This flag activates if a word or

doubleword is addressed on a non-word or non-
doubleword boundary.
VIF (Virtual Interrupt): This is a copy of the
interrupt flag in Pentium 4.

VIP (Virtual Interrupt Pending): Available to P4

MPs. This is used in multitasking environments to
provide the OS with virtual interrupt flags.

ID (Identification): This flag indicates P4

microprocessors support the CPUID instruction.
This instruction provides the system with version
number and manufacturer information.
 These additional registers generate memory addreses when
combined with other registers.
Segment Registers
CS (Code Segment): The code segment is a section of memory that
holds the code (programs and procedures) used by the MP.

DS (Data Segment): The data segment is a section of memory that

contains most data used by a program. Data in this segment is
addressed by an offset address o the contents of other registers
that hold the offset address.

ES (Extra Segment): Additional data segment used by some of the

string instructions to hold destination data.
SS (Stack Segment): This register
defines the stack memory. Stack
entry point is determined by the
stack segment and stack pointer
registers. BP register also
addresses data within stack
segment.
FS and GS: Supplemental
registers. Windows uses these
registers for internal operations,
but no details are given.
 Real mode operation allows
the MP to address only the first
Real Mode 1Mbyte of memory space.
Memory
Addressing
Windows does not use real
mode.
 A combination of segment address and an
offset address accesses a memory location
in the real mode.

The segment address, located within one of

Segments and the segment registers, defines the beginning
Offsets address of any 64Kbyte memory segment.

The offset address selects any location

within the 64Kbyte memory segment.
• The memory segment starts with 10000H and ends at
1FFFFH (64Kbytes).
• Note that the segment register contains 1000H, but it
addresses a starting segment at location 10000H.
• In the real mode, each segment register is internally
appended with 0H on its rightmost end. The MP must
generate a 20bit address to access a location within the
first 1Mbyte memory.
• Because the length of real mode segment is 64K, once
the beginning address is known, the ending address is
found by adding FFFFH (= 65535).
 Segment
Starting Address Ending Address
Register
2000H 20000H 2FFFFH
2001H 20010H 3000FH
2100H 21000H 30FFFH

• The offset address is always added to the starting address of the segment to
locate the data. The segment and offset address is sometimes written as
1000:2000 for a segment address of 1000H with offset of 2000H.
 • The MP has a set of rules that apply to segments whenever
memory is addressed.
Default • For instance, the code segment register is always used with
the instruction pointer.
Segment and • CS:IP
• The code segment defines the start of the code
Offset segment and instruction pointer locates the next
Registers instruction in this segment.
• If CS=1400H and IP=1200H, the address of the next
instruction is 14000H+1200H = 15200H
• Another default combination is the stack. (SS:SP). BP can
also be used here.
• For SS=2000H and BP=3000H then 23000H is the
address to access in the stack segment.
Segment Offset Special Purpose
CS IP Instruction address
SS SP or BP Stack address
DS BX, DI, SI, an 8/16 bit Data address
number
ES DI for string instructions String destination address
 This complicated scheme of
segment plus offset addressing
allows DOS programs to be
relocated in the memory
system. It also allows programs
written to function in the real This is ideal for use in a general-
mode to operate in a protected purpose computer system in
mode system. which not all machines contain This is also important for
The segment and offset addressing may look
•A relocatable program is one that can the same memory areas. The implementing swapping
complicated. However, it offers an
be placed into any area of memory and personal computer memory operation or paging for virtual
advantage to the system. executed without change. structure is different from memory.
•Relocatable data are data that can be machine to machine, requiring
placed in any area of memory and used
without any change to the program. relocatable software and data.
The segment and offset addressing
scheme allows both programs and data
to be relocated without changing a
thing in a program or data.
 What’s the FLAGS Register?

Extra The FLAGS register is like the microprocessor’s status

dashboard. After most arithmetic or logic instructions
(like ADD, SUB, CMP), it updates specific bits to show
what happened - did the result hit zero? Was there a
carry? Did the result go negative? These flags then
guide what the program does next, like jumping to a
different instruction if a condition (e.g., “zero result”)
is met. Data transfer instructions (like MOV) don’t
touch the flags, but most math and logic ops do.
 Here’s a quick recap of the flags we’re focusing on, based on the
document:

Carry (C): Set if there’s a carry out (addition) or borrow (subtraction). Also
signals errors in some cases.

Key Flags and Parity (P): Set to 1 for even parity (even number of 1s in the result), 0 for
odd. Mostly used in older systems for error checking.
Their Roles Auxiliary Carry (A): Tracks carry or borrow between bits 3 and 4 (used for
BCD arithmetic).

Zero (Z): Set to 1 if the result is zero, 0 otherwise.

Sign (S): Reflects the leftmost bit (sign bit) of the result: 1 for negative, 0
for positive.

Overflow (O): Set when a signed arithmetic result exceeds the register’s
capacity (e.g., adding two large positive numbers gives a negative result).
 The 8086 programming model has evolved through 80286, 80386, Pentium, and Core2
processors.

Evolution of the Core count increased, but the core programming model remains consistent for
compatibility.

Programming
Model 64-bit extensions (e.g., RAX, R8-R15) were added in Pentium 4 and Core2 for larger data
handling.

Backward compatibility ensures older 16-bit and 32-bit code can still run.

This slide introduces how the programming model has grown over time while keeping the
core structure intact. It emphasizes why the 8086 model is still relevant and how 64-bit
registers like RAX or R8-R15 expand capabilities without breaking older software. Keep it
visual with a timeline graphic showing 8086 to Core2.
 Registers like AX, BX, CX, and DX often team up for complex operations.

How Registers Example: Multiplication uses AX for input and DX:AX for the result.
Work
Together String instructions pair DI (destination) and SI (source) with segment registers.

FLAGS register updates automatically to reflect operation outcomes (e.g., Zero, Carry).

This slide shows how registers aren’t standalone - they collaborate. For instance, MUL
(multiply) might store a result across DX and AX, while string operations rely on DI and SI.
A simple diagram of registers interacting (e.g., AX → DX:AX for multiplication) would
make this pop visually.
 RFLAGS holds multiple flags: Carry, Parity, Zero, Sign, Overflow, etc.

Understanding
the FLAGS Each flag is a single bit, set or cleared based on operation results.

Register Example: ADD 127 + 1 sets Overflow (signed) but not Carry (unsigned).

Flags control program flow (e.g., jumps like JZ for “jump if zero”).

Dive deeper into the FLAGS register since it’s critical for decision-making in programs.
Explain how flags like Zero or Sign trigger conditional instructions. A table showing flag
states after an example operation (like ADD 7FH + 01H) would clarify this.
 • Stack grows downward (higher address to lower) using
SS:SP.
Stack • PUSH stores data on the stack; POP retrieves it.
• Example: PUSH AX decrements SP by 2 and stores AX
Operations in at SS:SP.
• Stack is critical for function calls and saving register
Real Mode states.
The stack is a big deal for managing data temporarily, so this
slide explains how SS and SP work together in real mode. A
diagram showing the stack growing downward with
PUSH/POP operations would help visualize it.
 • Real mode is capped at 1 MB (00000H to FFFFFH).
• 64 KB segments (FFFFH size) limit data and code
blocks.
Real Mode • Segment:Offset addressing allows access to any byte
within 1 MB.
Memory Limits • Modern systems rarely use real mode due to its
limitations.
Reinforce why real mode’s 1 MB limit exists and how
segment:offset gets around it. Mention that DOS relied on
this, but Windows doesn’t. A memory map showing the 1 MB
range with a few segment examples would be useful.
 • Physical address = (Segment × 16) + Offset.
• Example: CS=1000H, IP=2000H → 1000H × 10H =
Segment:Offset 10000H + 2000H = 12000H.
• Multiple segment:offset pairs can point to the same
Address physical address.
Calculation • This flexibility enables relocatable code and data.

Break down the math of segment:offset addressing with a

clear example. Show how 1000:2000 and 1200:0000 might
point to the same address (12000H). A formula and example
calculation would make this slide clear.
 • Relocatable programs run anywhere in memory
Relocatable without modification.
• Segment:Offset allows code to reference memory
Programs in relative to a starting point.
• Example: A program at CS=2000H or CS=3000H works
Action the same.
• Key for DOS multitasking and memory flexibility.
Expand on why relocatability matters for real mode. Show
how segment:offset makes it possible to move code without
rewriting it. A simple diagram of the same program loaded at
different segment addresses would drive this home.