CPS 705: Computer Architectures

Professor Victor Eshiet Ekong

[email protected]
+220-5072264
School of Information Technology and
Communications
University of The Gambia
© 2025
CPS 705 Course Information
 Course Title: Computer Architectures
 Course Code: CPS 705
 Credit Hours: 3 Credits
 Hrs: Mins: 2 hrs. 30mins
 Course Duration: 10 Weeks
 Day/Time: Tues: 11am-1.30pm
 Venue: Kanifing, Peace Building

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 CPS 705 Course Information
 Textbook References
 William Stallings (2013) Computer Organization and Architecture-Designing for Performance, 9th Edition,
Pearson Higher Education. ISBN 13: 978-0-13-293633-0
 Nicholas Carter (2001) Computer Architecture, Schaum’s outline series, McGraw-Hill, ISBN: 0417-136207-
X.
 John L. Hennessy and David A. Patterson (2012), Fundamentals of Computer Design" from Computer
Architecture: A Quantitative Approach, 5th ed. Elsevier, USA. ISBN: 978-0-12-383872-8

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

About Your Instructor
 Prof. Victor Eshiet Ekong
 Office hours: 10:00AM-5:00PM [Mon-Friday]
 Office Phone#: (+220)5072264
 Background:
 Artificial Intelligence
 Software Engineering
 Information technology
 Multi-disciplinary

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Course Objectives
 Understand the basic components and organization of a computer
system.
 Learn the principles of instruction set architecture (ISA) and its
impact on performance.
 Explore the design and functioning of processors, including
pipelining and parallelism.
 Analyze memory hierarchy, caching, and virtual memory systems.
 Examine input/output systems and their interaction with the CPU
and memory.
 Gain insights into parallel and multicore architectures.
 Develop the ability to evaluate and compare different computer
architectures.
Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong
 Learning Outcomes
 Understand the fundamental principles of computer
architecture and organization.
 Be able to design and analyze basic processor and memory
systems.
 Gain practical experience in assembly language programming
and processor simulation.
 Develop an appreciation for the challenges and trends in
modern computer architecture.
 Be prepared for advanced studies in computer engineering,
embedded systems, and parallel computing.

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Lecture Two
Instruction Set Architecture (ISA)
 Types of ISA:
 CISC vs. RISC.
 Instruction formats
 addressing modes, and operations.
 Assembly language programming.
 Case studies: MIPS, x86, and ARM architectures

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Instruction Set Architecture (ISA)
 ISA is an abstract interface between the hardware and the lowest level
software of a machine that encompasses all the information necessary
to write a machine language program that will run correctly, including
instructions, registers, memory access, I/O, and so on.
 It is the interface between hardware and software.
 It defines how a processor understands and executes instructions,
acting as the bridge that allows programs written in high-level
languages to be executed by the CPU.

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Components of an ISA
 Instruction Set – The collection of operations (e.g., ADD, SUB,
LOAD, STORE).
 Data Types – Defines the type and size of data handled (e.g., integer,
float, double).
 Registers – Small storage locations within the CPU used for fast data
access.
 Addressing Modes – Methods to specify where operands are
located (e.g., immediate, direct, indirect).
 Memory Model – Defines how memory is addressed and organized.
 Instruction Formats – Defines how bits are arranged in an
instruction (opcode, operands, etc.).
 I/O Mechanisms – Defines how input and output operations are
performed
Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong
 Intel 8085/86 ISA
 Every processor design is based on one specific ISA
 This only defines the operational capacity of the processor in terms of
sets of commands that the processor can decode and execute
 Intel 8085/86 processor ISA consists of 246 operation codes and 74
instructions

Figure 2: Intel 8085/86 CPU ISA

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong
 CPU Microarchitecture
 The processor architecture at the hardware level is also referred to as a
microarchitecture which defines the ISA
 The microarchitecture is the hardware circuitry of the processor chip
that implements one particular ISA
 The ISA does not specify the actual implementation details
 The chip manufacturing brand are responsible for deciding how to
implement the ISA onto the computer’s microarchitecture design.

Figure 3: Different brands of Intel microarchitecture and an implementation

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong
 Types of ISA
They are four types:
 CISC (Complex Instruction Set Computer)
 RISC (Reduced Instruction Set Computer)
 Very long Instruction word (VLIW)
 Explicitly parallel Instruction Computing (EPIC)

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 CISC
These are early Intel x86, IBM z/ machines
Characteristics
 Complex instructions (single instruction does multiple operations).
 Variable-length instructions (1–15 bytes).
 Memory-to-memory operations (e.g., ADD [A], [B]).

Advantages
 It makes compact code
 Uses fewer instructions per program
Disadvantages
 Requires complex hardware
 It uses higher power consumption

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 RISC
These are MIPS and ARM machines
Characteristics
 Simple and small number of instructions.
 Each instruction executes in one clock cycle.
 Focus on efficiency and speed.
 They utilize fixed-length instructions (e.g., 32-bit in ARM).
 Load/Store architecture (only LOAD/STORE access memory).
 Pipelining-friendly (faster clock rates).
Advantages
 Easier pipelining, faster execution
 They are energy-efficient
 They are easier to optimize
Disadvantage
 They use more instructions needed for complex tasks.

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 VLIW
 VLIW (Very Long Instruction Word) is a type of ISA that allows multiple
operations to be executed in parallel within a single processor cycle.
 Unlike traditional architectures (CISC or RISC) that execute one
instruction per cycle, VLIW packs several independent operations into
one long instruction word.
Characteristics
 Executes several instructions in one clock cycle.
 Each instruction word is very wide (e.g., 64, 128, or 256 bits).
 The compiler identifies and schedules independent instructions.
 Does not require complex runtime scheduling or dependency checking.

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 VLIW
Advantages
 Achieves parallel execution without complex hardware.
 No dynamic scheduling or dependency checking needed.
 Easier to optimize for embedded and real-time systems.
 Compiler performs instruction scheduling and dependency analysis.

Disadvantages
 Large instruction words lead to increased memory usage.
 The compiler must detect and schedule parallel operations effectively.
 Different implementations may require recompilation.
Examples: Intel Itanium (IA-64), Texas Instruments TMS320C6x DSPs,
etc.

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 EPIC
EPIC (Explicitly Parallel Instruction Computing) is a computer
architecture paradigm designed to enhance instruction-level parallelism
(ILP) by allowing the compiler to explicitly specify which instructions can
be executed in parallel.
Characteristics
 Register Rotation: Enables efficient implementation of loops and
pipelined operations.
 Instructions are grouped into fixed-size bundles (typically 128 bits) that
describe parallel execution
Advantages
 Higher Parallelism as compiler exploits more ILP by static scheduling.
 Reduced Hardware Complexity as complex runtime scheduling units are
reduced.
Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong
 EPIC
Advantages
 Power efficiency as lower power consumption compared to superscalar
CPUs are added
 Deterministic execution, making it easier to predict performance,
especially in real-time systems.

 Examples: Intel Itanium IA-64, Trimaran

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Instruction Format
 This is a design concept that is part of the processor architecture
 A program, which is a set of instructions that directs the CPU to perform a specific
set of operations.
 However, the computer only executes low level machine instruction in a binary
format
 All high level language are first compiled, interpreted or translated
 The computer translates the program instruction into low level machine instruction
in binary format.
 The instruction format defines the machines instruction in terms of operation code,
operands and addressing mode

Figure 4: Instruction format

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong
 Instruction Format
 Figure 5 shows a 16-bit instruction format

Figure 5: A 16-bit Instruction format

 The instruction format supported by the processor depends on the ISA of the processor
 Therefore, the processor can support the instruction format that are compatible with its
instruction set architecture as shown in Figure 6..

Figure 6: The instruction format is compatible with the ISA

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong
 Instruction Set Design Issues
 The number of explicit operands
 0, 1, 2, 3
 ADD R1 1 address instruction
 ADD R1, R2 2 address instruction
 ADD R1, R2, R3 3 address instruction
 ADD zero address instruction
 ADD R1, LOC A
 Location of the operands
 Registers, Accumulator or memory
 Specification of operand locations
 Addressing modes: register, immediate, direct, relative, etc.
 Size of the operands supported
 Byte (8bits), Half word (16 bit),Word (32 bits), Double (64 bits)
 Supported operations
 ADD, MUL, SUB,AND OR, CMP, MOVE, STORE, LOAD, JMP, etc.

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Evolution of Instruction Sets
SN Type Period Examples
1 Accumulator based 1960’s EDSAC, IBM 1130
2 Stack based 1960-70 Burroughs 8000
3 Memory-to-Memory based 1970-1980 IBM 360
4 Register-to-Memory based 1970 - date Intel X86
5 Register -to -Register based 1970 - date MIPS, CDC 6600,
SPARC

 Accumulator Based systems

 ADD R1 means R1 + ACC => ACC
 ACC – Register
 ADD X => ACC=ACC + MEM[X]
 Stack based systems
 ADD =>
 0 address instruction
 ADD =>TOS = TOS + NEXT

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Evolution of Instruction Sets
 Memory –to- Memory based systems
 2 or 3 address instructions
 ADD A, B => MEM[A] = MEM[A] + MEM[B]
 ADD A, B, C => MEM[A] = MEM[B] +MEM[C]

 Register –to- Memory Based systems

 2 address instruction
 LOAD R1, X => R1=MEM[X]

 Register –to-Register based systems

 3 address instruction
 ADD R1, R2, R3 => R1=R2+R3

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 EXAMPLES
Consider the code sequence Z=X+Y
 Stack based system
PUSH X
PUSH Y
ADD
POP Z
 The ADD instruction pops 2 elements from the stack, adds them and push back the result

 Accumulator based system

LOAD X // ACC = MEM[X]
ADD Y // ACC=ACC+ MEM[Y]
STORE Z // MEM[Z]=ACC
 All instructions assume that one of the operands (and also called the result) is in a special
register called Accumulator

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 EXAMPLE
Considering the code sequence Z=X+Y
 Register –to- Memory Based system
LOAD R2, X //R2=MEM[X]
ADD R2,Y // R2 = R2+ MEM[Y]
STORE Z, R2 // MEM[Z]=R2
 One of the operands is assumed to be in register and another in memory

 Register –to- Register based system

LOAD R1, X // R1 = MEM[X]
LOAD R2,Y // R2= MEM[Y]
ADD R3, R2, R1 // R3= R2 +R1
STORE Z, R3 // MEM[Z]= R3
 This is also called LOAD – STORE architecture as only LOAD and STORE instructions
can access memory

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Issues on General Purpose Registers
 Older architectures had large number of special purpose registers:
 Program counters, stack pointers, instruction registers , flag registers, index
registers, accumulators, etc.
 Newer architectures in contrast have a large number of general purpose registers
Why?
 Easy for the compiler to assign some variable to registers
 Registers are much faster than memory
 More compact instruction encoding as fewer bits are required to specify registers
 Many processors have 32 or more GPRs
The Pros and Cons of Registers
 The LOAD-STORE architecture form the basis for the RISC ISA such as MIPS
(Microprocessors without Interlocked Pipeline Stages)
 It helps reduce memory traffic once the memory data are loaded onto the register
 Compiler are generate very efficient code
 Additional overload for save/restore returns
 Many registers are used to save and restore

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 What are Addressing Modes?
 They specify the mechanism by which the operands data can be located
 Some ISAs are quite complex and support many addressing modes
 ISAs based on Load-Store architecture are usually simple and support
very limited number of addressing mode
 Various addressing modes exists:
 Immediate, Direct, Register, Register Indirect, Indexed, Stack, Based,
Relative, Auto-increment, Auto-decrement etc.
 Not all processors support all addressing modes

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Immediate Addressing
 Here, the operand is part of the instruction itself
 No memory reference is required to access the operand
 It is fast but has limited range (because a limited number of bits are
provided to specify the immediate data)
Example:
ADD #20 //ACC =ACC +20
ADDi R1, R2,30 //R1=R2+30

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Direct Addressing
 Here, the instruction contains a field that holds the memory address of
the operand

Example:
ADD R1, 14A16H //R1 =R1 +MEM[14A16H]
 A single memory access is required to access the operand
 No additional calculation is required to declare the operand address
 Limited address space (as number of bits is limited to say, 16 bits)

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Indirect Addressing
 The instruction contains a field that holds the memory which in turn
holds the memory address of the operand
 Two memory addresses are required to get the operand value
 It is slower, but can access larger address space
 It is not limited by the number of bits in the operand address like direct
addressing
Example:
ADD R1, (14A16H) //R1 =R1 +(MEM[14A16H])

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Register Addressing
 This again is a straight-forward addressing scheme
 The operand is held in a register and the instruction specifies the register number
 Very few number of bits is required as the number of registers are limited
 Faster execution, since no memory access is required for getting the operand
 Modern Load-Store architectures support large number of registers
Example:
ADD R1, R2, R3 //R1 =R2 + R3
MOV R2, R5 // R2=R5

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Register Indirect Addressing
 The instruction specifies a register, and the register holds the memory address where
the operand is stored
 Can access large address space
 One fewer memory access as compared to the indirect addressing
Example:
ADD R1, (R5) // R1 = R1 +MEM[R5])

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Relative Addressing (PC Relative)
 The instruction specifies an offset of displacement which is added to the PC to get
the effective address of the operand
 Since the number of bit to specify the offset is limited, the range of relative addressing also
limited.
 If a 12-bit offset for example is specified it can have values ranging from -2048 to +2047

Example:
ADD R1, (R5) // PC = R1 +(MEM[R5])

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Indexed Addressing
 Either a special purpose register or a GPR is used as index register in this
addressing mode
 The instruction specifies an offset of displacement, which is added to the index
register to get the effective address of the operand.
 Can be used to sequentially access the elements of an array
 Offset gives the starting address of the array and the index register value specifies the array
element to be used.
Example:
LOAD R1, 1240(R3) // R1 = MEM[1240+R3]

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Stack Addressing
 The operand is implicitly on top of the stack
 It is used in zero address machines as earlier stated.
 Many processor have a special register called the stack pointer (SP) that keeps track
of the stack top in memory
 PUSH, POP, CALL, RET instructions automatically modiFy SP.
Example:
ADD
PUSH X
POP X

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Other Addressing Modes
Base Register
 The processor has a special register called base register or segment register
 All operands addresses generated are added to the base register to get the final
memory address
 It allows easy movement of code and data in memory

Auto-increment and Auto-decrement Register

 They were first introduced in the PDP-11 computer systems
 The register holding the operand addresses is automatically incremented or
decremented after accessing the operand like in (a++ or a- - in C)

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 QUESTIONS!

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong

 Next Class
 Binary number representation and arithmetic.
 Design of ALU for integer and floating-point operations.
 Overflow, underflow, and rounding.

38 Lecture Notes on MIS 707 – Advanced I S A D - Prof. Victor Ekong

 Revision Exercise
 What is an Instruction Set Architecture (ISA)? Explain its role in computer architecture.
 Compare RISC and CISC architectures. What are the key differences in their design
philosophies?
 What are the typical components of a machine instruction? Explain opcode, operands, and
addressing mode fields.
 How does the choice of ISA affect processor performance? Discuss factors like instruction
complexity, pipeline efficiency, and power consumption.

Lecture Notes on CPS 705 – Computer Architectures - Prof. Victor Ekong