a LC2MOS

12-Bit Serial DACPORT

AD7243
FEATURES FUNCTIONAL BLOCK DIAGRAM
12-Bit CMOS DAC with
VDD
On-Chip Voltage Reference
Output Amplifier
Three Selectable Output Ranges
2R
–5 V to +5 V, 0 V to +5 V, 0 V to +10 V REFOUT
R OFS
Serial Interface
2R
300 kHz DAC Update Rate
VOUT
Small Size: 16-Lead DIP or SOIC 12 - BIT DAC
Nonlinearity: ⴞ1/2 LSB T MIN to T MAX REFIN
12
AGND
Low Power Dissipation: 100 mW Typical
AD7243 DAC LATCH
APPLICATIONS 12 DGND
Process Control
INPUT SHIFT REGISTER
Industrial Automation VSS
Digital Signal Processing Systems
Input/Output Ports
SDIN CLR BIN/ SCLK SYNC LDAC DCEN SDO
COMP

GENERAL DESCRIPTION The AD7243 is fabricated on Linear Compatible CMOS

The AD7243 is a complete 12-bit, voltage output, digital-to- (LC2MOS), an advanced, mixed technology process. It is pack-
analog converter with output amplifier and Zener voltage refer- aged in 16-lead DIP and 16-lead SOIC packages.
ence on a monolithic CMOS chip. No external trims are
required to achieve full specified performance. PRODUCT HIGHLIGHTS
The output amplifier is capable of developing +10 V across a 1. Complete 12-Bit DACPORT®
2 kΩ load. The output voltage ranges with single supply opera- The AD7243 is a complete, voltage output, 12-bit DAC on
tion are 0 V to +5 V or 0 V to +10 V, while an additional bipo- a single chip. The single chip design is inherently more
lar ± 5 V output range is available with dual supplies. The ranges reliable than multichip designs.
are selected using the internal gain resistor. 2. Single or Dual Supply Operation.
The data format is natural binary in both unipolar ranges, while 3. Minimum 3-wire interface to most DSP processors.
either offset binary or two’s complement format may be selected 4. DAC Update Rate–300 kHz.
in the bipolar range. A CLR function is provided which sets the
output to 0 V in both unipolar ranges and in the two’s comple- 5. Serial Data Output allows easy daisy-chaining in multiple
ment bipolar range, while with offset binary data format, the DAC systems.
output is set to –REFIN. This function is useful as a power-on
reset as it allows the output to be set to a known voltage level.
The AD7243 features a fast versatile serial interface which
allows easy connection to both microcomputers and 16-bit digi-
tal signal processors with serial ports. The serial data may be
applied at rates up to 5 MHz allowing a DAC update rate of
300 kHz. A serial data output capability is also provided which
allows daisy chaining in multi-DAC systems. This feature allows
any number of DACs to be used in a system with a simple
4-wire interface. All DACs may be updated simultaneously
using LDAC.

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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 (VDD = +12 V to +15 V,1 VSS = 0 V or –12 V to –15 V,1 AGND = DGND = O V, REFIN = +5 V,
AD7243–SPECIFICATIONS RL = 2 k⍀, CL = 100 pF to AGND. All Specifications TMIN to TMAX unless otherwise noted.)
Parameter A2 B2 S2 Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 12 12 12 Bits
Relative Accuracy 3 ±1 ± 1/2 ±1 LSB max
Differential Nonlinearity3 ± 0.9 ± 0.9 ± 0.9 LSB max Guaranteed Monotonic
Unipolar Offset Error3 ±4 ±4 ±5 LSB max VSS = 0 V or –12 V to –15 V 1; DAC Latch
Contents All 0s
Bipolar Zero Error3 ±5 ±5 ±6 LSB max VSS = –12 V to –15 V1; DAC Latch Contents All 0s
Full-Scale Error3, 4 ±6 ±6 ±7 LSB max
Full-Scale Temperature Coefficient 5 ±5 ±5 ±5 ppm of FSR/ Guaranteed By Process
°C typ
REFERENCE OUTPUT
Reference Output Range, REFOUT 4.95/5.05 4.95/5.05 4.95/5.05 V min/V max
Reference Temperature Coefficient5 ± 25 ± 25 ± 30 ppm/°C typ Guaranteed By Process
Reference Load Change
(∆REFOUT VS. IL) –1 –1 –1 mV max Reference Load Current (I L) Change (0–100 µA)
REFERENCE INPUT
Reference Input Range, REFIN 4.95/5.05 4.95/5.05 4.95/5.05 V min/V max 5 V ± 1% for Specified Performance
Input Current 5 5 5 µA max
DIGITAL INPUTS
Input High Voltage, VINH 2.4 2.4 2.4 V min
Input Low Voltage, V INL 0.8 0.8 0.8 V max
Input Current, IIN ±1 ±1 ±1 µA max VIN = 0 V to VDD
Input Capacitance5 8 8 8 pF max
DIGITAL OUTPUT
Serial Data Out (SDO)
Output Low Voltage, VOL 0.4 0.4 0.4 V max ISINK = 1.6 mA
Output High Voltage, V OH 4.0 4.0 4.0 V min ISOURCE = 400 µA
ANALOG OUTPUT
Output Range Resistor, ROFS 15/30 15/30 15/30 kΩ min/max Typically 20 k⍀. Guaranteed By Process
Output Voltage Ranges 6 +5, +10 +5, +10 +5, +10 V Single Supply; VSS = 0 V
Output Voltage Ranges 6 +5, +10, ±5 +5, +10, ± 5 +5, +10, ± 5 V Dual Supply; VSS = –12 V to –15 V
DC Output Impedance 5 0.5 0.5 0.5 Ω typ
AC CHARACTERISTICS 5
Voltage Output Settling-Time Settling Time to Within ± 1/2 LSB of Final Value
Positive Full-Scale Change 10 10 10 µs max Typically 4 µs
Negative Full-Scale Change 10 10 10 µs max Typically 5 µs
Digital-to-Analog Glitch Impulse 3 30 30 30 nV secs typ DAC Latch Contents Toggled Between All 0s
and All 1s
Digital Feedthrough3 10 10 10 nV secs typ LDAC = High
POWER REQUIREMENTS
VDD Range +10.8/+16.5 +10.8/+16.5 +11.4/+15.75 V min/V max For Specified Performance Unless Otherwise Stated
VSS Range (Dual Supplies) –10.8/–16.5 –10.8/–16.5 –11.4/–15.75 V min/V max For Specified Performance Unless Otherwise Stated
IDD 10 10 10 mA max Output Unloaded; Typically 7 mA
ISS (Dual Supplies) 2 2 2 mA max Output Unloaded; Typically 1 mA

NOTES
1
Power Supply Tolerance A, B Versions: ± 10%; S Version: ± 5%.
2
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
3
See terminology.
4
Measured with respect to REFIN and includes unipolar/bipolar offset error.
5
Guaranteed by design and characterization, not production tested.
6
0 V to +10 V output range is available only with V DD ≥ +14.25 V.
Specifications subject to change without notice.

–2– REV. B
 AD7243
1, 2 (VDD = +10.8 V to +16.5 V, VSS = 0 V or –10.8 V to –16.5 V, AGND = DGND = 0 V,
TIMING CHARACTERISTICS RL = 2 k⍀, CL = 100 pF. All Specifications TMIN to TMAX unless otherwise noted.)

Limit at +25ⴗC, TMIN, TMAX

Parameter (All Versions) Units Conditions/Comments
t1 3 200 ns min SCLK Cycle Time
t2 15 ns min SYNC to SCLK Falling Edge Setup Time
t3 70 ns min SYNC to SCLK Hold Time
t4 0 ns min Data Setup Time
t5 40 ns min Data Hold Time
t6 0 ns min SYNC High to LDAC Low
t7 20 ns min LDAC Pulsewidth
t8 0 ns min LDAC High to SYNC Low
t9 20 ns min CLR Pulsewidth
t104, 5 160 ns max SCLK Falling Edge to SDO Valid
t114, 6 >t5 ns min SCLK Falling Edge to SDO Invalid
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 7 & 8.
3
SCLK mark/space ratio range is 40/60 to 60/40.
4
SDO load capacitance is no greater than 50 pF.
5
At 25°C t10 is 130 ns max.
6
Guaranteed by design.

ABSOLUTE MAXIMUM RATINGS 1 Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

(TA = +25°C unless otherwise noted) Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
VDD to AGND, DGND . . . . . . . . . . . . . . . . . –0.3 V to +17 V Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
VSS to AGND, DGND . . . . . . . . . . . . . . . . . +0.3 V to –17 V Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V NOTES
VOUT2 to AGND . . . . . . . . . . . . . . . . . . . –6 V to VDD + 0.3 V 1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD nent damage to the device. This is a stress rating only; functional operation of the
REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V tions for extended periods may affect device reliability. Only one Absolute
SDO to DGND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Maximum Rating may be applied at any time.
Operating Temperature Range 2
The outputs may be shorted to voltages in this range provided the power dissipation
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C of the package is not exceeded. Short circuit current is typically 80 mA.
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD7243 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.

REV. B –3–
AD7243
TERMINOLOGY Relative Accuracy (Linearity)
Bipolar Zero Error Relative Accuracy, or endpoint linearity, is a measure of the
Bipolar Zero Error is the voltage measured at VOUT when the maximum deviation of the DAC transfer function from a
DAC is configured for bipolar output and loaded with all 0s straight line passing through the endpoints of the transfer func-
(Two’s Complement Coding) or with 1000 0000 0000 (Offset tion. It is measured after allowing for zero and full-scale errors
Binary Coding). It is due to a combination of offset errors in the and is expressed in LSBs or as a percentage of full-scale reading.
DAC, amplifier and mismatch between the internal gain resis-
Single Supply Linearity and Gain Error
tors around the amplifier.
The output amplifier on the AD7243 can have true negative off-
Full-Scale Error sets even when the part is operated from a single +15 V supply.
Full-Scale Error is a measure of the output error when the am- However, because the negative supply rail (VSS) is 0 V, the out-
plifier output is at full scale (for the bipolar output range full put cannot actually go negative. Instead, when the output offset
scale is either positive or negative full scale). It is measured with voltage is negative, the output voltage sits at 0 V, resulting in the
respect to the reference input voltage and includes the offset transfer function shown in Figure 1.
errors.
Digital-to-Analog Glitch Impulse
This is the voltage spike that appears at VOUT when the digital
OUTPUT
code in the DAC latch changes, before the output settles to its VOLTAGE
final value. The energy in the glitch is specified in nV secs, and
is measured for an all codes change from 0000 0000 0000 to
1111 1111 1111 and vice versa.
0V
Digital Feedthrough
This is a measure of the voltage spike that appears on VOUT as a
NEGATIVE
OFFSET { DAC CODE

result of feedthrough from the digital inputs on the AD7243. It

is measured with LDAC held high. Figure 1. Effect of Negative Offset (Single Supply)

AD7243 PIN FUNCTION DESCRIPTIONS (DIP and SOIC PIN NUMBERS)

Pin Mnemonic Description

1 REFIN Voltage Reference Input. It is internally buffered before being applied to the DAC. The nominal reference
voltage for specified operation of the AD7243 is 5 V.
2 REFOUT Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part -
using its internal reference, REFOUT should be connected to REFIN.
3 CLR Clear, Logic Input. Taking this input low sets VOUT to 0 V in both unipolar ranges and the two’s complement
bipolar range and to –REFIN in the offset binary bipolar range.
4 BIN/COMP Logic Input. This input selects the data format to be either binary or two’s complement. In both unipolar
ranges, natural binary format is selected by connecting this input to a Logic “0.” In the bipolar configuration,
offset binary format is selected with a Logic “0” while a Logic “1” selects two’s complement format.
5 SCLK Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
6 SDIN Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
7 SYNC Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readiness for a
new data word.
8 DGND Digital Ground. Ground reference for all digital circuitry.
9 LDAC Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of this
signal or alternatively if this line is permanently low, an automatic update mode is selected whereby the DAC
is updated on the 16th falling SCLK pulse.
10 DCEN Daisy-Chain Enable, Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise
this pin must be connected low.
11 SDO Serial Data Out, Logic Output. With DCEN at Logic “1” this output is enabled, and the serial data in the
input shift register is clocked out on each falling SCLK edge.
12 AGND Analog Ground. Ground reference for all analog circuitry.
13 ROFS Output Offset Resistor for the amplifier. It is connected to VOUT for the +5 V range, to AGND for the +10 V
range and to REFIN for the –5 V to +5 V range.
14 VOUT Analog Output Voltage. This is the buffer amplifier output voltage. Three different output voltage ranges can
be chosen: 0 V to +5 V, 0 to +10 V and –5 V to +5 V.
15 VSS Negative Power Supply (used for the output amplifier only, may be connected to 0 V for single supply
operation or to –12 V to –15 V for dual supplies).
16 VDD Positive Power Supply (+12 V to +15 V).

–4– REV. B
 AD7243
TERMINOLOGY (Continued) Internal Reference
This “knee” is an offset effect, not a linearity error, and the The AD7243 has an on-chip temperature compensated buried
transfer function would have followed the dotted line if the out- Zener reference which is factory trimmed to 5 V ± 50 mV. The
put voltage could have gone negative. reference voltage is provided at the REFOUT pin. This refer-
Normally, linearity is measured between zero (all 0s input code) ence can be used to provide the reference voltage for the D/A
and full scale (all 1s input code) after offset and full scale have converter (by connecting the REFOUT pin to the REFIN pin.)
been adjusted out or allowed for, but this is not possible in The reference voltage can also be used as a reference for other
single supply operation if the offset is negative, due to the knee components and is capable of providing up to 500 µA to an ex-
in the transfer function. Instead, linearity of the AD7243 in the ternal load. The maximum recommended capacitance on
unipolar mode is measured between full scale and the lowest REFOUT for normal operation is 50 pF. If the reference is re-
code which is guaranteed to produce a positive output voltage. quired for external use with capacitive loads greater than 50 pF
This code is calculated from the maximum specification for then it should be decoupled to AGND with a 200 Ω resistor in
negative offset. For the A and B versions the linearity is mea- series with a parallel combination of a 10 µF tantalum capacitor
sured between Codes 3 and 4095. For the S grade, linearity is and a 0.1 µF ceramic capacitor.
measured between Code 5 and Code 4095.
Differential Nonlinearity
200⍀
Differential Nonlinearity is the difference between the measured REFOUT EXT
LOAD
change and the ideal 1 LSB change between any two adjacent 10␮F 0.1␮F
codes. A specified differential nonlinearity of ± 1 LSB or less
over the operating temperature range ensures monotonicity.
Unipolar Offset Error Figure 3. Reference Decoupling Scheme
Unipolar Offset Error is the measured output voltage from External Reference
VOUT with all zeros loaded into the DAC latch when the DAC is In some applications, the user may require a system reference or
configured for unipolar output. It is due to a combination of the some other external reference to drive the AD7243. References
offset errors in the DAC and output amplifier. such as the AD586 provide an ideal external reference source
PIN CONFIGURATION (see Figure 10). The REFIN voltage is internally buffered by a
DIP and SOIC unity gain amplifier before being applied to the D/A converter.
The D/A converter is scaled for a 5 V reference and the device is
REFIN 1 16 VDD
tested with 5 V applied to REFIN. Other reference voltages may
be used with degraded performance. Figure 4 shows the typical
2 15 VSS
REFOUT degradation in linearity vs. REFIN.
CLR 3 AD7243 14 VOUT
1.0
BIN/COMP 4 13 ROFS
TOP VIEW VDD = +15V
0.9
(Not to Scale) VSS = –15V
SCLK 5 12 AGND TA = +25ⴗC
0.8
LINEARITY ERROR – LSBs

SDIN 6 11 SDO
0.7

SYNC 7 10 DCEN 0.6

DGND 8 9 LDAC 0.5

0.4
INL
CIRCUIT INFORMATION 0.3

D/A Section 0.2

The AD7243 contains a 12-bit voltage mode D/A converter 0.1
DNL

consisting of highly stable thin film resistors and high speed

0.0
NMOS single-pole, double-throw switches. The output voltage 2 3 4 5 6 7 8 9
from the converter has the same polarity as the reference volt- REFIN – Volts

age, REFIN, allowing single supply operation.

Figure 4. Typical Linearity vs. REFIN Voltage
2R 2R
R OFS Op Amp Section
The output of the voltage mode D/A converter is buffered by a
R R R R R VOUT noninverting CMOS amplifier. The ROFS input allows three out-
put voltage ranges to be selected. The buffer amplifier is capable
2R 2R 2R 2R 2R 2R of developing +10 V across a 2 kΩ load to AGND.
DB0 DB1 DB9 DB10 DB11
The output amplifier can be operated from a single +12 V to
+15 V supply by tying VSS = 0 V.
REFIN* SHOWN FOR ALL 1S
AGND ON DAC The amplifier can also be operated from dual supplies to allow
*BUFFERED REFIN VOLTAGE an additional bipolar output range of –5 V to +5 V. Dual supplies are
necessary for the bipolar output range but can also be used for
Figure 2. D/A Simplified Circuit Diagram the unipolar ranges to give faster settling time to voltages near

REV. B –5–
AD7243
0 V, to allow full sink capability of 2.5 mA over the entire circuitry is shown in Figure 6. Serial data on the SDIN input is
output range and to eliminate the effects of negative offsets on loaded to the input register under control of DCEN, SYNC and
the transfer characteristic (outlined previously). A plot of the SCLK. When a complete word is held in the shift register, it
output sink capability of the amplifier is shown in Figure 5. may then be loaded into the DAC latch under control of
LDAC. Only the data in the DAC latch determines the analog
3 output on the AD7243.
The DCEN (daisy-chain enable) input is used to select either a
VSS = –15V standalone mode or a daisy-chain mode. The loading format is
2 slightly different depending on which mode is selected.
I SINK – mA

VSS = 0V
Serial Data Loading Format (Standalone Mode)
With DCEN at Logic 0 the standalone mode is selected. In this
mode a low SYNC input provides the frame synchronization
1
signal which tells the AD7243 that valid serial data on the SDIN
input will be available for the next 16 falling edges of SCLK. An
internal counter/decoder circuit provides a low gating signal so
0 that only 16 data bits are clocked into the input shift register.
0 2 4 6 8 10
OUTPUT VOLTAGE – Volts
After 16 SCLK pulses the internal gating signal goes inactive
(high) thus locking out any further clock pulses. Therefore, ei-
Figure 5. Amplifier Sink Current ther a continuous clock or a burst clock source may be used to
clock in the data.
DIGITAL INTERFACE The SYNC input should be taken high after the complete 16-bit
The AD7243 contains an input serial to parallel shift register word is loaded in.
and a DAC latch. A simplified diagram of the input loading

DCEN
SYNC

RESET EN
÷ 16 GATING
COUNTER/ SIGNAL
DECODER GATED
SCLK INPUT SHIFT REGISTER (16 BITS)
SCLK
SDO
SDIN

AUTO – UPDATE
CIRCUITRY

LDAC DAC LATCH (12 BITS)

CLR

Figure 6. Simplified Loading Structure

t1

SCLK

t2
t3

SYNC

t4 t5

DB11 DB0
SDIN DB15* DB14* DB13* DB12*
MSB LSB
t6 t7 t8

LDAC

t9

CLR

* = DON'T CARE

Figure 7. Timing Diagram (Standalone Mode)

–6– REV. B
 AD7243
Although 16 bits of data are clocked into the input register, only SYNC is low. The data is clocked into the register on each fall-
the latter 12 bits get transferred into the DAC latch. The first 4 ing SCLK edge after SYNC going low. If more than 16 clock
bits in the 16 bit stream are don’t cares since their value does pulses are applied, the data ripples out of the shift register and
not affect the DAC latch data. Therefore, the data format is 4 appears on the SDO line. By connecting this line to the SDIN
don’t cares followed by the 12-bit data word with the LSB as input on the next AD7243 in the chain, a multi-DAC interface
the last bit in the serial stream. may be constructed. Sixteen SCLK pulses are required for each
There are two ways in which the DAC latch and hence the ana- DAC in the system. Therefore, the total number of clock cycles
log output may be updated. The status of the LDAC input is must equal 16N where N is the total number of devices in the
examined after SYNC is taken low. Depending on its status, one chain. When the serial transfer to all devices is complete, SYNC
of two update modes is selected. should be taken high. This prevents any further data being
clocked into the input register.
If LDAC = 0, then the automatic update mode is selected. In
this mode the DAC latch and analog output are updated auto- A continuous SCLK source may be used if it can be arranged
matically when the last bit in the serial data stream is clocked in. that SYNC is held low for the correct number of clock cycles.
The update thus takes place on the sixteenth falling SCLK edge. Alternatively, a burst clock containing the exact number of clock
cycles may be used and SYNC taken high some time later.
If LDAC = 1, then the automatic update is disabled and the
DAC latch is updated by taking LDAC low any time after the When the transfer to all input registers is complete, a common
16-bit data transfer is complete. The update now occurs on the LDAC signal updates all DAC latches with the lower 12 bits of
falling edge of LDAC. Note that the LDAC input must be taken data in each input register. All analog outputs are therefore up-
back high again before the next data transfer is initiated. dated simultaneously on the falling edge of LDAC.

Serial Data Loading Format (Daisy-Chain Mode) Clear Function (CLR)

By connecting DCEN high the daisy-chain mode is enabled. The clear function bypasses the input shift register and loads the
This mode of operation is designed for multi-DAC systems DAC Latch with all 0s. It is activated by taking CLR low. In all
where several AD7243s may be connected in cascade (see Fig- ranges except the Offset Binary bipolar range (–5 V to +5 V) the
ure 16). In this mode the internal gating circuitry on SCLK is output voltage is reset to 0 V. In the offset binary bipolar range
disabled, and a serial data output facility is enabled. The inter- the output is set to –REFIN. The clear function is especially
nal gating signal is permanently active (low) so that the SCLK useful at power-up as it enables the output to be reset to a
signal is continuously applied to the input shift register when known state.

t1

SCLK

t2 t3

SYNC

t4 t5

DB11 (N) DB0 (N) DB15* DB11 (N + 1) DB0 (N + 1)

SDIN DB15 (N)*
MSB LSB (N + 1) MSB LSB
t 10
t 11

DB11 (N) DB0 (N)

SDO DB15 (N)*
MSB LSB
t6 t7 t8
UNDEFINED
LDAC

t9
CLR

* = DON'T CARE

Figure 8. Timing Diagram (Daisy-Chain Mode)

REV. B –7–
AD7243
APPLYING THE AD7243 Unipolar (0 V to +5 V) Configuration
Power Supply Decoupling The 0 V to +5 V output voltage range is achieved by connecting
To achieve optimum performance when using the AD7243, the ROFS to VOUT. Once again, the AD7243 can be operated using
VDD and VSS lines should each be decoupled to DGND using either single or dual supplies. The table for output voltage vs.
0.1 µF capacitors. In noisy environments it is recommended digital code is as in Table I, with 2REFIN replaced by REFIN.
that 10 µF capacitors be connected in parallel with the 0.1 µF Note, for this range, 1 LSB = REFIN • (2–12 ) = (REFIN/4096).
capacitors.
Bipolar (ⴞ5 V) Configuration
The internal scaling resistors provided on the AD7243 allow The bipolar configuration for the AD7243, which gives an out-
several output voltage ranges. The part can produce unipolar put range of –5 V to +5 V, is achieved by connecting ROFS to
output ranges of 0 V to +5 V or 0 V to +10 V and a bipolar out- REFIN. The AD7243 must be operated from dual supplies to
put range of ± 5 V. Connections for the various ranges are out- achieve this output voltage range. Either offset binary or two’s
lined below. complement data format may be selected. Figure 10 shows the
Unipolar (0 V to +10 V) Configuration connection diagram for bipolar operation. An AD586 provides
The first of the configurations provides an output voltage range the reference voltage for the DAC but this could be provided by
of 0 V to +10 V. This is achieved by connecting the output off- the on-chip reference by connecting REFOUT to REFIN.
set resistor ROFS (Pin 13) to AGND. Natural Binary data format VDD
is selected by connecting BIN/COMP (Pin 4) to DGND. In this
configuration, the AD7243 can be operated using either single VDD
or dual supplies. Note that the VDD supply must be ≥+14.25 V
ROFS
for this range in order to maintain sufficient amplifier head-
+VIN 2R 2R
room. Dual supplies may be used to improve settling time and
give increased current sink capability for the amplifier. Figure 9 VOUT
shows the connection diagram for unipolar operation of the AD586 VOUT DAC
AD7243. Table I shows the digital code vs. analog output for –5V TO + 5V

this configuration. REFIN AD7243*

GND
VDD BIN/ COMP DGND AGND VSS
VDD

VDD VSS

*ADDITIONAL PINS OMITTED FOR CLARITY

AD7243*
REFOUT 2R ROFS
Figure 10. Bipolar Configuration with External Reference

2R
Bipolar Operation (Two’s Complement Data Format)
VOUT
The AD7243 is configured for two’s complement data format
DAC 0V TO + 10V by connecting BIN/COMP (Pin 4) high. The analog output vs.
REFIN digital code is shown in Table II.

BIN/
DGND AGND VSS Table II. Two’s Complement Bipolar Code Table
COMP
0V OR VSS Input Data Word
*ADDITIONAL PINS OMITTED FOR CLARITY
MSB LSB Analog Output, VOUT
XXXX 0111 1111 1111 +REFIN × (2047/2048)
Figure 9. Unipolar (0 V to +10 V) Configuration XXXX 0000 0000 0001 +REFIN × (1/2048)
XXXX 0000 0000 0000 0V
Table I. Unipolar Code Table (0 V to +10 V Range) XXXX 1111 1111 1111 –REFIN × (1/2048)
XXXX 1000 0000 0001 –REFIN × (2047/2048)
Input Data Word
XXXX 1000 0000 0000 –REFIN × (2048/2048) = –REFIN
MSB LSB Analog Output, VOUT
X = Don’t Care.
XXXX 1111 1111 1111 +2 REFIN × (4095/4096) Note: 1 LSB = REFIN/2048.
XXXX 1000 0000 0001 +2 REFIN × (2049/4096)
Bipolar Operation (Offset Binary Data Format)
XXXX 1000 0000 0000 +2 REFIN × (2048/4096) = +REFIN
The AD7243 is configured for Offset Binary data format by
XXXX 0111 1111 1111 +2 REFIN × (2047/4096)
connecting BIN/COMP (Pin 4) low. The analog output vs. digi-
XXXX 0000 0000 0001 +2 REFIN × (1/4096)
tal code may be obtained by inverting the MSB in Table II.
XXXX 0000 0000 0000 0V
X = Don’t Care.
Note: 1 LSB = 2 REFIN/4096.

–8– REV. B
 AD7243
MICROPROCESSOR INTERFACING AD7243–DSP56000 Interface
Microprocessor interfacing to the AD7243 is via a serial bus A serial interface between the AD7243 and the DSP56000 is
which uses standard protocol compatible with DSP processors shown in Figure 12. The DSP56000 is configured for Normal
and microcontrollers. The communications channel requires a Mode Asynchronous operation with Gated Clock. It is also set
three-wire interface consisting of a clock signal, a data signal up for a 16-bit word with SCK and SC2 as outputs and the FSL
and a synchronization signal. The AD7243 requires a 16-bit control bit set to a “0.” SCK is internally generated on the
data word with data valid on the falling edge of SCLK. For all DSP56000 and applied to the AD7243 SCLK input. Data from
the interfaces, the DAC update may be done automatically the DSP56000 is valid on the falling edge of SCK. The SC2
when all the data is clocked in or it may be done under control output provides the framing pulse for valid data. This line must
of LDAC. be inverted before being applied to the SYNC input of the
Figures 11 to 16 show the AD7243 configured for interfacing to AD7243.
a number of popular DSP processors and microcontrollers. The LDAC input of the AD7243 is connected to DGND so the
AD7243–ADSP-2101/ADSP-2102 Interface update of the DAC latch takes place automatically on the six-
Figure 11 shows a serial interface between the AD7243 and the teenth falling edge of SCLK. An external timer could also be
ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/ used as in the previous interface if an external update is
ADSP-2102 contains two serial ports, and either port may be required.
used in the interface. The data transfer is initiated by TFS going
low. Data from the ADSP-2101/ADSP-2102 is clocked into the LDAC
AD7243 on the falling edge of SCLK. When the data transfer is DSP56000
complete, TFS is taken high. In the interface shown the DAC is AD7243*
updated using an external timer which generates an LDAC
SCK SCLK
pulse. This could also be done using a control or decoded ad-
dress line from the processor. Alternatively, the LDAC input STD SDIN

could be hard wired low and in this case the update takes place SC2 SYNC
automatically on the sixteenth falling edge of SCLK.
*ADDITIONAL PINS OMITTED FOR CLARITY

TIMER
Figure 12. AD7243–DSP56000 Interface
AD7243–TMS32020 Interface
ADSP - 2101/ LDAC Figure 13 shows a serial interface between the AD7243 and the
ADSP - 2102*
TMS32020 DSP processor. In this interface, the CLKX and
AD7243* FSX signals for the TMS32020 should be generated using ex-
TFS SYNC ternal clock/timer circuitry. The FSX pin of the TMS32020
must be configured as an input. Data from the TMS32020 is
SCLK SCLK
valid on the falling edge of CLKX.
DT SDIN The clock/timer circuitry generates the LDAC signal for the
AD7243 to synchronize the update of the output with the serial
*ADDITIONAL PINS OMITTED FOR CLARITY
transmission. Alternatively, the automatic update mode may be
selected by connecting LDAC to DGND.
Figure 11. AD7243–ADSP-2101/ADSP-2102 Interface
CLOCK/
LDAC
TIMER
TMS32020
AD7243*
FSX SYNC

CLKX SCLK

DX SDIN

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 13. AD7243–TMS32020 Interface

REV. B –9–
AD7243
AD7243–87C51 Interface Figure 15 shows the LDAC input of the AD7243 hardwired
A serial interface between the AD7243 and the 87C51 low. As a result, the DAC latch and the analog output of the
microcontroller is shown in Figure 14. TXD of the 87C51 drives DAC will be updated on the sixteenth falling edge of SCK after
SCLK of the AD7243, while RXD drives the serial data line of the respective SYNC signal has gone low. Alternatively, the
the part. The SYNC signal is derived from the port line P3.3. scheme used in previous interfaces, whereby the LDAC input is
The 87C51 provides the LSB of its SBUF register as the first bit driven from a timer, can be used.
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that
the don’t care bits are the first to be transmitted to the AD7243 LDAC
68HC11*
and the last bit to be sent is the LSB of the word to be loaded to AD7243*
the AD7243. When data is to be transmitted to the part, P3.3 is
taken low. Data on RXD is valid on the falling edge of TXD. PC7 SYNC
The 87C51 transmits its serial data in 8-bit bytes with only eight SCK SCLK
falling clock edges occurring in the transmit cycle. To load data SDIN
MOSI
to the AD7243, P3.3 is left low after the first eight bits are trans-
ferred and a second byte of data is then transferred serially to the *ADDITIONAL PINS OMITTED FOR CLARITY
AD7243. When the second serial transfer is complete, the P3.3
line is taken high. Figure 15. AD7243–68HC11 Interface
Figure 14 shows the LDAC input of the AD7243 hard wired Multiple DAC Daisy-Chain Interface
low. As a result, the DAC latch and the analog output will be up- A multi-DAC serial interface is shown in Figure 16. This
dated on the sixteenth falling edge of TXD after the SYNC sig- scheme may be used with all of the interfaces previously dis-
nal for the DAC has gone low. Alternatively, the scheme used in cussed if more than one DAC is required in a system. To enable
previous interfaces, whereby the LDAC input is driven from a the facility the DCEN pin must be connected high on all de-
timer, can be used. vices, including the last device in the chain.

PA0

LDAC MICROCONTROLLER SDIN

87C51*
AD7243* AD7243*
PA1 SCLK
VDD
P3.3 SYNC PA2 SYNC
TXD SCLK PA3 LDAC DCEN

RXD SDIN SDO

*ADDITIONAL PINS OMITTED FOR CLARITY SDIN

AD7243*
Figure 14. AD7243–87C51 Interface
SCLK
AD7243–68HC11 Interface VDD
SYNC
Figure 15 shows a serial interface between the AD7243 and the LDAC DCEN
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of SDO
the AD7243 while the MOSI output drives the serial data line of
the AD7243. The SYNC signal is derived from a port line (PC7 SDIN
shown).
AD7243*
For correct operation of this interface, the 68HC11 should be SCLK
configured such that its CPOL bit is a 0 and its CPHA bit is a 1. VDD
SYNC
When data is to be transmitted to the part, PC7 is taken low.
LDAC DCEN
When the 68HC11 is configured like this, data on MOSI is valid SDO
*ADDITIONAL PINS OMITTED FOR CLARITY
on the falling edge of SCK. The 68HC11 transmits its serial data
in 8-bit bytes with only eight falling clock edges occurring in the Figure 16. AD7243 Daisy-Chain Configuration
transmit cycle. To load data to the AD7243, PC7 is left low after
the first eight bits are transferred and a second byte of data is
then transferred serially to the AD7243. When the second serial
transfer is complete, the PC7 line is taken high.

–10– REV. B
 AD7243
Common clock, data, and synchronization signals are applied to Figure 17 shows a 4-channel isolated interface using the
all DACs in the chain. The loading sequence starts by taking AD7243. The DCEN pin must be connected high to enable the
SYNC low. The data is then clocked into the input registers on daisy-chain facility. Four channels with 12-bit resolution are
the falling edge of SCLK. Sixteen clock pulses are required for provided in the circuit shown, but this may be expanded to ac-
each DAC in the chain. The data ripples through the input reg- commodate any number of DAC channels without any extra
isters with the first 16-bit word filling the last register in the isolation circuitry.
chain after 16N clock pulses where N = the total number of The sequence of events to program the output channels is as
DACs in the chain. follows:
When valid data has been loaded into all the registers, the 1. Take the SYNC line low.
SYNC input should be taken high and a common LDAC pulse
used to update all the DACs simultaneously. 2. Transmit the data as four 16-bit words. A total of 64 clock
pulses is required to clock the data through the chain.
APPLICATIONS 3. Take the SYNC line high.
OPTO-ISOLATED INTERFACE 4. Pulse the LDAC line low. This updates all output channels
In many process control type applications it is necessary to pro- simultaneously on the falling edge of LDAC.
vide an isolation barrier between the controller and the unit be-
ing controlled. Opto-isolators can provide voltage isolation in To reduce the number of opto-couplers, the LDAC line could
excess of 3 kV. The serial loading structure of the AD7243 be driven from a one shot which is triggered by the rising edge
makes it ideal for opto-isolated interfaces as the number of in- on the SYNC line. A low level pulse of 50 ns duration or greater
terface lines is kept to a minimum. is all that is required to update the outputs.

VDD

DATA OUT
SDIN
VDD
CONTROLLER
AD7243*
CLOCK OUT SCLK VOUT
VDD VOUT(A)
VDD
SYNC

LDAC DCEN
SYNC OUT SDO
VDD
SDIN

CONTROL OUT AD7243*

SCLK VOUT
VDD VOUT(B)
SYNC
QUAD OPTO-COUPLER LDAC DCEN
SDO

SDIN

AD7243*
SCLK VOUT
VDD VOUT(C)
SYNC

LDAC DCEN
SDO

SDIN
AD7243*
SCLK VOUT
VDD VOUT(D)
SYNC

LDAC DCEN
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 17. Four-Channel Opto-lsolated Interface

REV. B –11–
AD7243 Data Sheet

OUTLINE DIMENSIONS
0.775
0.755
0.735

16 9
0.280
PIN 1 0.250
INDICATOR 1
8
0.240

TOP VIEW
0.100 0.325
BSC 0.195 0.310
0.210 0.130 0.300
MAX SIDE VIEW 0.115
0.015
0.150 MIN 0.015
0.130 GAUGE END VIEW
PLANE 0.012
0.115 SEATING 0.010
PLANE
0.022 0.008
0.021 0.430
0.018 0.070 0.016 MAX
0.015 0.045 0.060 0.011
0.039 0.055

03-07-2014-D
0.030

COMPLIANT TO JEDEC STANDARDS MS-001-BB

Figure 18. 16-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body
(N-16)
Dimensions shown in inches
0.005 (0.13) MIN 0.098 (2.49) MAX

16 9
0.310 (7.87)
1 0.220 (5.59)
8

PIN 1
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.060 (1.52)
0.200 (5.08) 0.015 (0.38)
MAX
0.150
0.200 (5.08) (3.81)
0.125 (3.18) MIN
SEATING 0.015 (0.38)
0.023 (0.58) 0.070 (1.78) PLANE 15°
0.008 (0.20)
0.014 (0.36) 0.030 (0.76) 0°

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 19. 16-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-16)
Dimensions shown in inches and (millimeters)

Rev. B | Page 12 of 13
Data Sheet AD7243
10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)

BSC 45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

03-27-2007-B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 20. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Temperature Relative Accuracy Package
Model1 Range (LSB) Package Description Option
AD7243ANZ –40°C to +85°C ±1 16-Lead Plastic Dual In-Line Package [PDIP] N-16
AD7243BNZ –40°C to +85°C ±1/2 16-Lead Plastic Dual In-Line Package [PDIP] N-16
AD7243ARZ –40°C to +85°C ±1 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7243ARZ-REEL –40°C to +85°C ±1 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD7243BQ –40°C to +85°C ±1/2 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16
1
Z = RoHS Compliant Part.

REVISION HISTORY
3/2020—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 12
Moved Ordering Guide Section ................................................... 13
Changes to Ordering Guide .......................................................... 13

6/2000—Rev. 0 to Rev. A

©2020 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D01498-3/20(B)

Rev. B | Page 13 of 13