Assignment: Key Concepts in Computer
Organization and Architecture
1. Signed and Two’s-Complement Representations
Overview
In digital systems, representing both positive and negative integers is a fundamental
requirement. Computers use binary, a base-2 numeral system, where each bit has two
possible values (0 or 1). Since standard binary naturally supports only positive integers,
special representations are necessary for signed numbers. Among several techniques, the
two’s-complement representation stands out for its simplicity and efficiency in arithmetic
operations.
Historical Context
The evolution of signed number representations started with sign-and-magnitude and one’s
complement methods. However, both had limitations, such as the presence of two
representations for zero and complicated arithmetic logic. The two’s-complement system
emerged as the superior alternative due to its computational advantages and is now the
standard in almost all modern processors.
Sign-and-Magnitude Representation
In this method, the most significant bit (MSB) is used as the sign bit:
- ‘0’ indicates a positive number.
- ‘1’ indicates a negative number.
For example, using 8 bits:
- +10 = 00001010
- -10 = 10001010
Issues:
- Arithmetic operations become complex.
- Two representations of zero (00000000 and 10000000).
One’s Complement
This method flips all bits of a positive number to represent the negative version.
Example:
- +5 = 00000101
- -5 = 11111010
Issue:
- Requires end-around carry in addition.
- Still has two representations of zero.
Two’s-Complement Representation
This method resolves the drawbacks of the earlier schemes. It provides a single
representation for zero and simplifies arithmetic operations by allowing the same circuitry
to handle both addition and subtraction.
How It Works:
1. Write the binary representation of the positive number.
2. Invert the digits (one’s complement).
3. Add 1 to the result.
Example: Represent -18 in 8-bit two’s complement:
- +18 = 00010010
- Invert: 11101101
- Add 1: 11101110
Properties:
- Single zero representation (00000000)
- Easy arithmetic logic implementation
- The leftmost bit still indicates sign (0 = positive, 1 = negative)
Range of Values:
- For n-bit numbers: from -2^(n-1) to 2^(n-1) – 1
- Example (8-bit): from -128 to +127
Arithmetic Operations
Two’s complement arithmetic allows signed integers to be added and subtracted using the
same binary addition logic, greatly simplifying hardware design.
Overflow Detection:
- Occurs when the result exceeds the allowed bit range.
- In hardware, overflow can be detected by examining the carry into and out of the sign bit.
Applications
- Arithmetic Logic Units (ALUs)
- Compilers and programming languages (e.g., C/C++ use two’s complement as default
signed integer representation)
- Embedded systems and microcontrollers
Real-World Example
Suppose a banking application subtracts balances using signed integers. If two’s
complement is not used, the complexity increases and can lead to errors in financial
computations.
Graphical Representation (Figure Placeholder):
[Insert a number line showing binary representations from -128 to 127 in 8-bit two’s-
complement format.]
2. Priority Interrupts
Overview
Interrupts are crucial in modern computing for handling asynchronous events. Instead of
continuous polling, which is inefficient, systems use interrupts to respond immediately to
high-priority conditions. However, when multiple interrupts occur simultaneously or in
quick succession, a priority mechanism determines the execution order.
Types of Interrupts
- Hardware Interrupts: Generated by I/O devices (e.g., keyboard, mouse).
- Software Interrupts: Triggered by programs or operating system events.
Interrupt Handling
An interrupt signal causes the CPU to pause the current execution and service the interrupt
by executing an Interrupt Service Routine (ISR). Once the ISR completes, the CPU resumes
normal execution.
Need for Priority
Without priority, interrupt requests might be processed in random order, delaying critical
responses. Priority interrupts ensure that the most urgent tasks are handled first.
Fixed Priority Scheme
- Devices are assigned static priority levels.
- Example: Timer > Disk I/O > Keyboard
Rotating (Dynamic) Priority Scheme
- Priorities are adjusted after each interrupt to ensure fairness.
- Prevents lower-priority devices from being starved.
Daisy Chaining
- A hardware-based method where devices are connected in series.
- A device closer to the CPU in the chain has a higher priority.
Polling Method
- Software method where the CPU checks each device in sequence.
- Slower than hardware-based methods but easier to implement.
Nested Interrupts
- High-priority interrupts can interrupt a running ISR.
- Requires a stack-based context-saving mechanism.
Example
Imagine a real-time patient monitoring system:
- Heartbeat sensor interrupt (high priority)
- Temperature sensor interrupt (low priority)
If both occur, the heartbeat sensor must be serviced immediately to avoid missing a critical
signal.
Challenges and Considerations
- Interrupt Latency: Delay between request and service start.
- Context Switching Overhead: Saving and restoring state during ISR calls.
- Starvation: Low-priority devices may never get service.
Applications
- Operating Systems (e.g., Windows, Linux interrupt controllers)
- Real-Time Systems (robotics, medical devices)
- Embedded Systems (e.g., automotive ECUs)
Diagram Placeholder:
[Insert interrupt vector table and priority level diagram showing interrupt flow and
servicing.]
3. Asynchronous Data Transfer
Overview
Data transfer is fundamental to computing. It occurs between the CPU, memory, and
peripheral devices. In asynchronous data transfer, the devices involved do not share a
common clock signal. This is in contrast to synchronous transfer, where both sender and
receiver are synchronized via a shared clock.
Why Asynchronous Transfer?
- Devices often operate at different speeds.
- Synchronizing clocks across physically separated systems is difficult.
- Provides flexibility in data communication.
Mechanisms
1. Handshaking Protocol
A robust method using control signals such as:
- Data Valid
- Acknowledge
Steps:
- Sender places data and raises 'Data Valid' signal.
- Receiver reads data and raises 'Acknowledge'.
- Sender lowers the 'Data Valid' signal.
- Receiver lowers 'Acknowledge'.
Types:
- Source-Initiated Transfer: Sender initiates the handshake.
- Destination-Initiated Transfer: Receiver requests data.
2. Start-Stop Communication
Used in serial protocols such as UART:
- Data is framed with start and stop bits.
- No clock is shared; timing is recovered from data stream.
Framing Example:
- Start bit (0)
- 8 Data bits
- Parity bit (optional)
- Stop bit (1)
Applications:
- RS-232 Serial Communication
- USB, Bluetooth, UART, and SPI interfaces
Timing Diagrams:
[Insert diagram showing asynchronous handshaking signals and UART transmission]
Challenges
- Timing mismatches can cause data corruption.
- Requires error detection/correction (parity, checksums).
Advantages
- Flexibility in device speed and distance.
- Simpler wiring compared to synchronous systems.
Disadvantages
- More control overhead (start/stop bits, handshake signals).
- Typically slower than synchronous communication.
Applications in Real Life
- Communication between computers and peripheral devices.
- Embedded systems (e.g., microcontrollers with sensors).
- Networking protocols like HTTP over TCP/IP rely on asynchronous mechanisms.
Comparison with Synchronous Transfer:
| Feature | Synchronous | Asynchronous |
|------------------|-----------------------|---------------------------|
| Clock Required | Yes | No |
| Speed | Faster | Slower |
| Complexity | Higher | Lower |
| Flexibility | Less (fixed timing) | High |
| Use Cases | Memory Bus, CPUs | Serial Ports, USB, UART |
Conclusion
Conclusion
The discussed concepts form the backbone of digital computation and architecture. Signed
number representation using two’s complement is essential for efficient arithmetic
processing. Priority interrupt mechanisms ensure that critical system components receive
timely attention, which is vital for real-time performance. Finally, asynchronous data
transfer provides a reliable and flexible means of communication between system
components that operate independently of each other’s timing.
Understanding these mechanisms is crucial for anyone pursuing a career in computer
engineering, embedded systems, or systems programming. As systems become increasingly
complex and diverse in their interactions, mastering these fundamental principles remains
as relevant as ever.
